JPH01311338A - Data memory address generating circuit - Google Patents

Abstract

PURPOSE:To reduce a useless area generated in a program memory and to reduce the whole memory capacity by providing the title circuit with an address memory for storing a data address for directly accessing a data memory. CONSTITUTION:A data address having a comparatively long word length is stored in an exclusive address memory 11. On the other hand, an instruction set to which a subaddress 10A for reading out the data address from the memory 11 is stored in a program memory 10 together with an operation instruction or the like. Since only a group of data addresses is stored in the memory 11, the whole memory can be effectively used. Since an address with a sort word length for reading out the data address from the memory 11 is used together with the operation instruction on the memory 10 side, the word length of a direct addressing instruction set itself can be sufficiently shortened. Consequently, the generation of an useless area in the memory 10 can be prevented and the capacity of the memory 10 itself can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is provided in a digital signal processing processor,
The present invention relates to a data memory address generation circuit used to access the data memory.

(Prior Art) Digital signal processing processors used in voice synthesis digital filters and the like are required to have the ability to calculate various numerical data as fast as possible.

As a processor that satisfies these requirements, an LSI (Large Scale Integrated Circuit) such as Texas Instruments ITMs32010 (published in the company's Digital Signal Processor User's Manual, 1985) has been developed.

FIG. 2 shows a principle diagram of a data memory address generation circuit in such a conventional digital signal processing processor.

This circuit has a program memory 1, an auxiliary register 2, a selector 3, and a data memory 4.

This digital signal processing processor reads the data address of the data memory 4 from the program memory 1, outputs predetermined data from the data memory 4, and at the same time outputs the data using the arithmetic instructions read from the program memory 1 at the same time. This is a device that performs calculations.

Here, in the circuit shown in FIG. 2, the data address lA is first read out from the program memory 1, and this is output to the data memory 4 through the selector 3. On the other hand, the auxiliary register 2, and the start address IA read from the program memory 1.
' is stored in this auxiliary register 2, the start address stored in the auxiliary register 2 is incremented or decremented, thereby outputting the data address 2A, and the data memory 4 can also be accessed through the selector 3.

In this case, the method of directly accessing the data memory 4 using the data address read from the program memory 1 is called direct addressing, and the method of accessing the data memory 4 using the data address generated by the auxiliary register 2 is called indirect addressing. I'm calling.

FIG. 3 shows the format of the direct addressing instruction set and indirect addressing instruction set stored in the program memory 1.

In this way, an instruction set in which the arithmetic instruction 5 and information such as the data address IA are linked is read out from the program memory 1.

First, the direct addressing instruction set is composed of an arithmetic instruction 5 and a data address IA, as shown in FIG. Further, the indirect addressing instruction set is composed of arithmetic instructions 5 and control bits 6, as shown in FIG. 2(b).

In the case of the LSI explained earlier, the arithmetic instruction 5 is 8 bits,
Data address IA including memory chip select etc. is composed of 8 bits.

On the other hand, control bit 6 of the indirect addressing instruction set is
It consists of several bits of signals for controlling the operation of the auxiliary register, such as decrementing or incrementing, based on the start address previously stored in the auxiliary register 2 (FIG. 2). In reality, two auxiliary registers shown in FIG. 2 are provided, and the control signals for the two auxiliary registers are included in this one indirect addressing instruction set.

(Problem to be Solved by the Invention) By the way, as explained earlier, this digital signal processor is required to perform calculations at the highest possible speed, so it reads a large amount of data at the same time and performs various calculations. It is desirable to adopt so-called parallel processing.

For this purpose, for example, the data memory 4 shown in FIG.
It is conceivable to provide a plurality of data memories and output the data addresses of each data memory from the program memory 1 simultaneously and in parallel. In this case, for example, considering the direct addressing instruction set shown in Figure 3, the data address IA used to consist of 8 bits (7 bits excluding memory chip select), but this can be changed to 16 bits,
A word length of 32 bits or more is required. Of course, parallel processing requires an increase in the number of bits for arithmetic instructions.

However, if such a long word length program memory is prepared, the program memory itself will have a large capacity. Moreover, although the direct addressing instruction set and the indirect addressing instruction set are actually mixed, the actual situation is that the indirect addressing instruction set contains a relatively larger number.

Here, the indirect addressing instruction set, as explained above, does not itself include a data address and does not require a large number of control bits. Taking this into consideration, storing two types of instruction sets with different data lengths will result in an extremely large amount of wasted area in the program memory.

As a result, there is a problem in that the cost of a processor having a parallel processing function that uses two or more data memories, such as multiplication using two or more variables or ALU operation, increases.

The present invention has been made in view of the above points, and eliminates the problem of the long word length of the direct addressing instruction set of program memory, and provides a versatile digital signal processing processor with high parallel processing capability. The object of the present invention is to provide a data memory address generation circuit that realizes the following.

(Means for Solving the Problem) A data memory address generation circuit of the present invention includes an address memory storing a group of data addresses set for accessing the data memory, and a circuit for reading the data address from the address memory. and includes a sub-address with a word length shorter than the data address;
a program memory storing a set of instructions; reading the sub-address from the program memory; reading the data address from the address memory using the sub-address; and accessing the data memory using the data address. The access control circuit is characterized in that it has an access control circuit that controls the access control.

(Operation) The above device stores data addresses with a relatively long word length in a dedicated address memory. Further, the program memory stores an instruction set including a sub-address for reading a data address from the address memory together with arithmetic instructions and the like. In this way, the address memory stores only a group of data addresses, so the entire memory is used effectively. Further, on the program memory side, since a short word length address is used for reading a data address from the address memory together with an arithmetic instruction, the word length of the direct addressing instruction set itself can be made sufficiently short. As a result, the word lengths of the direct addressing instruction set and the indirect addressing instruction set are made close to each other, thereby preventing the generation of wasted areas in the program memory and reducing the capacity of the program memory itself.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of a data memory address generation circuit of the present invention.

This circuit includes a program memory 1o, an address memory 11, and four data memories 12a.

12b, 12c, and 12d, an arithmetic unit 13, and an access control circuit 14.

The access control circuit 14 outputs an address signal 14A for reading the instruction set stored in the program memory 10, and indirectly reads the data memory 12a-
This circuit controls access to 12d. The program memory 10 is a circuit composed of a read-only memory or the like that stores an instruction set including arithmetic instructions and sub-addresses in the order of their addresses. Also, address memory 11
is composed of a read-only memory or the like that accepts the sub-address IOA included in the instruction set read from the program memory 10 and outputs the data address IIA. Data addresses set for accessing the data memories 12a-12d are stored here in the order of the addresses.

Further, this device is equipped with four data memories, and the data address 11A read from the address memory 11 is
is divided into, for example, four sets of address signals a, b, c, and d of 8 bits each, and is sent to each data memory 12a to 12a.
12d.

The data read from each of the data memories 12a to 12d is transferred to the arithmetic unit 13, and predetermined parallel arithmetic processing is performed in accordance with the arithmetic instructions previously read from the program memory 10.

Note that the address memory may be created at the same time as the program memory is created. In this address memory, data addresses may be stored in consecutive numbers, or in the case of jumps, data addresses may be stored intermittently.

The circuit of the present invention having the above configuration operates as follows.

First, the access control circuit 14 outputs a predetermined address signal 14A to the program memory 10, and one instruction set is read from the program memory 10. Of the instruction set, sub-address IOA is input to address memory 11, and as a result, address memory 11 outputs a predetermined data address llA. This data address IIA is a, b as shown in the figure.

The data is divided into four parts, c and d, and input in parallel to four data memories 12a, 12b, 12c, and 12d. These four data memories 12a.

From 12b, 12c, and 12d, the above data address I
The data corresponding to IA is read out, and these are stored in the calculation unit 1.
3 is output.

The arithmetic unit 13 receives the arithmetic instruction previously read out from the program memory 10 through a circuit (not shown), performs various arithmetic operations on the four data, and executes so-called parallel processing. The results of these calculations are stored again in any of the data memories 12a to 12d as necessary, and used for calculations when the next set of instructions is read out from the program memory 10.

The above embodiments have described circuits that employ only the direct addressing method. However, in reality, indirect addressing is often used in conjunction with indirect addressing as described above.

FIG. 4 is a block diagram showing a more practical embodiment of the invention.

This circuit consists of a program memory 10, an address memory 1
1. In addition to the data memory 12 and the access control circuit 14, an address counter 15, a selector 16, a data address register 17, and an indirect address generation circuit 18 are provided.

Here, the start address IOA of the address counter 15 is read out from the program memory 10, and the address counter 15 increments, holds, or The sub address 15A is generated by decrementing the sub address 15A. This sub-address 15A is input to the address memory 11, and the data address 11A is read from the address memory 11. This data address lIA is the selector 1
It is wired to input to 6. Also, this selector 1
The output of 6 is connected to be supplied to the data memory 12, and is also connected to be output to the data address register 17.

The data address register 17 is a circuit that temporarily stores the data address 16A output from the selector 16 and supplies it to the indirect address generation circuit 18. The indirect address generation circuit 18 is a circuit that operates to decrement, hold, or increment the data address stored in the data address 17 as a start address, and the new data address 18A generated by the indirect address generation circuit 18 is also used as a selector. It is wired to input to 16.

The access control circuit 14 selects the selector 16 depending on whether the mode is direct addressing mode or indirect addressing mode.
A signal that controls the selection operation of the address memory 11 and selects either the data address output from the address memory 11 or the data address 18A output from the indirect address circuit 18 and outputs it to the data memory 12. Output. Furthermore, the decrement, hold, or increment control of the address counter 15 and the indirect address generation circuit 18 is also controlled by this signal.

The above circuit operates as follows.

First, the access control circuit 14 sends an address signal 14A to read a predetermined instruction set from the program memory 10.
supply. Assume that the instruction set read from program memory 10 is a direct addressing instruction set. In this case, the start address IOA of the address counter 15 included in the instruction set is stored and initialized in the address counter 15. At the same time, the access control circuit 14 instructs the address counter 15 to increment, hold, or decrement. Thereafter, the sub address 15A output from the address counter 15 is input to the address memory 11, and the data address 1. IA is output. The configuration of the sub-address, address memory, etc. are as described above with reference to FIG.

In the case of direct addressing mode, the selector 16 selects the data address IIA output from the address memory 11 by the access control circuit 14, and selects the data address IIA output from the address memory 11.
It is set to output to 2. As a result, predetermined data is read from the data memory 12,
The signal is output to the arithmetic unit 13 (not shown) as previously explained with reference to FIG.

On the other hand, in the case of indirect addressing mode, selector 1 is set in advance.
The data address 16A output from 6 is stored in the data address register 17. Then, the indirect address generation circuit 18 accepts the data address, and the access control circuit 14 decrements, holds, and
Or receive an increment instruction. As a result, the newly generated data address 18A is supplied to the data memory 12 through the selector 16. At this time, the access control circuit 14 controls the selection operation of the selector 16 and transfers the output of the indirect address generation circuit 18 to the data memory 12.
Needless to say, it is set to be supplied to In fact, when the present invention is applied to a digital signal processor, a program memory that conventionally required about 30 ROM elements can now be configured with about half as many ROM elements.

As described above, if the data memory address generation circuit is configured as shown in FIG. 4, and the address memory 11 is created simultaneously when the program memory 10 is created, the start address is set in the address counter, and the address Complex access to the data memory 12 is made possible by appropriately combining direct addressing, in which data addresses are read from memory 11 in a predetermined order, and indirect addressing mode, in which a new data address is generated based on a certain data address. . Furthermore, in the case of a jump, a new start address from the program memory 10 may be stored in the address counter 15, and the address memory may be read.

(Effects of the Invention) According to the data memory address generation circuit of the present invention described above, an address memory is provided for storing data addresses for directly accessing the data memory, and the word length of the direct addressing instruction set of the program memory is shortened. Therefore, wasted areas in the program memory can be reduced, and the overall memory capacity can be reduced. This makes it possible to economically access many data memories simultaneously, and to realize a digital signal processing processor with excellent versatility and high parallel processing capability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data memory address generation circuit of the present invention, FIG. 2 is a block diagram of a conventional data memory address generation circuit, FIG. 3 is an explanatory diagram of the format of its instruction set, and FIG. 4 FIG. 2 is a block diagram showing another embodiment of the present invention. 10...Program memory, IOA...Sub address, 11...Address memory, 11A...Data address, 12A-12d...Data memory, 13...Arithmetic unit, 14...Access control Circuit, 15...Address counter, 16...Selector, 1
8...Indirect address generation circuit. Patent Applicant: Oki Electric Industry Co., Ltd. Fig. 1 Conventional data memory address generation circuit Fig. 2 Direct addressing instruction set Indirect addressing instruction set Conventional instruction set format Fig. 3 1-A The present invention Other actual users ↑, Niblock diagram Figure 4

Claims (1)

[Scope of Claims] 1. An address memory storing a group of data addresses set for accessing the data memory; and an address memory provided for reading the data address from the address memory, the address memory having a word length longer than the data address. a program memory storing a set of instructions, the sub-addresses being read from the program memory, using the sub-addresses to read the data addresses from the address memory, and using the data addresses to read the data addresses from the address memory; and an access control circuit for controlling access to the data memory. 2. An address memory that stores a group of data addresses set for accessing the data memory, and a sub-address that is prepared for reading the data address from this address memory and has a word length shorter than the data address. , a program memory storing a group of instructions; an indirect address generation circuit that receives a data address read from the address memory and generates a new data address; and a data address output from the address memory and the indirect address. a selector that selects one of the data addresses output by the generation circuit and supplies it to the data memory; and a selector that reads the data address from the address memory using the sub-address, controls the selection operation of the selector, and outputs the selected data address. A data memory address generation circuit comprising: an access control circuit that controls access to the data memory using the data address.