JPS58208981A - Address control circuit - Google Patents

Abstract

PURPOSE:To attain accessing of a memory with continuous addresses, addresses at intervals of (n), or their combinations, by counting the address at each addition for selecting a fixed adding value. CONSTITUTION:An address added and counted at an adder 7 is stored in an address register 4 for accessing a memory 1. This address is also impressed to an adder 7, where a fixed value of fixed value designating means 5 and 6 selected at a control circuit 3' is added, and the count of the next address is determined. Through the constitution above, the memory 1 is accessed with continuous addresses, addresses at intervals of (n) or their combinations, allowing to attain suitable access cycle.

Description

[Detailed description of the invention] The present invention relates to memory addressing circuits.

In digital processing, data stored in memory is often retrieved and processed every few pieces in succession. For example, fast Fourier transform is a typical example of digital signal processing. In this case, for one column of data written to the memory in the previous processing step, in the next processing step, it is necessary to successively read and calculate the contents of every few addresses in the memory. Memory addressing means generally consists of a simple register or a counter as shown in FIG. In Figure 1, 1 is memory;
2 is an address designation counter for the memory 1, and 3 is a control circuit for controlling the counter. The counter is generally
An up counter of 1 or a down counter of -1 is used.

When using simple registers as the addressing means, it is possible to access memory in any order, but
It is necessary to transfer the address value to the register each time the memory r is accessed.

In digital processing, consecutive addresses in memory are often accessed one after another, and the counter shown in Figure 1 was devised to save time in transferring address values for each access. This method is used as an addressing means. Instead of transferring an address value, it only requires one bit to increment (or decrement) a counter, which shortens the memory access cycle compared to when a simple register is used as an addressing means, and speeds up processing. It's useful. However, when accessing the contents of every few (n) addresses in the memory one after another, as required in fast Fourier transform, the configuration shown in FIG. 1 is inappropriate. This is because the count width is fixed to 1 or -1, and every nth value necessary for the counter 2 must be transferred every time the memory is accessed. If the execution time of a memory access instruction is equal to the execution time of an instruction to transfer data to an address register, the memory access 'cycle will be twice as long as when accessing consecutive addresses. The above-mentioned problems are major obstacles to digital processing, which handles large amounts of data and requires high-speed processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory address control circuit that eliminates the above-mentioned problems.

According to the present invention, an address register, an adder that takes the address register as an augend and selects a plurality of fixed values and outputs them as addition values to the address register, and selection and addition of the addition values of the adder. An address control circuit is obtained, which includes an arithmetic operation and a control circuit that controls the operation.

Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of main parts showing one embodiment of the present invention. In Figure 2, 1' is a memory, 4 is an address register, 3' is a control circuit, 5.6 is a fixed value specifying means, 7 is an adder, and the control circuit 3/ is the input 5, 6 of the adder. control the selection and addition operation.

As an example, the addition values specified by 5 and 6 are respectively 1 and
n (n is an integer). If a fixed value of 5 is selected and added by the control circuit 3', the contents of consecutive addresses in the memory 1/ can be accessed one after another. or,
If a fixed value of 6 is selected and added by the control circuit 3', the contents of n addresses in the memory 1' can be successively accessed. As described above, according to this embodiment, the contents of consecutive addresses in the memory can be accessed one after another, and the contents of n addresses can also be accessed one after another. Moreover, the contents of consecutive addresses and the contents of n addresses can be accessed in any combination, which is highly effective against an increase in hardware.

In this embodiment, two selectable fixed addition values are provided, but it is clear that this can be expanded to three or more.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the main parts of a conventional address control circuit.
FIG. 2 is a block diagram of essential parts showing one embodiment of the present invention. 1.1'...Memo 1c2...Address specification counter, 3.3'...Control circuit, 4...
... Address register, 5, 6 ... Fixed value specifying means, 7 ... Adder. 2nd step

Claims (1)

[Claims] In the memory address control circuit, an address register, an adder that selects a plurality of fixed values in the address register and outputs them to the address register, and controls the selection of the addition value of the adder and the addition operation. Equipped with a control circuit,
An address control circuit characterized in that each time the adder executes an operation, the amount of increase between the current content and the next content of the address register is changed by selecting an addition value.