JPS62171052A - Memory structure - Google Patents

Abstract

PURPOSE:To enable a shift operation in a memory by providing a means which designates addresses adjoining to each other of a memory block divided into two blocks and a means to mask except a data position extending over both blocks and set a data position. CONSTITUTION:Addresses ADO and ADE which are given to two memories, E-MEM1 and O-MEM2, are respectively different, and this operation is executed by the output of address adders 7 and 8, and a constant arithmetic ROM 9. These values are designated by the address ADex including a shift. To this address ADex, bits showing the shift number S of 3 bits and the check bit ADO of 1 bit are added. According to the check bit value, addresses ADO and ADE given to the memories 1 and 2 are designated. Mask set values ME and MO necessary to the mask registers 3 and 4 are designated by the value of the check bit ADO in the address ADex and the shift number S. These values are stored in the constant arithmetic ROM 9.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a memory structure, and more particularly to a memory structure in which memory can be accessed, including any shift operation.

BACKGROUND OF THE INVENTION Among the processes performed by conventional microprocessors, the least efficient is access to memory, including shift operations. In this case, in order to access memory that spans the boundary, two accesses, several dot shifts, and several register cycles are required, which significantly slows down the processing speed. Ta.

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional memory structures and to provide a memory structure that allows access including shift operations. It is in.

Configuration The above object of the present invention is to provide means for dividing a memory into two blocks and specifying adjacent addresses of the divided memory blocks;
This is achieved by a memory structure characterized in that it is provided with means for masking a position other than the position of the data to be processed across two blocks, and a means for setting the position of the data to be processed in the masking means.

Hereinafter, the configuration of the present invention will be explained in more detail based on examples.

FIG. 1 is a block diagram of a memory showing an embodiment of the present invention. In this embodiment, when accessing the memory, in order to complete the access in one cycle in an arbitrary shifted state, two blocks of memory (E-MEM and
-MEM), so that even if data straddles memory boundaries, it can be accessed at once.

In the figure, 1 is an even memory (E-MEM), 2 is an odd memory (0-MEM), 3 and 4 are mask registers, 5 is an input/output arithmetic unit, 6 is a shifter, 7 and 8 are address adders,
Reference numeral 9 indicates a constant operation ROM.

In the following description, the operation in the case where 1 word = 8 bits 1 will be explained. In this case, the mask registers 3 and 4 each require a capacity of 8 bits.

Addresses given to the above two memories (ADo, ADH)
are different from each other. This operation is performed by the address adder 7.
, 8 and the output of the constant operation iROM 9. These values are specified by an address including shift (ADex). This value is shown in FIG.

FIG. 2(A) shows details of the address ADex,
It is something. A 3-bit bit indicating the shift number S and a 1-bit check bit ADo are added to this address ADex.

Depending on the value of the above check bit, the two memories E-
MEM1. 〇-Address AD,, AD given to MEM2
H is specified as shown in FIG. 2(B).

Also, the mask setting value M required for mask registers 3 and 4
E g Mo is specified from the value of the check bit AD and the shift number S as shown in FIG. 3, and these values are stored in the constant calculation ROM 9.

The operation of this embodiment will be explained below in the case of memory reading and memory writing.

Memory reading is performed simultaneously for E-MEMI and O-MEM2. Here, as shown in FIGS. 4(A) to (E),
A case will be described in which data D and A are read out of data C, D, A, and B spanning two addresses. In addition, S=
3. Set AD0=1.

FIG. 4(A) shows data at adjacent addresses read to the E-MEMI and O-MEM2.

That is, this shows a situation in which data C and D are stored in E-MEM1, and data A and B are stored in O-MEMZ.

, As mentioned above, S=3. Since AD, = 1, the third
From the figure, ME=07. Mo=F8, and this value is the fourth
As shown in FIG. 1(B), the mask registers 3.4 are filled with cell numbers 1 to 1.

The above read data is stored in each mask register 3.
, 4, as shown in FIG. 4(C).

Only the necessary parts (in this case data D and A) are extracted,
The signal is sent to the input/output arithmetic unit 5, where an OR operation is performed. This output is shown in Figure 4 (CD).

The above output is then shifted by the shifter 6, and the fourth
As shown in Figure (E), the necessary data is arranged and output after being corrected.

During memory writing, the written data is subjected to a shift operation opposite to that during reading, and is input to the input/output arithmetic unit 5. At this time, the data is stored in two memory blocks E without any operations.
-MEMI, given to 〇-MEM2.

However, in this case, since writing is not done to extra memory bits, the mask register is set to T for the memory write pulse.
1 Write with only the BH bit active. These write pulse signals are indicated by E-WE and O-WE.

The constants (A o g A E ,
M a + M o +S), etc. are stored in a constant calculation ROM.

The operations described above enable memory access including shifting.

In the above embodiment, the case where 1 word = 8 bits was explained, but also in the case where 1 word = 16 bits, the mask registers 3 and 4 are each set to have a capacity of 16 bits.
It goes without saying that it can be implemented in a similar manner.

Effects As described above, according to the present invention, shift operations can be performed within the memory, thereby reducing the number of accesses to the memory and improving the processing speed of the processor.

Furthermore, since there is no need for memory address boundaries, the program becomes simpler.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a memory showing an embodiment of the present invention, FIG. 2 (A) is an explanatory diagram of addresses including shifts, and FIG. 2 (B) is a diagram illustrating a memory addressing method using check pits. Figure 3 is a diagram showing how to specify the value of the mask register by shift number and check pit, and Figure 4 (
A) to (E) are diagrams illustrating the read operation. 1: Even memory, 2: Odd memory, 3, 4: Mask register, 5: Input/output arithmetic unit, 6: Shifter, 7.8 Near address adder, 9: Constant arithmetic ROM, ADo: Check pit, S: Shift number. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] (1) Dividing the memory into two blocks, and providing means for specifying adjacent addresses of the divided memory blocks, and masking other than the position of the data to be processed that spans the two divided blocks. A memory structure comprising means for setting the processing target data position in the masking means and the masking means.