JPS60218146A - Storage device address control system - Google Patents

Abstract

PURPOSE:To improve the economical efficiency of a computer or the like by using one address register for both the specification of a storage device address and a byte position in a buffer. CONSTITUTION:A writing address register is constituted of a high-order address register 11-1 holding a high-order digit part and a low-order address register 11-2 holding a low-order digit part. An output 30 from the low-order address register 11-2 specifies the byte position of the buffer 18 storing the output byte of a data processing part 17. The register 11-2 is counted up in each byte processing through an increment circuit 32. A carried value from the most significant digit at the increment operation of the register 11-2 is held by a carrying holding circuit 34 constituted of a flip flop and having an object to delay the carrying. Therefore, the carried value can be prevented from being immediately transmitted to the upper address register 11-1 and changed at its contents.

Description

DETAILED DESCRIPTION OF THE INVENTION (a1) Technical Field of the Invention The present invention relates to an electronic computer system, and more particularly to a method for controlling updating of a storage device address for accessing a computer storage device.

(b) Background of the Technology In order to access data in a computer, especially in the main memory, information indicating the location of the data in the main memory, that is, an address, is sequentially acquired from each instruction of the program being executed during the execution process. generated. This address is set in the address register for accessing the 'IfW device and used for access control.

In many instructions, addresses can be specified in units of approximately 8-bit data called bytes, and data from that specified address to the number of bytes determined by the function of the instruction is processed as the data specified by that instruction. be done.

On the other hand, in consideration of speeding up access, storage devices often have a structure in which the access unit is set to about 4 or 8 bytes, and multiple bytes are read/written at once (such units (hereinafter referred to as words).

In that case, only the upper part of the address generated by the instruction is used as the address required for the actual storage access, and the lower part of the address is, for example, the byte position of the 4 bytes read at once from the storage device. used as a specification.

(C1 Prior Art and Problems FIG. 1 is a block diagram illustrating control in the above configuration. In this example, the storage read address and write address generated in the process of executing an instruction are stored in the address register 10, respectively. and when set in address register 11, output 1 of the upper part of address register 10
2, the storage device 13 is accessed and the read word (
For example, 4 bytes) of data is held in the buffer 14.

The lower part (eg 2 bits) of address register 10 is used by control line 15 to specify the byte location within buffer 14. In the case of an instruction in which multiple bytes of a sequential address are to be processed, this lower part is incremented through the increment circuit 16 for each byte processed.

One byte taken out from the sofa 14 is subjected to the processing defined by this instruction in the data processing section 17 and is held in the buffer 18. The buffer 18 is a buffer provided primarily to hold write data, and the byte position within the buffer where the output of the data processing section 17 is to be stored is specified by the byte position register 19 using a control line 20.

The byte position register 19 is set in its lower part 21 when the address register 11 for writing is set, and thereafter updated by the increment circuit 22 every time one byte is processed.

When one word has been processed as described above, the contents of the buffer 18 are written to the address of the writing device 13 specified by the upper part 23 of the address register 11.

If this instruction is an instruction that targets data spanning two or more words, data at the next address is read out using the contents of the address register 10 that have been updated in the sequential increments described above, and processing continues in the same manner as described above.

In this case, the write address is written to the byte position register 19 by the adder circuit 24 after writing the previous word.
The address register 11 is updated according to the contents of.

As is clear from the above explanation, in the conventional method,
Since it is necessary to save the write address until the write data is output, it is necessary to provide the byte position register 19 and their peripheral circuits in addition to the address register 21 regarding the write address. This was a cost that could not be ignored, especially in the field of small computers that required low prices.

fd1 OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide an address control method that eliminates the need to provide a register for specifying a byte position within a buffer, in addition to an address register, in controlling the storage address of a system as described above. .

te+ Structure of the Invention According to the present invention, in a storage device address control method for controlling the address of data in a computer storage device, the address is divided into two parts and configured into an upper digit part and a lower digit part. a second-order address register that holds the upper digit part, a lower address register that holds the lower digit part, means for updating the contents of the lower address register, and a carry value generated by the updating means for storing the carry value in the upper address register. This can be achieved by a storage device address control method characterized by having means for adding to the contents and means for delaying the timing of the addition.

That is, according to the above configuration, the address register for accessing the storage device is divided into two parts, the upper digit part and the lower digit part, and the lower digit part can be updated independently, and the resulting carry value to the higher digit can be Since the timing of addition to the digits can be delayed,
By using the lower digit part to designate the byte position within the buffer, it becomes possible to use only one address register for both the address designation of the storage device and the designation of the byte position within the buffer.

(f1 Embodiment of the Invention FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, the same parts as in the conventional example shown in FIG. 1 are given the same numbers.

In FIG. 2, the process of reading data from the storage device 13 is the same as that of the prior art example, so a description thereof will be omitted.

In the present invention, the write address address register 11 in FIG. 1 is shown in FIG. 2 as an upper address register 11-1 that holds the upper digit part of the address register, and a lower address register 11-2 that holds the lower digit part. It is divided into two parts like this. Lower address register 11-2
The output 30 specifies the byte position of the buffer 18 in which the output byte of the data processing section 17 is stored. Also, it is incremented by the increment circuit 32 every time one byte is processed.

The carry value from the upper limit in the increment operation of the lower address register 11-2 is held in a carry holding circuit 34, which is formed of, for example, a flip-flop and whose purpose is to delay the carry. Therefore, it is possible to prevent the carry from immediately propagating to the -h address register 11-1 and changing its contents.

When the processing of one word currently being processed is completed, the storage device &13 is accessed based on the contents of the upper address register 11-1, and the contents of the buffer 18 are written. Thereafter, the contents of the carry hold circuit 34 are added to the upper address register 11-1 by the addition circuit 38, and the contents of the carry hold circuit 34 are added to the upper address register 11-1 by the adder circuit 38,
Set to 1-1. This value is used as the address to write the processing result of the next word.

The above description assumes that the address register 10 is dedicated to read addresses, and the upper address register 11-1 and lower address register 11-2 are dedicated to write addresses. However, in consideration of instructions that require two sets of read addresses, it may be desirable to enable the upper address register 11-1 and the lower address register 11-2 to also be used for read addresses.

In such a device, as illustrated in FIG.
A path 40 is provided to directly lead the carry signal from the lower address register 11-2 to the adder circuit 38, and a gate circuit 42 connects the output of the carry hold circuit 34 and the carry signal 40 depending on the purpose of this address register. be selected.

(Effects of the Invention As is clear from the above explanation, according to the present invention, one address register is used both for specifying a storage device address and for specifying a byte position in a buffer, thereby improving the economy of computers, etc.) This has a significant industrial effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing another embodiment of the present invention. In the figure, 10 and 11 are address registers, 11-1 is an upper address register, 11-2 is a lower address register, 13 is a storage device, 14 is a read buffer, 17 is a data processing unit, 18 is a write buffer, and 19 is a byte A position register, 22, 32 an increment circuit, 34 a carry hold circuit, 38 an adder circuit, and 42 a gate circuit. Kaya 1 prisoner

Claims (1)

[Claims] In a storage device address control method for controlling the address of data in a computer storage device, the above address is divided into two parts, an upper digit part and a lower digit part. A lower address register that holds a digit part, means for updating the contents of the lower address register, means for adding a carry value generated by the updating means to the contents of the upper address register, and means for delaying the timing of the addition. A storage device address control method comprising: