JPS60112140A - Access system of stack - Google Patents

Abstract

PURPOSE:To execute operation between two set of stacked data by one machine cycle by storing stacked data used frequently for a high-speed register and values of their stacked pointers and by accessing the register and the stack. CONSTITUTION:When assuming that a programmer uses frequently data 12 in a stack 2 afterwards, some one bit having a micro-field is turned on as a specific bit. A stack pointer 1 instructs address data 12, outputs the data 12 to an arithmetic system from a terminal A and stores them in a data register 9. A V-flag of a flag register 6 is turned on, which shows effectiveness of data in the register 9. Operation of the data 12 accesses the data register 9 inserted of accessing the stack 2. In such a case in which the newest data 13 specified by the stack pointer 1 are added to the data 12 stored in the stack 2, the data 13 are read out from the terminal 13, the data 12 are read out from the data regisrer 9 through the terminal B, the operation can be executed by one machine cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a central processing unit of a computer system that is equipped with a hardware stack in the central processing unit and a stack pointer that indicates the address of the hardware stack. When performing mutual operations, the data previously stored on the stack is stored in a register along with the stack pointer value indicating the address of the data, reducing the number of times the stack pointer is updated and performing the operation in one machine cycle. The present invention relates to a stack access method in which it is possible to determine whether data in the register is to be returned to the stack based on a flag indicating the state of the data, and to omit unnecessary control by a central processing unit.

(b) Prior art and problems Conventionally, in computer systems that use a stack, there is only one stack pointer that indicates the address of the stack.
During a machine cycle, one address on the stack is pointed to, so some operations on the first and second data stored in the stack require setting the stack pointer to obtain the first data. However, after reading the first data into the register, the stack pointer must be reset to obtain the second data, which requires at least two machine cycles. Therefore, there is a drawback that access to the stack is slow and the calculation speed is slow.

(C) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks by storing stack data that is considered to be used relatively frequently in the stack and also in a register, and actually accessing the data in a register. In addition to speeding up access by implementing this method, when performing an operation, the first data is read from the register and the second data is read from the stack, making it possible to perform operations between the first and second stack data. Its purpose is to provide a stack access method.

(d) Configuration of the Invention The configuration of the present invention is a data processing device equipped with a stack and a stack pointer that indicates the address thereof, and a register that stores part of the data stored in the stack and the address of the data; A flag indicating whether the memory content of the register has been rewritten in the stack is provided, and the validity of the data stored in the register is determined based on the content of the flag, and the stack is rewritten using the memory content of the register. It is designed to perform data calculations.

(e) Embodiments of the Invention The present invention stores frequently used stack data and the value of its stack pointer in a high-speed register, and accesses the register and stack to perform operations between two stack data in a single operation. This is done using machine cycles. Further, a flag indicating whether the data in the register is valid or not and a flag indicating whether the data in the register has been rewritten after being written from the stack is provided,
These flags ensure consistency between stack data and register data. These controls are processed by interrupts at the microprogram level so as not to impair high speed.

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention. For example, in the stack 2, new data is stored sequentially in the direction shown by the arrow ial, and the data storage area expands from top to bottom. When the data processing is completed, data is erased from the bottom in the opposite direction to the data storage area ( , 1 area is decreased.The address for accessing stack 2 is indicated by stack pointer 1.

A programmer who is currently creating a microprogram thinks that data 12 in stack 2 will be frequently used in subsequent processing, and turns on a certain bit of the micro field (part of the microprogram), for example, pin 1-"48". . FIG. 2 is a schematic diagram of a microfield. For example, “0
Pit 1-"48" of the micro field consisting of 49 bits from "" to "48" is set as a specific bit, and when this specific bit "4B" is on, the following operation is performed.

At this time, stack pointer 1 indicates an address as shown by the dotted line, and data 12 is output from terminal A to the arithmetic system and stored in data register 9 for preservation. At this time, the V flag of the flag register 6 is turned on to indicate that the data in the data register 9 is valid, and the W flag of the flag register 6 is turned on.
Leave the flag off.

Also, the value of stack pointer 1 at this time, ie, the address of data 12, is stored in address register 3.

Subsequent processing of data 12 accesses data register 9 without accessing stack 2. Therefore, when adding the latest data 3 indicated by stack pointer 1 to data 12 previously stored in stack 2, data 13 is read from the terminal, and data 12 is read from the data register 9 via terminal B. is read out, calculations can be performed in (1) machine cycles. And stack pointer 1 does not need to update its address.
If the data 12 is read from the stack 2 and stored in the data register 9 and then rewritten, the W flag of the flag register 6 is turned on. This embodiment shows a case where three address registers, three flag registers, and three data registers are used. Therefore, similar to the above operation, the data previously stored in the stack 2 is stored in the data register 10.11, and its address is stored in the address register 4.5.
34ffi types of frequently used data can be prepared by storing the data in each of the data registers 7 and 8 and setting the flags in the flag registers 7 and 8, respectively.

If the number of data to be stored in the data registers 9, 10.11 is 4 or more, the interrupt processing routine returns the data from one of the data registers 9, 10.11 to the stack 2. For example, data 1 of data register 9
If 2 is to be returned, the return operation will not be performed if the W flag in the flag register 6 remains off. Therefore, unnecessary control operations of the central processing unit can be prevented. If it is on, the address of stack 2 stored in address register 3 is read from terminal C, and new data 12 is written from data register 9 into the area where data 12 of stack 2 is stored. Therefore, consistency between the data in the stack 2 and the data in the data registers 9, 10, and 11 is guaranteed.

Further, when the data in the stack 2 is erased and the storage area is reduced, if the value of the stack pointer l becomes smaller than, for example, the address of the data 12, the ■ flag of the flag register 6 is turned off. This clears the data register 9.

(f) As described in detail, the present invention can significantly reduce the number of updates of the stack pointer to the stack, and the operation between the stack data and the stack data can be performed in one machine cycle, greatly improving the operation speed. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 2 is a schematic diagram of a micro field. 1 is the stack pointer, 2 is the stack, 3,4゜5 is the address register, 6,7.8 is the flag register, 9,1
0.11 is a data register.

Claims (1)

[Claims] A data processing device equipped with a stack and a stack pointer that indicates the address thereof, and a register that stores part of the data stored in the stack and the address of the data, and a register whose storage contents are rewritten by the stack. a flag indicating whether or not the data is stored in the register, the validity of the data stored in the register is determined based on the contents of the flag, and the stack data is operated using the stored contents of the register. access method.