JPS6180331A - Variable length data processor - Google Patents

Abstract

PURPOSE:To process variable length data simply the rapidly by forming a means for reading and writing fixed length data from an optional bit position at the time of access to the variable length data. CONSTITUTION:At the time of access to the variable length data, an address (A+1) is inputted through an adder 102 and a selection gate 103 as an address input to a bank 110 and an address A is inputted through a selection gate 104 as an address input to a bank 11n. A reading control circuit 106 turns on the lower (N-l) bits of a reading gate 12n and the upper (l) bits of a reading gate 120 on the basis of the bank address (n) and dot address (l) of the address input and sends the data to a memory data bus 100. Thus, the written variable length data are read out as the fixed length data from an optional bit position.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a variable length data processing device, and more particularly to a variable length data processing device that processes a large amount of variable length data such as image data.

(Prior Art) Instructions in conventional data processing devices have a fixed length (bytes,
It has been considered based on data (words, etc.). In this fixed length data, the length of the data to be calculated is predetermined, and is, for example, 1 bit, 1 character, 1 word, etc. The length of data actually generated varies depending on the processing content, so it is desirable to be able to set it to any length from the viewpoint of saving memory capacity and simplifying programs, but it is difficult to Fixed-length data is simpler and faster, so most commercial computers are based on fixed-length data operations. Furthermore, storage circuits within data processing devices also use a method of accessing fixed length data.

(Problem to be solved by the invention) However, with the current development of information processing systems, the range of information that must be handled has expanded, and multimedia data processing such as image information or phonetic information has become an important function. . These data are of variable length, and the information exchange is enormous.

Therefore, in a conventional data processing device, such ijf
When processing variable-length data, there are problems with storage device binding due to the increased number of data blocks, and the complexity of processing algorithms due to the need to always be aware of byte boundaries (or word boundaries) in data processing operations. The problem arises of increased time. In particular, the latter factor has become a drawback as storage elements become more highly integrated and the problem of coalescence in storage devices is being avoided.

This invention is intended to solve these problems.
O that can simplify and speed up processing for variable length data.
An object of the present invention is to provide an f-variable length data processing device.

(Means for Solving the Problems) In order to achieve the objectives 1-2, the present invention provides a storage device for storing variable length data used as image data such as image information, and a storage device for storing variable length data used as image data such as image information. In a variable-length data processing device consisting of an arithmetic device that reads, edits, and writes variable-length data, and an output mechanism that outputs the contents processed by this arithmetic device, fixing from an arbitrary bit position in the storage device is possible. A reading/writing means for reading and writing long data, a mask pattern generating means for selecting designated bit length data from a designated bit position of fixed length data in an arithmetic unit, and a mask pattern generating means for selecting designated bit length data from a designated bit position of fixed length data; Shifting means for shifting to an arbitrary bit position and transmitting the shifted data to the mask pattern generating means is provided in JJ.

(Function) According to the present invention, since the variable length data processing device is configured as described above, the storage device for storing variable length data can have variable length data according to the bit address obtained by the 11-bit address when accessing the variable length data. Read data from a fixed bit position as fixed length data. In addition, the arithmetic unit obtains the specified bit length data from the specified pit stand for the fixed length data read from the storage device, shifts this bit length data to an arbitrary bit position, and sets it as the focus address. Process variable length data with effective bit length. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration diagram showing a storage device according to the present invention. In the figure, +00 is the N value sent to the arithmetic unit that reads/adds/writes data in this storage device.
A memory data bus is a bidirectional bus of bits, 101 is a memory address bus to which data from the arithmetic unit 1- is transmitted, and 102 is for selecting the address to bank 11O, so that the data that has been accessed is transferred from bank lln. If the address spans the bank 110, an adder circuit 1 is prepared for supplying the address in the memory cell plus 1 to the bank +10, and extends from the bank lln to the bank 110.
03 is a selection gate that receives an address in a memory cell in the address input and selects an address to the bank 110;
04 is a selection gate that inputs the address in the memory cell in the address input, selects the row address and column address, and supplies data to the memory cells of bank 111 to bank IIn. 105 is the selection gate in the memory cell that is the target when writing is specified. A write control circuit 10 [( is a write control circuit that supplies a write signal to the bit of
Read control circuit that turns on the read signal of 2n, 1
10-11n are banks, each of which is a collection of storage units selected by the same bank address, and 120-12n transfer necessary data from banks 110-tin to the memory data bus 100-1- according to instructions from the read control circuit 108. This is a readout gate for sending out data. Here, the storage section of this storage device is divided into units called banks, and further divided into units called cells depending on the capacity of the storage section. The bit length of a cell is N bits, and the data lines of cells in the same bank are connected to the corresponding memory data bus 100 according to the bit number. By the way, the addresses of this storage device are assigned from bank 110 to bank 1 as shown in FIG.
1n) Continuous addresses are determined throughout. Further, the address input to this storage device is classified into four types, ie, a memory cell selection address, a memory cell internal address A, a puncture address n, and a dot address Q, from the highest order as shown in FIG. The memory cell selection address is used to select multiple cells in the same bank, and the address A in the memory cell is selected.) 103.104 and addition circuit! 02 input. Bank address n and dot address l are written in the write control circuit 105. It is used as an input to the read control circuit 10B.

Next, the operation of the storage device configured as described below will be explained.

When accessing variable length data as shown in FIG. 3, (A+1) is input as an address input to the bank 110 via the adder circuit 102 and the selection gate 103, and as an address input to the bank lln, it is inputted to the selection gate 104. A is input via. Then, the read control circuit +06 receives the address input bank address n,
According to the dot address l, read out the lower (N-J2) bits of I +2n and -h of the read gate 120.
Turn on the B11 bit and send the necessary data to the memory data bus 100.

In this way, the storage device of this embodiment can write variable length data to a fixed bit position according to the assigned bit address, and can read the written variable length data from any bit position as fixed length data. . Also,
The selection at the time of reading is made by the final stage readout gates 120 to 1.
2n eliminates the effect of access time on the arithmetic unit, and by placing the row address on the lower side of the address in the memory cell, the delay in addition of address input via the adder circuit 102 is minimized to achieve high-speed access. can.

FIG. 4 is a configuration diagram showing an arithmetic device according to the present invention. In the figure, 200, 201, and 202 are for connecting each unit, and are operand bus A, operand bus B, and result bus, 210 is an arithmetic unit that performs barrel shift, logical operation, and arithmetic operation, and 211 is a hard register. 2!3 and a selection gate that specifies the shift of the barrel shift in the arithmetic unit 21O according to the contents of the lower bits of the address register 215, 212 is a local memory that temporarily stores the arithmetic result, and 213 is the 2 bit address of the bit address to be Seratosed. 214 is a read-only memory for generating a mask pattern that uses the contents set in the hard register 213 as an address and sends the data to the operand bus A200. 215 is a dot address from the aforementioned storage device. The address register 216 is a data buffer in which N-bit data from the aforementioned storage device is set. Here, operand bus A200.
Operand bus 8201. The width of each bus of the result path 202 is the data width N bits of the aforementioned storage device. Further, the shift function in the arithmetic unit 210 can be performed by the contents of the lower bits of the address register 215 and the hard register 213 via a rotary shift of up to N bits and a selection of shift at (211). This makes it possible to combine the data read in the aforementioned storage devices as required. That is, by performing a left rotation shift operation for the dot address set in the address register 215, the read data is aligned to N bits starting from the most significant bit. In addition, when writing this generated N-bit data from an arbitrary bit position, the two's complement data of the bit address to be set is set in the hard register 213, and the counterclockwise shift is performed according to the shift amount instruction, as described above. It is possible to write N bits into the storage device from any bit position. Then, the contents set in the hard register 213 are sent to the operand bus A200 via the mask pattern generation read-only memory 214 as an address. This hard register 2
FIG. 5 shows the correspondence between the contents of 13 and the read mask pattern, that is, the contents of the mask pattern generation read-only memory 214. The selected mask pattern has N bits and is defined by the mask bit start position and mask length. By using this mask pattern and the shift function described above, arbitrary bit position data processing can be easily performed for any bit position of the variable length data in the storage device.

For example, when transferring C-bit length data in the shaded area (C≦N) from address a to address b as shown in FIG. 6, the data operation of the arithmetic unit in this embodiment is performed as follows. .

(1) Set a to the atto register 215. (2) From the storage device to the memory data bus 100 from address a to N.
Read the bit data and set it in the data buffer 216 (3).
Perform a left rotation shift by 15 dot addresses and temporarily store it in the local memory 212 as data aligned to N bits (4) Set b to the address register 215 (5)
Read N-bit data from location b# from the storage device via the memory data bus 100 and set it in the data buffer 216 (8) Rotate the N-bit data in (5) counterclockwise by the dot address of address register 2]5. Shift, N
Data buffer 21B as bit-aligned data
(7) Set C in the hard register 213 (s) The logical product of the data stored in (3) and the mask pattern, and the logical product of the data in the data buffer 21B and the reverse pattern of the mask pattern. (8) Set the two's complement of b to the hard register 213. (10) Transfer the data stored in the data buffer 216 in (8) to the hard register 213. Performs a left rotation shift by the shift amount specified by
Store in 1B (11) Store the contents of the data buffer 218 in (10) in address b indicated by the address register 215 (effects of the invention) As explained above, according to the present invention, access can be made in bit units. The shift function and mask pattern generation mechanism in storage devices and arithmetic units that can be used make it possible to process variable-length data through unified management of bit addresses and effective bit lengths, and also speed up and simplify the processing of variable-length data. It is possible to provide a variable length data processing device that can effectively perform editing, φ displaying and outputting or data compression/expansion of image data such as image information.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing a storage device in this invention, and FIG.
The figure shows the address allocation of the storage device shown in FIG. 1, FIG. 3 shows the address division of the storage device shown in FIG. 1 and an example of accessing it, and FIG. A configuration diagram, FIG. 5 is an explanatory diagram of a mask pattern,
FIG. 6 is a diagram showing an example of variable length data processing. 100...Memory data bus, 101...Memory address bus, 102...Addition circuit. 103, 104.211... selection gate, 105...
-Write control circuit, 10B... Read control circuit, 110-lln... Bank, 120-12n read gate, 200... Operand bus A, 201... Operand bus B, 202... Result bus, 210... Arithmetic unit, 212... Local memory, 213... Hard register, 214... Read-only memory for mask pattern generation, 215... Address register, 21B... Data buffer.

Claims (1)

[Claims] a storage device that stores variable-length data; and a storage device that reads the variable-length data stored in the storage device, performs data processing, and outputs the processed data to the storage device for storage in the storage device. In a variable-length data processing device comprising an arithmetic unit that performs processing, and an output mechanism that outputs content processed by the arithmetic unit, the storage device stores fixed-length data from an arbitrary bit position when accessing the variable-length data. The arithmetic unit is equipped with a reading/writing means for reading and writing data, and the arithmetic unit obtains specified bit length data from a specified bit position with respect to the variable length data read from the storage device, or Mask pattern generating means for giving the specified bit length data to a bit position, and shifting the specified bit length data obtained from the mask pattern generating means to an arbitrary bit position, or shifted data A variable length data processing apparatus, comprising: a shift means for applying a value to the mask pattern generation means.