KR830000265B1 - Information processing device - Google Patents

Abstract

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Description

Information processing device

1 is a block diagram of a conventional information processing apparatus.

2 is a block diagram of an information processing apparatus showing one embodiment of the present invention.

3 is a diagram showing a state of storing registers in the local memory shown in FIG.

4 and 5 show the command format.

The information processing apparatus has a plurality of general registers, and the registers may be configured in a common storage apparatus. This memory device is called local storage and is provided in the form of a high speed IC memory.

The present invention relates to an information processing apparatus having a local memory as described above.

If the maximum and address space handled by a conventional information processing apparatus are within 64K bytes, 16 bits are sufficient to display address information, but when using an address space exceeding 64K bytes, 17 bits or more of address information is displayed. Is needed.

For example, 20 bytes of address information are required to display an address space of 1M bytes.

Therefore, in order to reduce the size of the information processing apparatus and reduce its cost, there are cases where 16 bits (2 bytes) are used to display the address information in the apparatus or to transfer the normal data and to display the information processing in one unit.

1 is a block diagram of a conventional information processing apparatus as described above. In FIG. 1, the local memory device 12 has a suitable storage capacity and each word has a width of 16 bits. The read and write operations of the local memory 12 are performed in units of words, and one register is formed by combining two words. There are general registers, work registers, and the like, which are registers configured in the local storage device 12.

The general purpose register is used to store address information as an index register or a base register, and is used to store normal data as an operand register in the case of performing fixed-point or logical operations.

The work register is used to temporarily store the result of the operation and prepare for the next operation.

In the local memory 12, various registers are configured, and two words are not necessarily allocated. Since such registers are not directly related to the present invention, they may be omitted in the following description.

In the operator 1 which receives two input data having a data width of 16 bits all together, this input data is applied from the input bus 13 via the input registers 15 and 16. The output data of the operator 11 appears on the output bus 14 and this data is either set to the local memory 12 or set in the address register 17.

In the main memory 18, instructions or data are stored, and the read address or write address of the main memory 18 is stored in the address register 17. As shown in FIG.

In the above-described complementary processing apparatus, there are the following problems when address information is read out from each of two sets of registers of the local memory device 12, and then these are added by the calculator 11.

The address operation will be described later in detail. That is, since the address information is 16 bits when the address space handled by this information processing apparatus is 64K bytes, the above address operation is completed in one time, and there is no problem. However, when the address space is 1M bytes, the address information is It becomes 20 bits and adds with respect to the lower 16 bits of 20 bits from the 1st time, and adds with respect to the remaining upper 4 bits from the next 2nd time. Therefore, it is necessary to perform the address operation twice, and the address operation takes time and has the disadvantage of poor performance.

To solve this problem, there is a method of increasing the word width of the local memory device 12 or the input data width of the calculator 11, but the number of bytes of the width should be 2 ⁿ (n: number of bytes of address information). Therefore, if the address information exceeds 2 bytes, it is not necessary to set the word width of the local memory device 12 or the input data width of the operator 11 to 4 bytes. However, such a wide width causes the device to be large, resulting in an excessively expensive cost.

An object of the present invention is to provide an information processing apparatus capable of shortening the time required for address operation and improving performance without increasing the size of the apparatus to solve such a problem. In general, the processing of an instruction includes (1) reading the instruction to be executed from the main memory, (2) decoding the read instruction using the instruction, and (3) performing an address operation for address addressing. (4) reading the operand from the register or the main memory, (5) performing an operation on the operand (the operation may not be performed on the operand, In the following, the operation is divided into registers or main memory.

The present invention has a feature in the case of performing the address calculation process (3) and the operand calculation process (5).

In the operand operation, the case where the operation result is loaded into the register is related to the present invention, and the case where the operation result is loaded into the main memory is not directly related to the present invention.

Therefore, in the present invention, when the operation result is loaded into a register in the local memory in the operand calculation process, the study is conducted on the side of the operation. In operand calculation, in general, it is impossible to determine whether the operand calculated at that time is normal data or address information in the apparatus. In either case, the following work is done on the register side of the register. That is, when it is necessary to read address information from a register in the address operation of the next new instruction processing, address information of a sufficient number of bits to display the address space can be read at once.

In this way, if the operator has an input data width capable of processing this address information at one time, the address calculation process of each instruction can be performed at high speed, and the performance of the information processing apparatus can be greatly improved.

Embodiments of the present invention will be described below with reference to the drawings.

2 is a block diagram of an information processing apparatus according to the present invention. In this information processing apparatus, the address space is at most 1 Mbyte. The local memory 22 includes two banks, BK ₁ and BK ₂ , each independently accessible. Both banks are commonly addressed, so the word width on the bank BK ₁ side is 4 bits and the word width on the bank BK ₂ side is 16 bits. Therefore, one word of local memory tee 22 is 20 bits.

If each of these 20 bits is set to A to A ₁₉ , the four ratios of A ₀ to A ₃ are in charge of the bank (BK ₁ ), and the 16 bits of A ₄ to A ₁₉ are in charge of the bank (BK ₂ ). One register composed of a plurality of registers in the local memory 22 has a width of 32 bits (4 bytes) as shown in FIG. 3, and the 2 bytes (0, 1 byte) thereon are address i. Is composed of A ₄ to A ₁₉ , and the lower two bytes (second and third bytes) are configured as A ₄ to A ₁₉ at address i + 1.

Each byte has a bit position from 0 to 7.

The operator 21 has 20 bits of left and right input data widths, and the input data is applied from the input bus 23 via the input registers 25 and 26.

This operator 21 is used for both an address operation and an operand operation. The input bus 23 is composed of three sets of data buses 231 to 233, and each of four bits from A ₀ to A ₃ in the read data A ₄ to A ₁₉ of the local memory device 22 is A ₄ to A. 8 bits up to ₁₁ are output, and 8 bits up to A ₁₂ to A ₁₉ are output.

The output data of the calculator 21 appears on the output bus 24. The output bus 24 is formed of four sets of data buses 241 to 244. The output data of the operator 21 is a maximum of 20 bits. When each bit is set to B ₀ to B ₁₉ , the data buses 241 to 244 each have 4 bits of B ₀ to B ₃ and B ₄ to B ₁₁ . 8 bits are output, 4 bits from B ₁₂ to B ₁₅ and 4 bits from B ₁₆ to B ₁₉ are output.

Data on the output bus 24 is written to the local memory 22 or set in the address register 27.

The contents of the address register 27 are used as the read address or the write address of the main memory 28. When data from B ₀ to B ₁₉ on the output bus 24 are written to the local storage device 22, the data of B ₄ to B ₁₉ is always included in the positions A ₄ to A ₁₉ , but A ₁₆ to A Position ₁₉ contains the data of or.

This selection is made in the selector circuit 29. The command read from the main memory 28 is supplied to the command register 30.

The control unit 31 receives a command from the command register 30, and controls each unit based on the content.

This control part 31 is good as a micro-program type.

The control unit 31 controls the operation of the selector control unit 311 for controlling the operation of the selector circuit 29 and the operation of the local memory control unit 312 and the calculator 21 for controlling the operation of the local memory 22. There is an operation control unit 313 for this purpose.

There are various other types in the control unit 31, but they are omitted here. Each control part controls the selector circuit 29, the local memory device 22, and the calculator 21 as described below.

The features of the present invention are in the address operation process and the operand operation process as described above. So, while the above process is described, the operand operation process will be described first for ease of explanation. It is apparent to those skilled in the art that writing of arithmetic operations in registers in the epoland calculation process can occur when executing an instruction such as RR format or RX format.

Therefore, the case of executing the RR format instruction will be explained. The instruction in the RR format is shown in FIG.

R ₁ and R ₂ are respectively locked to the general purpose registers in which the first and second operands are stored.

Thus, the general registers GRA and GRB operate on each of 4 bytes and log the result to the general register GRA. The general-purpose registers GRA and GRB are assumed to be configured as n and n + 1 addresses and m and m + 1 addresses of the local memory 22, respectively.

The above-described operand reading process will be described. First, the operand reading process is performed in the first step. Here, A ₄ to AB ₁₉ are read from the n + 1 address of the bank BK ₂ of the local storage device 22 and set in the input register 25 via the input bus 23. The register contents occupy the second and third bytes of the general register GRA.

The operand reading process is also performed in the second step. Here, the contents of the input registers 25 and 26 are calculated by the calculator 21, and the result is passed through the output bus 24 to the local storage device 22. This bank BK ₂ is locked to A ₄ to A ₁₉ at address n + 1.

In the next fourth step, the operand reading process is performed again. Here, A ₄ to A ₁₉ are read out at the n address of the bank BK of the local storage device 22 and set in the input register 25 via the input bus 23. This content occupies 0,1 byte of the general-purpose register GRA. The operand reading process is also performed in the next fifth step. Here, A ₄ to A ₉ are read out at the m address of the bank BK of the local memory 22, and are set in the input register 26 via the input bus 23. Occupies one byte Next, the operand calculation process is performed in the sixth step. Here, the contents of the input registers 25 and 26 are calculated by the calculator 21, and the result is output bus 24, so that the bank BK ₂ of the local memory device 22 is A ₄ to A ₁₉ at n. Be lodged in. At this time, the selector circuit 29 outputs data of B ₁₆ to B ₁₉ and is written to A to A at address n + 1 of the bank BK.

The four-byte data calculated in this manner is stored in the general-purpose register GRA in the local memory 22 in the state shown in FIG.

Attention is drawn to the fact that the contents of A ₁₆ to A ₁₉ of address n of the general-purpose register GRA and the contents of A ₀ to A ₃ of address n + 1 are the same. The same applies to all cases in which the operand calculation result is loaded into another register of the local memory device 22.

In the above description, there is a case where the reading of the local memory device 22 is performed only for the banks BK ₂ (steps 1, 2, 4, 5), but the bank BK ₁ also permits reading and instead A Regarding the data of ₀ to A _3, the input to the input bus 23, the input registers 25 and 26, or the calculator 21 is prohibited or the target of the operation in the calculator 21 is limited to 16 bits. You may not perform further calculations. The local memory 22 may also be written only in the bank BK ₂ (step 3). However, the bank BK ₁ is allowed to write, and the selector circuit 29 allows the data to be written instead. May not be output.

Next, an address operation process will be described.

It is well known to those skilled in the art that it is the case of executing an instruction such as RX format or RS format that can occur in the address operation.

Thus, a description will be given of the address calculation process in the RX format instruction processing. The RX format instruction is shown in FIG. R ₁ designates a general register in which the first operand is stored. X and B designate the index register and the base register of the local memory 22, respectively.

And D designates displacement. The address calculation process is performed by adding the contents of the index register, the contents and the displacement of the base register to obtain the address of the main memory 28 in which the second operand is stored. Hence, the address calculation process in the case where X, B and the general purpose registers GRA and GRB used in the above operand calculation process are specified, respectively. First, in the first step, A ₀ to A ₁₉ are read at the n + 1 addresses of the banks BK ₁ and BK ₂ of the local memory device 22 and set in the input register 25 via the input bus 23. do.

In the second step, A ₀ + A ₁₉ is read out from the banks BK ₁ and m + 1 of the local memory device 22 and BK ₂ to the input register 26 via the input bus 23. Is set.

In the next third step, the contents of the input registers 25 and 26 are added by the calculator 21, and the result is routed to the work register GRC in the local memory 22 via the output bus 24. If the work register (GRC is composed of l and l + 1 addresses of the local memory 22), the result of the calculation is loaded into l + 1 addresses of the banks BK ₁ and BK ₂ . The circuit 29 outputs B ₀ to B ₃ on the output bus 241.

In the fourth step, A ₀ to A ₁₉ are read out at l + 1 of the banks BK ₁ and BK ₂ of the local memory device 22 and set in the input register 25 via the input bus 23. do.

In the next fifth step, the displacement D in the instruction is taken out from the instruction register 30 and set in the input register 26 via the input bus 23.

In the next sixth step, the contents of the input registers 25 and 26 are added by the calculator 21 and the result is set in the address register 27 via the output bus 24.

The contents of this address register 27 become the address of the second operand in the main memory 28.

The above address operation is performed much faster than the conventional one. That is, even in the conventional case, the first to third steps and the fourth to sixth steps need to be divided into two times of the lower 16 bits of the first 20 bits and the remaining upper 4 bits of the second bit, respectively.

On the other hand, when the local memory device 22 reads the address information by the information processing apparatus of FIG. 2, all 20 bits are obtained at once, and further, the entire calculator 20 can calculate all of these 20 bits at once. Therefore, the address operation can be performed at twice the speed, and a high performance information processing apparatus can be obtained.

In the above embodiment, the operator 21 is used for both the address operation and the operand operation, but a separate operator may be used. In this case, the arithmetic unit for address calculation needs to have 20 bits of the input data width on the left and right sides similar to that of the arithmetic operator 21. However, the arithmetic operator for operand operation should process 2 bytes, so the input data width may be 16 bits.

In the above, the present invention has been described with an example of an information processing apparatus that handles 20 bits of address information in order to display an address space of 1M bytes, but the present invention can be applied to the case of handling address information of other bits. It is obvious.

According to the present invention, it is possible to obtain a high performance information processing apparatus capable of calculating a high speed address.

Claims (1)

Each word has a number of bits of X bytes + Y bits, the memory of which two words make up one register, and the low Y bits of the upper word when the result of the operand calculation is loaded into the register. A circuit that loads the data being written to the upper Y bits of the lower word, an operator that processes data consisting of the number of bits of X bytes + Y bits at a time, and the data of the register is input to the operator to perform the operand operation. And a circuit for separately reading the word X bytes of the upper and lower registers of the register.

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