JPH0315772B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory cell for storing list structured data.

List processing languages such as LISP are widely used as languages for creating programs related to symbol processing and artificial intelligence.

In list processing languages such as LISP, programs and list structure data are realized in a storage device based on list cells consisting of a control section, a data section, and a pointer section.

In FIG. 1, one word in the storage device is used as a control section, a data section, and a pointer section, and list data (ABC) is expressed using three words from addresses 100 to 102. The data section indicates the location where the actual data A, B, and C are stored.
“NIL” in the pointer section at address 102 indicates the end of the list data.

When list processing proceeds using such list cells, temporarily used working list cells end up being scattered unused in the storage device. During processing, as list cells are needed, they are taken from the list of available cells and used. However, once all of the available cells are used up, it becomes necessary to retrieve the unnecessary list cells in the storage device. This operation is called garbage collection (GC).

This GC operation is generally performed in the following two steps.

(1) Based on all registers related to list processing, such as control registers in the computer and pointer data in the stack for arithmetic processing, search for list cells connected from these registers and execute the control unit. Set to valid state (“1”).

(2) All list cells in the storage device are sequentially scanned, and the control unit selects words in an invalid state (“0”), performs chaining, and registers them in the list of available cells.

The above two steps are conventionally accomplished by serially searching one word at a time. especially,
The second step was accomplished by reading all the words in the memory one by one, and the controller determining which words were in an invalid state and connecting them to the list of available cells. Therefore, when the word capacity of a storage device becomes large, a very large amount of time is required, which is the biggest cause of deterioration in list processing performance.

It is an object of the present invention to solve the drawbacks of the above-mentioned second step when realized by the conventional method, and to achieve high-speed operation.
An object of the present invention is to provide a memory cell having a built-in mechanism for performing a GC operation.

A further object of the present invention is to provide a memory device that connects a plurality of memory cells, has a large capacity of words, and can perform GC processing at high speed.

That is, according to the present invention, 1. a plurality of word memory cells in which data can be written and read by sequentially addressed addresses, block address storage means for storing block addresses of the memory cells, and memory cells for storing block addresses of the memory cells; A control means that divides one word and uses it as a control section, a data section, and a pointer section, and controls the control section to chain words indicating an invalid state, and the first and last word addresses of the chained memory cells. The device is equipped with a chain address storage means for storing a chain address, and an instruction means for indicating that chaining is completed, and when an activation signal is given from the outside, all words of the memory cell are searched in the order of addresses, and the control unit and invalid state are searched. A memory cell which connects words in a chain and makes it possible to set the chain address storage means and instruction means.

2. When a plurality of memory cells according to claim 1 are connected in cascade, and a set signal from the outside is activated, the word pointer section of the memory cell indicated by the chain address storage means is set to the chain address storage means of other memory cells. By adding a control function for setting the address data indicated by to the control means of claim 1, a memory device is obtained in which all memory cells can be chained simultaneously.

Next, a detailed explanation will be given using examples.

FIG. 2 shows a block diagram of an embodiment of a memory cell using the present invention, which comprises a memory cell 1, block address storage means 2, control means 3, chain address storage means 4 and 5, and instruction means 6.

Memory cell 1 consists of 8 words with 33 bits per word.
The upper 1 bit is used as a control section, the next 16 bits are used as a data section, and the next 16 bits are used as a pointer section. This memory cell is realized in the same way as a commercially available IC memory, and has a 3-bit address signal line 7.
Accordingly, write and read operations are performed based on instructions from the read/write signal line 8. At this time,
Data to be written is input via signal line 9, and data to be read is taken out via signal line 10.

The block address storage means 2 is a 16-bit register and is realized using a commercially available D-type flip-flop IC. A 16-bit block address is set in the block address storage means 2 via the input data signal line 9.

The control means 3 comprises a binary counter 31, a binary adder 32, selectors 33 and 34, and a control circuit 35. The binary counter 31 has a length of 3 bits and is a commercially available binary counter IC (for example,
SN74191). This binary counter 31 is initialized to 7 by the control signal 101 from the control circuit 35, and is sequentially initialized to 6, 5,
...The count is decremented to 0.

The binary adder 32 is 16 bits long and is implemented using a commercially available logic unit (eg, SN74181). Then, by setting the carry input from the lower bit to "0", the data ("BA") of the block address storage means 2 and the data ("1") of the binary counter 31 are input, and the data ("1") of the binary counter 31 is inputted.
2 outputs the address value "BA+i". The output of the binary adder 32 is led via the signal line 202 to the chain address storage means 5 and to the temporary address register 36 in the control circuit 35.

Selectors 33 and 34 are realized by commercially available selector ICs (for example, SN74158), and have 3 bits and 16 bits, respectively.

The control circuit 35 is constructed of a commercially available AND gate, NAND gate, D-type flip-flop, etc., and includes, in particular, a 16-bit temporary address register 36 and a control section determination gate 37. Temporary address register 36 is comprised of a 16-bit D-type flip-flop. Further, the control section determination gate 37 is constructed by combining two-input AND gates.

The chain address storage means 4 and 5 are both 16-bit registers, which are commercially available D-type flip-flops, and the indicating means 6 is a 1-bit flip-flop, which is also a commercially available D-type flip-flop. And these are each signal line 1
2, 13, and 14, it is possible to take out the data to the outside of the memory cell.

Next, the operation of the control circuit 35 will be described in detail.

In memory cell 1 in FIG. 1, currently the above
The first step of GC operation is completed, BA+0, BA
Assume that the word at address +3, BA+5 is in a valid state, that is, the control unit is set to "1".

This operation is performed by an external control circuit (not shown) as follows.

One of the control registers involved in list processing is selected, and the value indicated by this register is applied to the memory cell as an address to read out the corresponding word. Then, the control section is set to "1". Next, the pointer part of this word is used as an address to retrieve the word it points to. Then, the control section is set to "1". This operation continues until the pointer section indicates the end of the list, and then ends.

The above operations are achieved by performing them based on all registers related to list processing.

When a starting signal is applied to the signal line 11 from the outside, the binary counter 31 is set to "7" by the signal line 101. Next, the signal line 102 becomes "1", and the second step of the GC operation is entered.

The data (“7”) of the binary counter 31 passes through the selector 33 and is transferred via the signal line 203 to the address value “7” in the memory cell, which is the address at address BA+7.
is applied to the memory cell 1, and a read operation is instructed by the signal line 8. The read data is given to the control circuit 35 via the signal line 10,
The control circuit 35 determines the control section of the word at address BA+7. This determination is made by checking whether the control unit (bit 32) bit of the signal line 10 is "1" or "0" using the control unit determination gate 37.
Since the control unit for the word at address BA+7 is "1", it is determined that the word is in a valid state, so no processing is performed on this word. Next, when the binary counter 31 is set to "6" and the word at address BA+6 is taken out, the control section is "0", indicating that it is in an invalid state. At this time, the address "BA+6" is output from the binary adder 32, and this address value is set in the chain address storage means 5 and the temporary address register 36 through the signal line 202. As a result, the chain address storage means 5 holds the address of the invalid state word having the maximum address of this memory cell.

Next, when the binary counter 31 is set to "5" and the word at address BA+5 of the memory cell is taken out, it shows a valid state, so no processing is done and the binary counter 31 is read out.
Change 1 to “4”. And memory cell BA+4
When the address word is retrieved, it is found that it is in an invalid state. Therefore, the signal line 103 is set to "1" and the data in the temporary address register 36 is transferred to the signal line 205,
Furthermore, the memory cell address "4" indicated by the binary counter 31 is given to the signal line 203, and the address value "BA+6" is sent to the pointer part (bits 15 to 0) of the word at address BA+4. ”. Then, binary adder 3
The address value "BA+4", which is the output data of step 2, is set in the temporary address register 36. At this time
Since the word BA+4 is not in the first invalid state, it is not set in the chain address storage means 5.

The same processing as above is BA+3, BA+2, BA+
When this is performed on the word at address 1, as shown in Figure 2, the pointer field of the word at address BA+2 is set to "BA+4", the pointer field of the word at address BA+1 is set to "BA+2", and the pointer field of the word at address BA+1 is set to "BA+2", and Address register 36 is set to "BA+1".

Next, the binary counter changes from “1” to “0”,
From the control unit for the word at address BA+0, it can be seen that the word at address BA+0 is in a valid state. Also, since the binary counter 31 becomes "0", the memory cell 1
It can be seen that the processing of all words has been completed.

At this time, the address "BA+1" stored in the temporary address register 36 is set in the chain address storage means 4 via the signal line 204. Therefore, the chain address storage means 4 holds the address of the invalid state word having the smallest address in this memory cell. Furthermore, it is set to "1" so that the instruction means 6 indicates the completion of chaining.

As a result of the above operations, as shown in Figure 2,
BA+1, BA+2, BA+4, BA of memory cell 1
The words at address +6 are chained in this order, and the chain address storage means 4 and 5 respectively store the minimum word address "BA+1" and the maximum word address "BA+6".

The control circuit 35 controls the above operations. The configuration and operation of the memory cell have been described above in detail.

Next, a case will be described in which a plurality of these memory cells are connected to form a large-capacity memory device and GC processing is performed at high speed.

FIG. 3 shows a block of a memory device using three of the above memory cells. It is also assumed that a control circuit is provided to control all of these. First, this control circuit sets the block addresses of each memory cell A, B, and C to 100, 200, and 300, respectively.
The street address is set. Next, the INIT signal 11 is applied to all memory cells A, B, and C to perform chaining within the memory cells. The results are shown in FIG. Then, based on the output STAT-OUT signal 14 of the instruction means 6, which is a chaining completion signal from each memory cell A, B, and C, it waits until chaining is completed in all cells. When chaining is completed, all memory cells A, B, and C are set in this state.
The signal line 15 is activated to perform chaining between memory cells.

Next, this operation will be explained in detail.

Data input signal line 9 of memory cell A is connected to memory cell B
The memory cell B is connected to the output line 12 of the chain address storage means 4, and is supplied with the minimum word address (address "200") of the list cell chain of the memory cell B.
At this time, in the memory cell shown in FIG.
When the set signal is applied via the control signal 1
04 becomes valid, and address data "200" is guided to the memory cell 1 via the signal lines 9 and 201. Further, the data in the chain address storage means 5 is selected by the selector 33, and the address "106" is led to the memory cell 1. and,
By putting the signal line 8 into the write state, the pointer section of the word at address 106 of memory cell A is set to address "200", and memory cell A is chained to memory cell B. At the same time, storage cells B and C are also chained. Furthermore, the beginning of the list cell chain can be known from the data in the chain address storage means 4 of the memory cell A. Further, a value indicating NIL is supplied to the data input signal line 9 of the memory cell C, and the chain address storage means 5
"NIL" is set in the pointer field of the word at address 306 of the memory cell C held by the memory cell C, which can indicate the end of the list cell chain.

The configuration and operation of a memory device including one memory cell and a plurality of memory cells have been described above.
As is clear from the above description, by using the memory cell according to the present invention, GC operation can be performed at high speed.

An embodiment using the present invention has been described above.

Therefore, the bit length of the memory cell of this memory cell,
The word length is just an example and may have any structure.

In addition, the block address storage means 2 has a dynamically possible format (register format), but the ROM
It may be of any format.

Furthermore, although the chaining process in this embodiment is carried out serially one word at a time within the memory cell, it may be divided into a plurality of blocks and carried out in parallel.

Further, the combination of memory cells for configuring the storage device of this embodiment is merely an example, and the combination may be performed out of physical order.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of list data, FIG. 2 is a block diagram showing an embodiment of the memory cell of the present invention, and FIG. 3 is a block diagram showing an embodiment of a storage device using the memory cell of the present invention. It is a diagram. In FIG. 2, reference numeral 1 is a memory cell, 2
3 is a block address storage means, 3 is a control means, and 4 is a block address storage means.
and 5 indicate chain address storage means, and 6 indicates instruction means, respectively.

Claims (1)

[Scope of Claims] 1. A plurality of word memory cells in which data can be written and read by sequentially addressed addresses, block address storage means for storing block addresses of the memory cells, and one word memory cell of the memory cells. is divided and used as a control section, a data section, and a pointer section, and the control section stores the first and last word addresses of the chained memory cells. It is equipped with a chain address storage means and an instruction means for indicating that chaining is completed, and when an activation signal is given from the outside, all the words of the memory cell are searched in address order, and the control section searches for words in an invalid state. 1. A memory cell characterized in that the memory cells are connected in a chain, and the chain address storage means and instruction means are set. 2. A plurality of word memory cells in which data can be written and read by sequentially addressed addresses, block address storage means for storing block addresses of the memory cells, and a control unit that divides one word of the memory cells. , a first control means which is used as a data part and a pointer part, and which controls the control part to chain words indicating an invalid state; and a chain address storage which stores the first and last word addresses of the chained memory cells. means for indicating that chaining has been completed; and a step for setting address data indicated by the chain address accumulation means of another memory cell input to the word pointer portion of the memory cell indicated by the chain address accumulation means. 2 control means, when an activation signal is applied from the outside, all the words of the memory cells are searched in address order, the control section connects the words in the invalid state in a chain, and the chain address storage means 1. A memory cell characterized in that the instruction means sets the address data indicated by the chain address accumulation means of another memory cell input to the pointer section of the word of the memory cell indicated by the chain address accumulation means.