JPH02136946A - Cache memory control circuit - Google Patents

Abstract

PURPOSE:To shorten the cache reading time by storing the cache read data into a data buffer and then reading out the read data en bloc. CONSTITUTION:When a cache memory is set in a read mode, a data array DA 11 and the data buffer word address are sequentially counted up and at the same time the read data on the DA 11 is stored in a data buffer DB 18. Meanwhile the data buffer word location is also successively counted up. Then the DB 18 is set in a shift mode and the contents of the DB 18 can be completely read out via a shift path. Thus the reading time is shortened for all contents of the cache memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cache memory control circuit, and particularly to a cache memory control circuit when not all data stored in a cache memory is read.

In some types of information processing devices, in order to speed up memory access time, a memory called cache memory, which has a smaller capacity and is faster than main memory, is placed between the processing unit and the main memory. There is. By storing a copy of a part of the main memory in this cache memory and making the cache memory appear to be main memory from the processor, while the processor is accessing the area existing in the cache, (Catschhit) provides high-speed memory access time.

In this case, copies between the main memory and the cache memory are managed in units called blocks. A block is smaller than the total capacity of cache memory, typically a few bytes to tens of bytes.

When a memory access is made to an area that does not exist in the cache memory (cache miss), replacement with the main memory is performed in units of blocks.

The cache memory has the following two methods for handling store access. One of these is the store-through method, in which store accesses are made to the cache memory and main memory simultaneously. Even if there is a store access or a cache miss, replacement with main memory is not performed.

The other method is a store-in method, in which store access is performed only to the cache memory. When a store access results in a cache miss, replacement with the main memory is performed.

As mentioned above, the contents of the cache memory appear to be the same as the main memory from the processor's perspective, so it is usually not necessary to consciously read the contents of the cache memory.However, in the event of a cache memory abnormality (design error, failure) In some cases, you may want to read the contents of a cache memory separately from the main memory to see the access history of the processor. In addition, in a cache memory that uses the store-in method described above, the contents of the main memory at a certain point in time do not reflect store accesses made only to the cache memory, so the contents of the cache memory are read at the same time as the main memory. There is a need.

The following method can be considered as a method for reading the contents of the cache memory. One method is to provide a dedicated read line for each read unit of the cache memory, and the other is to read the successive register of the cache memory using a so-called shift method. In either method, it is necessary to sequentially change the contents of the address register that addresses the cache memory and perform reading as many times as the number of addresses.

Although the former method is fast, it requires many signal lines, resulting in an increase in hardware and a decrease in reliability, so the latter method is often adopted.

This method (referred to as the shift method) takes more time to print successively than the former method. Therefore, it is desired to shorten the read time.

Regarding the read time of the cache memory using the shift method, the following equation holds true.

T+---+ =A-3・+B-Ca +c+++-+
+ (1) Here, S is the number of shifts (times) required to read the entire memory (Ca/D: D is the number of bits that can be read in one shift), and Ca is the total memory capacity (number of bits [bit]
, A is the processing time per shift [5 ecl times], B is the processing time proportional to the memory capacity [sec/bijl, and C is the fixed time [5 ecl] required for the memory successive access operation.

A is the time spent on setting the environment when performing a shift operation, and B is the time spent on extracting and setting target information after shifting out. C is the time spent receiving a memory reload command from the console of the diagnostic processor or from the diagnostic program, setting various parameters, etc.

- It is generally known that A is larger than B and does not depend on the number of shift data per - cycle. This is because B mainly performs CPU processing such as field extraction and data formatting using logical and arithmetic operations on data, whereas A performs memory access such as table indexing and interface processing with other devices. This is because the main focus is on

Even when reading from the cache memory using the shift method described above, increasing the read width reduces the number of shifts and significantly shortens the read time. All you need to do is prepare a register with the data width required for memory access, and a wide register for reading from the cache memory is usually a read register or a 32-bit register.
This is not very realistic considering that there are 72 pins from the focus and that the memory configuration of the cache memory is not made to match the readout of the cache memory.

-i, the cache memory capacity is 671 to 1024 bits, and in conventional machines the cache memory cannot be read without performing a shift operation several thousand times, so the read time is increasingly dominated by parameter A. It turns out.

OBJECTS OF THE INVENTION An object of the present invention is to provide a cache memory control circuit that reduces the time required to read the entire contents of a cache memory.

A cache memory control circuit according to the present invention includes means for maintaining a cache memory in a read mode, means for sequentially incrementing a read address of the cache memory in this read mode, and a means for maintaining a cache memory in a read mode. It is characterized by having a data buffer for storing successive data from the cache memory, and means for sequentially incrementing the write address of this data buffer in a read mode.

In recent high-speed information processing devices, the data required by the arithmetic circuit is stored in a multi-word register called a data buffer, which is used to wait between other factors and control steps. It is designed to be stored in groups. In this case, the word location in the data buffer in which read data from the cache memory is stored is determined when the arithmetic unit issues a data request to the cache memory, along with the request at the data buffer word location (
It is added as a word address). The cache memory is configured to carry around this data buffer word location together with the request and send it to the arithmetic unit together with the access read data.

Therefore, in the present invention, attention is paid to this data buffer and its word location, and the cache memory is set in read mode, and the contents are read while sequentially incrementing the read address of the cache memory. The data is sequentially stored in the data buffer, and the data buffer word location is also sequentially incremented during this time.

K1 Decoy Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

First, in order to facilitate understanding of the explanation of the operation of this embodiment,
The operation during normal cache memory read access will be explained.

In an arithmetic processing unit, when the need for cache access occurs, the request address and data buffer word address are sent to the single word line 5 along with the cache access request.
1.57 and 58 to the cache memory. At this time, the cache read mode signal line (HD)
Since 75 has a logical value of 0, each request signal 51, 5
7.58 are respectively address selectors (8X) 1. via the request selector (RX) 2 and the data buffer word address selector (DX) 3, and further through the signal line 52.
．． Address register (ADR) 4 through 59.60,
It is stored in the request register “(RQ11?) 6 and the data buffer word address register (DB^1R) 7.

In the next cycle, the contents of ADR4 and the address array (A
A) The contents of 10 are compared by comparator 12. Note that the configuration of the cache memory here is assumed to be a Lebel (also referred to as a way or a compartment) set associative (direct mapping) cache memory. AAI in lower bit of ADR4
At the same time that O is addressed, the data array (O
A) 11 is also addressed with the same address.

When the output of the comparator 12 has a logical value of 1, the cache
), signal line 66, OR gate 13° signal line 68
The signal is input to the AND gate 14 through the . At this time, R
If the output 61 of the QIR 6 is a logical value 1, the logical condition of the AND gate 14 is satisfied, and the logical value 1 is stored in the register 2 (RQ2R) 15 to the refnis 1. On the other hand, D
The data buffer word address stored in IR7 is stored in data buffer word address register (DB8R) 16.

^The output of the DAll addressed by the lower bit of DR14 is sent to the AND gate 1 through the signal line 70.
The data register (D
AR) 17.

2T after the cache read access request is sent to the cache memory, the cache read data is sent to the arithmetic processing unit via the signal line 73 to the data array (DB
) sent to 18. At the same time, as a reply signal, II
The output of Q2R15 is sent through signal line 71 as the write address of the data buffer, and the output of D[1A2R1,6 is sent through signal line 72 to DBI8. The signal line 71 is used as a write enable (WE) signal for the DB 18.

Next, the cache read mode (HD) 75 has a logic value of 1.
The case will be explained below.

In this case, the output of the NOT circuit 9 becomes a logical value of 0, and the states of each selector are as follows. The output of the adder 5 is selected as the lower bit in the selector ^X1. A logic value of 1 is always input to the selector RX2, so that there is always a request. In the selector DX3, the output of the adder 8 is selected.

Further, the HD75 is input to the OR gate 13, and the signal line 6
Always turn 8 into 1 (hint). When the clock is advanced in this state, the DAII and the datum/y forward address are incremented sequentially, and the read data of the DAII is 0B1.
8. Assuming that the number of words in the DB 18 is 16, the read data is stored in 0818 one cycle after the read, so 16 words of data are stored in the DB from the address before advancing the clock by 17 cycles.
The data in AII is stored in DB18. Here, D
B18 can be put into shift mode and its contents can be read by a shift pass.

If ADIt4, RQIR6, and DBAIR7 are first initialized to 0 by the shift bus, (DAII
This means that the entire contents of DAII can be read out with +1 clock. In this case, when reading by shifting DB18 every 16 words, 80R
4 indicates the address of DI'tL1 to be read next, and DB
Since ^1R is set to O, you can just advance the clock as is after the angle gear division of the mode to shift 1.

As described in detail, according to the present invention, cache read data is stored in a data buffer and read out all at once.
Since the number of shuffles can be reduced and the first term of equation (1) for the cache read time described above becomes smaller, there is an effect that the time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the invention. Explanation of symbols of main parts 5.8...11 adder 10...Address array 11... Data array 18... Data buffer Figure 1 ：Tora calculation Tae iPΔPoor i force・6

Claims (1)

[Claims] (2) means for maintaining the cache memory in read mode; means for sequentially incrementing the read address of the cache memory during this read mode; and a data buffer for storing data read from the cache memory during this read mode. , means for sequentially incrementing the write address of the data buffer in a read mode.