JPS63158647A - Information processing device - Google Patents

Abstract

PURPOSE:To execute the reading of a variable-length data at high speed by providing a data buffer similar to the data buffer of a basic instruction processing device, to a variable-length data instruction processing device. CONSTITUTION:The basic instruction processing device 102 executes such a basic instruction as the four arithmetic operation of a floating point or of a fixed point. Besides, the variable-length data instruction processing device 104 executes a variable-length data instruction to process such the variable-length data as a decimal operation or a character operation. In this case, a data requesting part 12 outputs a read request which transfers the data necessitated for processing, from a cache storing part 101 to a data buffering part 11 or the data buffering part 17, to the device 101. In this constitution, by providing the buffering part 17, a waste, required for transferring the data from a first register 14 to a second register 16, is eliminated, and the reading of the variable- length data, necessitated at the time of the execution of the variable-length data instruction, can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device including variable length data instructions.

[Conventional technology]

Conventionally, this type of information device has had a configuration as shown in FIG. In the figure, a cashier storage device 101 transfers data from the main storage device to a data buffer, processes data processed by the basic instruction processing unit 13 of the basic instruction processing device 102, and processes variable-length data instructions in the variable-length data instruction processing device 103. This is a buffer storage device for transferring data processed by the unit 15 to the main storage device. The basic instruction processing unit 102 is composed of a data buffer section 11, a data request section 12, a basic instruction processing section 13, and a second register 16, and mainly includes basic instructions such as four arithmetic operations on floating point data or #'i identified decimal point data. Execute all. The variable length data instruction processing device 103 is composed of a second register 16 and a variable length data instruction processing section 15, and mainly executes variable length data instructions for processing variable length data such as decimal operations and character operations.

Next, each part of the basic instruction processing device 102 and the variable length data instruction processing device 103 will be explained.

The data request unit 12 is controlled by firmware and outputs a read request for transferring data required for processing from the cache storage device 101 to the data buffer unit 11 to the cache storage device 101 together with address information of the data, In addition, the basic instruction processing unit [
The data processed by the variable length data command processing unit 102 and the variable length data command processing unit 103 is output to the ride request cashier storage unit 101, which transfers it to the main storage unit.

The data buffer section 11ti is configured as shown in FIG. Read address section 23 and write address section 2
4 specifies the read address or write address of the data buffer 21 (hereinafter referred to as DB) and the V bit register 22, respectively.

DB 21t Holds data transferred from the cache storage device 101. The set signal is the reply signal S1 of the read request output from the cache storage device 101. Therefore, cache storage device 101
The read data R1 and the reply signal S1 outputted from the DB 21 are simultaneously inputted to the DB 21.

The V bit register 22 has bits corresponding to each word of the DB 21, and the V bit register 22 has bits corresponding to each word of the DB 21.
A bit corresponding to a write word of 1 is set by the reply signal S1 to indicate whether each word of the DB 21 is valid data. When reading requested data from the DB 21 to the register 14, the V bit register 22 corresponding to the word of the DB 21 read out by the read data buffer signal of the firmware is read.
bits are examined. When the bit to be checked is set, data from the DB 21 is stored in the register 14, and at the same time, the bit checked in the V bit register 22 is reset, the read address field 22 is set, and the read address increments 1. be done. Also, if the bit to be checked is in the reset state, the V bit register '22
, DB21, and write address section 241&: basic instruction processing section ff102 and variable length data instruction processing device 1
All registers in 03 send out a signal S2 which holds this bit to be tested until it is in the set state.

The register 14 stores data from the DB 21 and outputs the stored data to the basic instruction processing section 13 and the variable length data instruction processing device 103, and is provided for the following reason. In other words, since the DB 21 is configured with a register file, the propagation time until the data is output from the DB 21 is very expensive. The delay time becomes longer than one clock time. For this reason, the LUGister 14 divides the propagation time by storing data from the DB 21, and stores the data between the DB21 and the LUGister 14, between the LUGister and the basic instruction processing unit 13, and from the LUGister 14 to the variable length data instruction. Each propagation delay time between processing units is made to be less than one clock time.

The basic instruction processing unit 13 receives data from the register 14 and executes basic instructions.

The second register 16 stores data from the register 14 and outputs it to the variable length data instruction processing device 103, and is provided for the following reason. That is, since the basic instruction processing device 102 and the variable length data instruction processing device 103 each have an adder and a chic that can process in units of words, they are generally made up of a plurality of cards with a large amount of hardware. Therefore, since the basic instruction processing device 102 and the variable-length data instruction processing device 103 are physically separated, the data propagation delay time between these two devices is large. In this case, it is necessary to store the register output data directly in the register. The second register 16 is a data input register of the variable length data instruction processing device 103 provided for this purpose.

The variable length data instruction processing unit 15 receives data from the second register 16 and executes the variable length data instruction.

When executing a variable length data instruction in such a data processing device, variable length data t- must first be prepared in the variable length data instruction processing section 15. FIG. 5 is a 70-chart showing this operation. The step person determines whether the data is to be processed, that is, whether the data length is zero. If the data length is zero, the process branches to step F, and if it is not zero, the process branches to step B. Step B outputs a read request from the data request unit 12 to the cache crystal storage device 101. Step C is held until the request data is set in DB21, and it is
When set to 21, 1 is added to the address of the data request section and the 1st Lujistor IIC request data is stored. In step D, the request data stored in the register 14 is stored in the second register 16.

Step E outputs the request data stored in the second register 16 to the variable length data instruction processing section 15.

Further, in this step, if the data read by the request is shorter than the data required for processing the instruction, the process branches to step B without branching to step FK. When branching to step B, the same operation as above is performed and the next one word of data is read out. In step F, since variable length data is prepared, data processing is started.

In order to perform the above operations, K at which to start reading data of 2 and 3.4 words is 10 and 14, respectively.
．． The time required is the sum of 18 clock times and hold time.

[Problem that the invention seeks to solve]

When executing a variable length instruction in a conventional information processing device configured in this way, the data in the data buffer is first stored in the first register, then stored in the second register at the next clock, and then stored at the next clock. Since data processing is performed by the variable-length data command processing section, there is a drawback that the greater the number of requests for variable-length data, the greater the waste of data transfer time, which degrades the performance of the information processing apparatus.

Therefore, the problem to be solved by the present invention, in other words, the purpose of the present invention is to provide an information processing apparatus that improves the above-mentioned drawbacks by providing a route that shortens the data transfer time.

[Means for solving problems]

The information processing device of the present invention has a cache crystal storage device that holds a part of data stored in a main storage device, and a first data buffer that holds data transferred from the cache storage device, and has basic instructions. It is configured to include a basic instruction processing device that mainly processes, and a variable length data instruction processing device that mainly processes variable length data and has a second data buffer that holds data transferred from the cache crystal storage device. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the same figure, a cache storage device 101 is a basic instruction processing unit f that transfers data from the main storage device to a data buffer.
This is a buffer storage device for transferring data processed by the basic instruction processing unit 13 of the iik 102 and data processed by the variable length data instruction processing unit 15 of the variable length instruction device 104 to the main storage device. Basic instruction processing unit R1
02 is a data buffer section 11, a data request section 12
, a basic instruction processing unit 13, and a first register 14, and mainly executes basic instructions such as four arithmetic operations on floating point data or fixed point data. The variable length data instruction processing unit f104 is composed of a data buffer unit 17, a second register 16, and a variable length data instruction processing unit 15, and mainly processes variable length data such as decimal operations and character operations. Execute commands.

Next, each part of the basic instruction processing device 102 and the variable length data instruction processing device 104 will be explained.

The data request section 12 is controlled by firmware, and outputs a read request to the cache storage device 101 to transfer data required for processing from the cache storage device 101 to the data buffer section 11 or 17, and also outputs a read request to the cache storage device 101. and outputs a ride request to the cache storage device 101 to transfer the data processed by the variable length data instruction processing device 104 to the main storage device.

The data buffer section 11 is configured as shown in FIG. Read address section 23 and write address section 24
specifies the read address or write address of the data buffer 21 (hereinafter referred to as data buffer DB) and the V bit register 22, respectively.

The data transferred from the DB21ii cache storage device 101 is held. The set signal is the rewrite signal S1 of the read request output from the cache storage device 101. Therefore cache storage device 1
Read data R1 and rib 2 signal S output from 01
1 are input to the DB 21 at the same time.

■The bit register 22 has bits corresponding to each word of the DB 21, and the bit register 22 has bits corresponding to each word of the DB 21, and the bit register 22 has bits corresponding to each word of the DB 21, and
The bit corresponding to the write word of DB 21 is set by the reply signal S1 to indicate whether or not each word of the DB 21 is valid data. When reading requested data from the DB 21 to the register 14, the V bit register 22 corresponds to the word of the DB 21 read by the read data buffer signal of the firmware.
bits are examined. If the checked bit is set, the data is stored from the DB 21 to the register 14, and at the same time the checked bit of the KV pit register 22 is reset and the read address section 23 is set and the read address Fil is added. be done. Also, if the bit to be checked is in the reset state, the V bit register 22
, DB21, DB31 (described later), the write address section 24, and the write address section 33 (described later), all registers in the basic instruction processing unit 102 and the variable length data instruction processing unit 103 are Hold signal S2 that is held until the set state is reached
Send out.

The first register 14 stores the data read from the DB 21 and outputs it to the basic instruction processing section 13, and the basic instruction processing section 13 inputs the data output from the second first register 14 and executes the basic command.

The data buffer section 17 is composed of a data buffer 31, a read address section 32, and a write address section 33, as shown in FIG.

The DB 31 and the write address section 33 perform the same operations as the DB 21 and the write address section 24 described above, respectively. Further, the read address section 32 operates in the same manner as the read address section 23 except that the read address is held by the hold signal S2 of the data buffer section 11 described above.

The second register 16 stores the data read from the DB 31 and outputs the data to the variable length data instruction processing section 15, and the variable length data instruction processing section 15 inputs the data output from the second register 16 and outputs the data to the variable length data instruction processing section 15. Execute commands.

Next, read the processing data necessary before processing the variable length data instruction! The flowchart of FIG. 6 showing t' will be explained. Step N1 determines whether the variable length data length is zero, and if it is zero, the process branches to step N5, and if it is not zero, the process branches to step N2.

Step N2 outputs a read request from the data request unit 12 to the cache storage device 101. Step N3 is held until the request data is set in DB21 and DB31.
When set, 1 is added to the address of the data request unit 12 and the request data is stored in the second register 16. Step N4 outputs the request data stored in the second register 16 to the variable length data instruction processing section 15. In addition, if the data read by the request is shorter than the data required to process the instruction, this step does not branch to step N5 and step N
Branch into 2. When branching to step N2, the same operation as above is performed and the next one word of data is read out. In step N5, since the variable length data has been prepared, processing of the data is started.

When a variable length data instruction is executed by such an information processing device, 2.3. In order to start the process of reading 4 words of data, the sum of 8 and 11°14 clock times plus the hold time is required, respectively. Therefore, the time explained in the conventional example can be shortened by 2 and 3.4 clock times, respectively.

〔Effect of the invention〕

As explained above, the present invention eliminates the need to provide a variable-length data instruction processing device with a data buffer similar to the data buffer of the basic instruction processing device, and eliminates the waste required for data transfer between the first register and the second register. This has the advantage that reading of variable length data required when executing a variable length data instruction can be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional example, FIG. 3 is a block diagram showing a data buffer section of a basic instruction processing device, and FIG. 4 is a block diagram showing a variable length data instruction. a block diagram showing a data buffer section of the processing device;
FIG. 5 is a flowchart showing a procedure for reading variable length data in a conventional example, and FIG. 6 is a flowchart showing a procedure for reading variable length data in an embodiment. Part, 12... Data request part, 13...
...Basic instruction processing unit, 14th... Lujista,
15... Method for writing procedural amendments), 2, 1.27 Showa year, month, day 1, case description 1985 Patent Application No. 182424 2
, Title of the invention Information processing device 3, Relationship with the case of the person making the amendment Application Colonel Office
5-33-1 Shiba, Minato-ku, Tokyo Name (423)
) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent Address: Sumitomo Sanda Building, 37-8 Shiba 5-chome, Minato-ku, Tokyo 108 Telephone: Tokyo (03) 456-3111 (Main Representative) (
Contact information: NEC Corporation Patent Department) 5. Date of amendment order: December 22, 1988 (shipment date) 6. Figure 5 of the drawing subject to the amendment. 7. Details of the amendments are as shown in the attached sheet.

Claims (1)

[Claims] a basic instruction processing device that mainly processes basic instructions and has a cache storage device that holds part of the data stored in the main storage device, and a first data buffer that holds data transferred from the cache storage device; An information processing device comprising: a variable length data instruction processing device that has a second data buffer that holds data transferred from the cache storage device and mainly processes variable length data.