JPH0298754A - Main storage control system - Google Patents

Abstract

PURPOSE:To accelerate a partial write store processing by performing the readout and write of data in byte unit from a store buffer to a cache, and performing data transfer to a main memory device by performing the readout of the data in the store buffer and the cache in byte unit with the same timing. CONSTITUTION:Store data in byte unit set as effective by store mask information in a store mask buffer 1 is read out from the store buffer 2 for the store instruction of partial write in cache hit, and it is written in byte unit of corresponding data in the cache 6. The store data in byte unit set as ineffective in the store mask information is read out from the cache 6, then, the merge of the data read out from the store buffer 2 and the data read out from the cache 6 is performed. At this time, the store mask information is set as effective for all store data in byte unit, and it is swept to the main memory device with coupled store data. In such a way, it is possible to perform a store instruction processing at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data transfer processing from a central processing unit to a main storage device, and particularly to a full write data transfer processing method for partially written store data.

[Conventional technology]

Conventionally, in this type of Vibrine type information processing device, partial write store processing to the main memory at the time of cache hit involves reading valid store data from the main memory multiple times, compared to full write store processing.
Because it is necessary to merge the read data and transfer it to the cache or main memory, the store process requires a significant amount of processing time, making it necessary to perform an all-write process on the partial write store process. there was.

In the conventional technology, the processing method for executing full write store processing of partial write store processing is to first read the partial write store data from the cache, merge it with valid data, and then write it to the cache and main storage again. A processing method called full write by writing data into the cache, or first writing valid store data to the cache.
There is a processing method called full write by reading the data from the cache and writing it to the main storage device.

[Problem to be solved by the invention]

However, in the conventional full write processing method of partial write store processing described above, the cache is
Since this processing method requires multiple accesses, it has not been possible to put this processing method into practical use in high-speed machines where store processing is made into one cycle.

Therefore, a technical object of the present invention is to provide an information processing apparatus that processes store commands at high speed.

[Means to solve the problem]

According to the present invention, in an information processing device that has a store buffer and includes an arithmetic unit and a main memory device that support execution of an instruction that requires a partial write store process, a partial write store instruction at the time of a cache hit is provided. On the other hand, the store mask information indicating the valid byte unit of the store data of the store instruction is referred to, and for the store data in the byte unit that is shown to be valid in the store mask information, the store data in the store buffer is Reads valid byte-by-byte store data, writes valid byte-by-byte store data in the store buffer to the corresponding byte-by-byte data in the cache, and writes invalid byte-by-byte store data in the cache to the cache. For byte-based store data that is indicated as being present, read the byte-based store data of the corresponding data in the cache, merge the store data read from the store buffer and cache, and obtain the store mask information. A main memory $IJWJ method is obtained which is valid for all byte-based store data and is characterized in that it is flushed to the main memory together with the combined store data.

In other words, the present invention allows the store command received by the store buffer, A, to be partially written (
If it is a partial write, it has a means for determining whether it is a partial write (partial write) or a full write (all write). means for reading byte-based store data that is valid from the store buffer according to the information shown in the cache, and store mask information related to the store data for byte-based cache data whose store mask value is 1'. means for writing valid byte-based store data of the store data in the store data buffer into the cache; and means for reading byte-based cache data whose store mask value is 0 from the cache;
A means for merging each valid byte-by-byte store data read from the store data buffer and cache and transferring it to the main memory as complete data, and effective for all bytes to be transferred to the main memory. store mask information regarding the store data that is a111
and means for transferring the data to the main storage device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows the operation of the block diagram of the embodiment of the invention shown in FIG. 1 and the vibration line processing operation shown in FIG. It is a figure showing a time chart.

FIG. 3 is a diagram showing an example of the vibe line processing, which is divided into six stages from stage IF to stage ST. Stage IF is the process of fetching instructions, stage AC is the process of generating operand addresses, stage AT is the process of converting logical addresses to real addresses, stage CA is the process of reading operands, and stage EX is arithmetic processing of the read operands. , and stage ST performs storage processing of the calculation results. Hereinafter, embodiments of the present invention will be described with the vibrine stage shown in FIG. 3 facing downward.

In the embodiment of the present invention, store data and cache data consist of 8-byte data, store data has store mask information in 1-byte units, and cache data can be accessed for writing and reading in 1-byte units. .

The embodiment will be described with reference to the block diagram of FIG. 1 and the time chart of FIG. 2. When store instruction A is accepted by the IF stage in cycle t1, store data and store mask information regarding store instruction A are stored in cycle t6. are each store data buffer 2. Written to store mask buffer 1. In cycle [7], if it is possible to flush from the store buffer to the stage below it, and if it is a cash hit, the store data and store mask information regarding store instruction A are stored in store data buffer 2. When the store mask information is read from the store mask buffer l, the true output of the store mask information is stored in the cache write instruction register 7, and the complement (Co) of the store mask information is stored in the cache write instruction register 7.
iplement) The cache data is read by using the output as a valid byte-by-byte read instruction signal of the cache data of the word corresponding to the store instruction A. At the store data buffer 2, the logical product of the true output of the store mask information and the store data is performed, and the valid byte unit store data is merged with the valid byte unit store data read from the cache. It is stored in the main memory write wait store data register 5 and also in the cache write wait register 6. In addition, for the main memory write wait store mask register 4, the True output from the store mask buffer 1 and (Coipl
cment ) output, i.e. °all'
Store. In cycle 8, store A'', which is the degenerated data of store A, and store mask information, which is al11', are transferred to the main memory. Also, the byte-based data in the cache write wait register 6 is transferred to the cache. It is written in valid byte units of the word corresponding to the store instruction.At this time, the corresponding word in the cache has registered data store A', which is equal to the data transferred to the main memory. .A more specific example will be described.

Assuming that there is a store mask in store mask buffer 1 in which the upper 4b is 1° and the lower 4b is 0', in the cycle of reading data from store buffer 2, the upper 4 bytes of toss store data whose store mask information is 1' is stored in the upper 4 bytes of the main memory write wait register 5, and in the same cycle, the upper 4B cache data whose store mask information is 0 is read from the corresponding word in the cache and becomes the main memory write wait store data. It is stored in the upper 4B of register 5. Therefore, there are 8 bytes of valid data in the main memory write-waiting store data register 5. In the same cycle, the True output of store mask buffer 1 and
The logical OR value of the +gent output, that is, all', is stored in the main memory write wait store mask register 4.

In addition, for the cache write wait register 6, store data in bytes with store mask information of “1°”,
In other words, the upper 4B store data is stored. In the next cycle, the transfer to the main memory and the writing of valid byte-by-byte data to the corresponding word in the cache 3 are performed. As a result, the data transferred to the main memory and the 8-byte data present in the corresponding word in the cache 3 become equal in value.

〔Effect of the invention〕

As explained above, the present invention reads and writes data from the store buffer to the cache in byte units in the partial write store processing at the time of cache hit, and at the same timing, writes the data to the main storage device at the same timing. Data can be transferred to the main memory by reading data in the store buffer and cache in bytes, and partial write store processing can be made full written by accessing the cache in only one cycle, making partial write store processing faster. There is an effect that can be processed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing a time chart in one embodiment of the block diagram shown in FIG. 1. FIG. 3 is a diagram showing an example of vibe line processing in an embodiment of the present invention. 1... Store mask buffer, 2... Store data buffer, 3... Cache, 4... Store mask register waiting for main memory writing, 5... Store data register waiting for main memory writing, 6... Cache write wait register, 7... Cache write instruction register.

Claims (1)

[Scope of Claims] 1) In an information processing device including a main storage device and an arithmetic unit that has a store buffer and supports execution of instructions that require partial write store processing, For a store instruction, the store mask information indicating the valid byte unit of the store data of the store instruction is referred to, and the store buffer reads the valid byte-by-byte store data in the store buffer, and writes the valid byte-by-byte store data in the store buffer into the byte-by-byte corresponding data in the cache; For byte-wise store data that is indicated as invalid, read the byte-wise store data of the corresponding data in the cache,
It is characterized by merging the store data read from the store buffer and cache, making the store mask information valid for all byte unit store data, and flushing the combined store data to the main storage device. Main memory control method.