JPH0298755A - Cache nullification processing system - Google Patents

Abstract

PURPOSE:To prevent registered block data from being deleted wastefully and to accelerate performance by providing identification information to separate block data with different (n) kinds of meaning in unit of block data, and performing a nullification processing selectively on the information classified by every kind. CONSTITUTION:An identification information storage means 2 stores the information to identify block data with different (n) kinds of meaning in a cache memory 1 when plural pieces of block data are registered. An identification information readout register 9 receives the identification information corresponding to the block data read out from the identification information storage means 2 by a read address register 4, and nullification instructing registers 10 and 11 issue instructions to nullify the block data registered on the cache memory 1 individually. In such a way, it is possible to prevent the nullification processing from being applied on all block data, and to accelerate the performance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a method for individually invalidating n types of block data having different meanings or sizes registered in a cache memory of a buffer storage device. This invention relates to a block data invalidation processing method that makes it possible to block data.

[Conventional technology]

Conventionally, block data registered in a set-associative cache memory in a buffer storage device has no distinction based on the meaning of each block data, and is treated as block data defined by a certain block size. In other words, from the perspective of the cache memory, all blocks were treated as equivalent block data. For example, when registering operand block data and instruction block data in this cache memory, if you want to invalidate one of the block data, there is no way to distinguish between them, so register them in the cache memory. All block data that was set was invalidated. Also, for example, if you want to invalidate block data that has a special meaning other than the above after registering it in the cache memory and using it,
All block data registered in cache memory was invalidated.

In addition, conventionally, when the block sizes of block data registered in the set associative cache memory in a buffer storage device are different, the block data is configured using the minimum block size (m bytes) as the reference block size, and 2e pieces of block data are configured. By creating block data with different block sizes, it was possible to register block data with different block sizes on the cache memory.

However, even if you want to invalidate a certain block size of block data on the cache memory. Since there is no distinction based on the size of block data, the invalidation process has been performed by invalidating all block data.

(Problems to be Solved by the Invention) In the above-mentioned invalidation processing method in the set associative cache memory in the conventional buffer storage device,
Even if there is block data that has been read out from the main memory and registered in the cache memory over time, and you want to invalidate some of the block data or have some kind of meaning, First, all block data is invalidated, which has the disadvantage of slow performance.

[Means to solve the problem]

According to the invention, nf! In a buffer storage device equipped with a set-associative cache memory that allows block data with different meanings to be stored, information for identifying block data with different meanings in nFi is stored in units of block data. By the identification information storage means and the identification information read from the identification information storage means,
nFI! has an invalidation processing means for individually invalidating block data of different meanings of nff1 from the cache memory, and nFI! A cache invalidation processing method is obtained that enables block data of 1 to be invalidated individually from the cache memory.

Further, according to the present invention, m bytes of block data and m
In a buffer storage device equipped with a set associative type cache memory that makes it possible to store block data with different nH sizes of block data using 2° block data of bytes. , an identification information storage means for storing information for identifying n types of block data of different sizes corresponding to m byte block data, and identification information read from the identification information storage means,
and invalidation processing means for individually invalidating n types of block data of different sizes from the cache memory, and invalidating block data of n14 different sizes individually from the cache memory. A cache invalidation processing method is obtained that enables this.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a cache invalidation processing method for individually invalidating block data in a buffer storage device according to a first embodiment of the present invention.

The cache memory 1 is a cache memory using a set associative method, and stores, for example, block data An and block data Bn.

In the identification information storage means 2, when a plurality of 0 types of block data with different meanings are registered in the cache memory 1, the identification information storage means 2 stores information for identifying them in (for example, 2 types; block data An/block data Bn). information (for example, 1
bits; 0 niblock data An, 1 niblock data Bn) are stored.

The read address register 4 is an address register for reading the V bit (bit indicating validity of block data) of block data from the cache memory 1.

The address rotation register 6 is a register that receives the contents of the read address register 4.

The write address register 5 is an address register for writing V bits of block data into the cache memory 1.

The address counter 7 is a counter for updating an address when block data in the cache memory 1 is invalidated, and increments the address information in the read address register 4 by 1.

The V bit read register 8 stores the v bit read from the cache memory 1 by the read address register 4.
A register that receives bits.

The identification information read register 9 reads the information read from the identification information storage means 2 by the read address register 4.
This is a register that receives identification information corresponding to block data.

The invalidation instruction An register 10 is a register that instructs to invalidate block data An registered in the cache memory 1.

The invalidation instruction Bn register 11 is a register that instructs to invalidate block data Bn registered in the cache memory l.

Gates 13 to 15 repeat and invert the outputs of invalidation instruction An register 10/invalidation instruction Bn register 11/identification information read register 9, respectively.

AND/Nand gate 16 AND/NANDs the inverted output of gate 13 and the inverted output of gate 14. AND gate 17 connects the repeat output of gate 13 and gate 14.
AND with the inverted output of.

AND gate 18 connects the inverted output of gate 13 and gate 1
AND the repeat output of 4. The NAND gate 19 NANDs the output of the NAND gate 17 and the inverted output of the gate 15. The Nandt gate 20 NANDs the output of the AND gate 18 and the repeat output of the gate 15. Nant gate 21 connects the repeat output of gate 13 and gate 1
NAND the repeat output of 4. The AND/Nant gate 22 NAND/ANDs the outputs of the Nant gates 19 to 21.

The selector 23 selects the V bit read register 8 or the fixed value "0°" according to the output of the AND/Nant gate 22.

Next, the operation of the first embodiment will be explained.

Assume that the cache memory 1 is in a state as shown in FIG. 3(1).

Furthermore, if a request to invalidate block data An is issued to cache memory 1, invalidation instruction An
Register 10 is “1°, invalidation instruction Bn register is 02”
is set to Here, the addresses in the read address register 4 are counted up from all '0' to all '1' using the address counter 7. This means that all set addresses for cache memory 1 are created. By doing so, the V bits read from the cache memory 1 according to the read address indicated by the read address register 4 are successively read to the V bit read register 8. Furthermore, in the same manner, identification information is read out one after another from the identification information storage means 2 to the identification information reading register 9.

The contents of the read address register 4 are transferred to the address rotation register 6 at the same timing as the V bit is read to the V bit read register 8.

The address received in the address rotation register 6 is used as the address for writing the V-bit information received in the V-bit write register 12 to the cache memory 1 at the next timing, and the address received in the write address register 5 is used as the address for writing the V-bit information that is received in the V-bit write register 12 at the next timing. It will be done. In synchronization with the address operation as described above, the second According to the truth table shown in the figure, gates 13 to 15,
AND/Nante Gate 16, 22, AND Gate 17,
18. The contents of the V bit read register 8 are invalidated (
“0°) or as is (Vn) is sent to the V bit write register 12.

After this operation, the V bit is written to the cache memory l.

If these operations are performed continuously in the vibe line method, the cache memory 1 that was in the state shown in Figure 3 (1) will change to the state shown in Figure 3 (2) where all the V bits of the block data An are invalidated. It becomes a converted state.

Conversely, if a request to invalidate block data Bn is issued to cache memory 1, invalidation instruction Bn
Register 11 becomes “1”, invalidation instruction An register 10
is set to "0'".

If the same operation as described above is repeated, the cache memory 1 changes from the state shown in FIG. 3(1) to the state shown in FIG. 3(3), and all block data Bn disappears from the cache memory l.

Furthermore, when a request is issued to the cache memory 1 to invalidate all block data, the invalidation instruction An
Both the register 10 and the invalidation instruction Bn register 11 are set to "11," and by repeating the same operation as described above, all blocks are changed from the state shown in FIG. 3 (1) to the state shown in FIG. 3 (4). The data becomes invalidated.

Here, the explanation is based on two types of block data, but
It goes without saying that even block data of n14 can be invalidated to 1 by a similar operation.

In FIG. 1, a cache invalidation processing method for individually invalidating block data in a buffer storage device according to a second embodiment of the present invention is such that a cache memory 1 is a cache memory using a set associative method; For example, block data An (n bytes) and 8 blocks of block data (2n bytes) are stored, and the identification information storage means 2 registers 0 types of block data of different sizes in the cache memory 1. If there are, for example, two types of block data An/block data Bn, information for identifying them (for example, 1 bit; 0 ni block data An, 1 ni block data Bn) should be stored in units of block data An. The second embodiment is the same as the first embodiment except for the following.

Next, the operation of the second embodiment will be explained.

Assume that the cache memory 1 is in a state as shown in FIG. 4(1).

Furthermore, if a request to invalidate block data An is issued to cache memory 1, invalidation instruction An
Register 10 is set to “1” and invalidation instruction Bn register is set to “Oa”.
is set to Here, the addresses in the read address register 4 are counted up from all '0' to all '1' using the address counter 7. This means that all set addresses for cache memory 1 are created. By doing so, the V bits read from the cache memory 1 according to the read address indicated by the read address register 4 are successively read to the V bit read register 8. Furthermore, in the same manner, identification information is read out one after another from the identification information storage means 2 to the identification information reading register 9.

The contents of the read address register 4 are transferred to the address rotation register 6 at the same timing as the V bit is read to the V bit read register 8.

The address received in the address rotation register 6 is used as the address for writing the V-bit information received in the V-bit write register 12 to the cache memory 1 at the next timing, and the address received in the write address register 5 is used as the address for writing the V-bit information that is received in the V-bit write register 12 at the next timing. The identification information read register 9 and the invalidation instruction An register 1, which are at the same stage as the address rotation register 6, operate in synchronization with the address that is being read as described above.
0 and the output of the invalidation instruction Bn register 11,
Gates 13 to 15, AND/Nant gates 16 and 22, and AND gate 17.1
8. The contents of the V bit read register 8 are invalidated (“
0") or as is (Vn) is sent to the V-bit write register 12.

After this operation, the V bit is written to the cache memory 1.

If these operations are performed continuously in a pipelined manner, the cat's memory 1 in the state shown in FIG. 4 (1) will become
As shown in FIG. 4(2), all the V bits of the block data An are invalidated.

Conversely, if a request to invalidate block data Bn is issued to cache memory 1, invalidation instruction Bn
When register 11 is “1°,” invalidation instruction An register 10
is set to "0".

If the same operation as described above is repeated, the cache memory 1 changes from the state shown in FIG. 4(1) to the state shown in FIG. 4(3), and all block data Bn disappears from the cache memory 1.

Furthermore, when a request is issued to the cache memory 1 to invalidate all block data, the invalidation instruction An
Both the register 10 and the invalidation instruction Bn register 11 are set to "1°," and by repeating the same operation as described above, the state shown in FIG. 4(1) is changed to the state shown in FIG. 4(4). The block data becomes invalidated.

Here, the explanation is based on two types of block data, but
It goes without saying that even n types of block data can be invalidated by the same operation.

〔Effect of the invention〕

As explained above, the present invention provides identification information for differentiating block data with different meanings or sizes in the block data unit (minimum block data unit), so that it can be selectively classified by type. Since invalidation processing can be performed immediately, the block data registered in the cache memory can be left in the cache memory in the R-enabled state without being wasted, resulting in faster performance. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of the first and second embodiments of the present invention, and FIG. 2 is a block diagram showing a configuration example of the invalidation processing means 3 of FIG.
Truth table showing the logical operation during invalidation processing in , Part 3
4 and 4 are diagrams for explaining the operation of the invalidation process in the first and second embodiments, respectively, where (1) is before the invalidation process, and (2) is the invalidation process of block data An. After execution, (3) executes the invalidation process of block data Bn,
(4) is a state diagram of the cache memory 1 after all block data is invalidated. DESCRIPTION OF SYMBOLS 1... Cache memory, 2... Identification information storage means, 3... Invalidation processing means, 4... Read address register, 5... Write address register, 6... Address rotation register, 7...address counter,
8...V bit read register, 9...Identification information read register, 10...Invalidation instruction An register, 11...Invalidation instruction Bn register, 12...V bit write register, 13-15 ...gate, 16
゜22...And/Nante Gate, 17-18...
And Gate, 19-21... Nantes Gate, 23.
...Selector. Mesuga; Yo? Effect? 31 no no N no no no no ゝ″' 0-O-0-0- o8; 6EOO221no+7-me I+J\ノ\nono

Claims (1)

[Scope of Claims] 1. In a buffer storage device equipped with a set associative cache memory capable of storing n types of block data with different meanings, the n types of blocks with different meanings are provided. an identification information storage means for storing data identification information in units of block data, and each of the n types of block data having different meanings from the cache memory by the identification information read from the identification information storage means. and invalidation processing means for individually invalidating the data, the cache invalidation processing method making it possible to individually invalidate the n types of block data from the cache memory. 2. Set associative that makes it possible to store m-byte block data and n types of block data using 2^e blocks of m-byte block data with different sizes. In a buffer storage device equipped with a cache memory of the above-mentioned method, an identification information storage means for storing information for identifying the n types of block data of different sizes in correspondence with block data of m bytes; and the identification information storage. invalidation processing means for individually invalidating the block data of the n types of different sizes from the cache memory according to the identification information read from the means; A cache invalidation processing method that makes it possible to individually invalidate different block data from the cache memory.