JPS6244838A - Instruction fetching device - Google Patents

Abstract

PURPOSE:To improve the processing speed of an information processor including an instruction fetching device by instantaneously fetching an instruction word for a loaded block from an instruction buffer and supplying the instruction word to an execution stage. CONSTITUTION:At the reception of a start command, a block load is requested to a cache memory by using the value of an instruction counter 12 as an access address. Block '0' is selected as the block No. to be loaded at first. A control circuit 22 writes response information obtained from the cache memory in respective words in the block '0'. The control circuit 22 sets up a block No. signal 20 in a block No. part of an instruction pointer 7, so that instruction words are successively read out by the lower 7 bits of the pointer 7. A request is outputted to the cache memory, and during the returning of its response information, loaded block No. registers 8, 9 are updated. When all the lower 7 bits of the pointer 7 become '1', instructions are continuously read out from the loaded block.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction fetching device in a high-speed information processing device.

[Prior art]

In recent years, in high-speed information processing devices, in parallel with the execution of an instruction, an instruction sequence subsequent to the instruction sequence currently being executed is read out from a cache memory.

It often has an instruction buffer to temporarily store this information. It also has a series of processing stages corresponding to each process of fetching instructions from the instruction processor, decoding instructions, and preparing operands, and processes instructions by sequentially passing them through the series of stages at the cycle of the machine cycle. Mother Eveline treatment is often performed.

Conventionally, one method for fetching instructions in processing devices dedicated to scientific and technical calculations is to increase the capacity of the instruction buffer to, for example, a number of bytes, divide it into multiple blocks, and store the instructions in the instruction word area of the storage device. A means is provided to transfer the instruction word being executed block by block to the block on the instruction puncher, and at the same time to hold the instruction address of the instruction word held in the block for each block of the instruction buffer, and to transfer the instruction word to be decoded. There is a method in which the block number on the instruction table is obtained by searching the address of the address holding means using the instruction address of , and the instructions are sequentially taken out from the block to the decoding stage.

Note that the address on the instruction buffer is different from the address on the main memory, and is composed of a block number on the instruction buffer, a load number within the block, and sometimes a word white number.

[Problem to be solved by the invention]

The problem with the above method is that when moving to the first instruction word of an attack in main memory (hereinafter the case on the left is referred to as block crossing), if the block ahead of the block is searched,
This is the point where there is a delay in reading the instruction words of other blocks.

In other words, it takes time to extract the block number at the end of the block image.

If the block number of the block destination is determined after detecting from the read address register Ω value that it is the last instruction in the block, there is a drawback that a delay occurs in the readout.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an instruction fetching device which solves the above-mentioned delay in fetching instructions when a block is exceeded.

[Means for solving problems]

In order to achieve the above object, the instruction retrieval device of the present invention has, in addition to the conventional instruction retrieval method, a means for holding the block number of the block destination for each block of the instruction/retrieval sofa. It is.

That is, according to the present invention, there is an instruction buffer that holds instruction words read from a storage device in block units, and instruction words that are held in a group of blocks corresponding to one or several blocks on the instruction buffer. an instruction counter that holds the upper bits of the address of the instruction word being read from the instruction buffer; and an address holding means for holding the address of the instruction word being read from the instruction buffer; an instruction pointer indicating the instruction buffer; block number holding means for holding a number of a block following the block as viewed from the address of the storage device corresponding to each block on the instruction buffer; indicating means for indicating whether or not a block corresponding to a block number in the number holding means exists in the instruction buffer; and indicating means for indicating whether or not a block corresponding to a block number in the number holding means exists in the instruction buffer; In the first case where the indicating means indicates that a block detected by the instruction pointer and corresponding to the block number in the block number holding means of the block exists in the instruction/97a; puts that value into the instruction pointer, and also detects from the instruction pointer that the instruction read from the instruction is the last instruction in the block and stores the block number in the block number holding means of the block. In the second case where the indicating means indicates that the block corresponding to the block number does not exist in the instruction buffer, the memory storing the block corresponding to the block number in the block number holding means and means for comparing the value of the instruction counter or the value obtained by adding or subtracting the value of the instruction counter in binary form with the value of the address holding means, while sending a request to the means and receiving response information. Thus, an instruction fetching device is obtained, which is characterized in that in the first case, the instruction word reading is performed successively, and in the second case, the value of the block number holding means is updated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an instruction fetching device which is an embodiment of the present invention. In this example, the instruction length is 4 bytes or 3
The logical address of the instruction is a 30-bit byte address.

In FIG. 1, the instruction buffer 3 has a configuration of 32 bytes x 64 words, which can be read and written simultaneously using memory elements, and is used as a block 0°1.2.3 every 16 words. Each block contains one block of instruction information in cache memory, i.e. 51 blocks starting from a 512 byte boundary.
Two bytes of information are loaded. Write data register 2
←Gin←≠! " , , , ÷ ÷ + → 〒 → is a register that once receives the response information from the cache memory and is written to the instruction buffer 3 when loading. It is a 32-byte register. The selector 4 is a 32-byte register. The output is strobed into the 4-byte instruction register 5.

Start address registers 14 and 15 are instruction buffer 3
The four blocks each hold the upper 23 bits of the address of the instruction word held in block 0 to block 3.
This figure shows the top address registers with some parts omitted. Registers 8 and 9 are provided for each block, and each register holds a block no-flock number following the block as viewed from the address of the storage device. After reading the last instruction word of the block here.

If we call the movement of the accessed block to another block in order to read the instruction word following the above instruction word from the address of the storage device, registers 8 and 9 are set in blocks corresponding to the blocks. This is the block image destination block number register that holds the block number of the image destination. 10 is a selector, register 27.2
8 is a V bit indicating the validity of the contents of registers 8 and 9, respectively.

The instruction counter 12 is a register in which the upper 23 bits of the address on the storage device of the instruction word being read from the instruction buffer 3 and the upper 23 bits of the initial value (hereinafter referred to as initial IC) of an instruction counter (not shown) are set. It is. The value of this instruction counter 12 is input to controllers 16 and 17. ll) Start address register 14
．． 15, and the block number containing the command word at the end of the block image is determined by the matching output.

FIG. 2 (7D (a) Id, read address counter of instruction buffer 3 (hereinafter referred to as "instruction pointer") 7
FIG. 2 is a diagram illustrating the format of , and is shown in the form of a register. Bits 0 and 1 are block numbers, bits 2 to 5 are word numbers within the block, and bits 6 to 8 are word white numbers, respectively. Bits 2-8 are normally incremented by +1.

FIG. 2(b) is a diagram showing the format of the write address counter 1 of the instruction buffer 3, and is the same as FIG. 2(a).

Bits 0 and 1 are block numbers, and bits 2 to 5 are word numbers. Bits 2-5 may be incremented by +1.

The load destination block number register 19 is a register indicating the block number on the instruction buffer 3 which receives 512 bytes of response information from the cache memory at the time of the aforementioned load, and is incremented by 1 in response to the request signal. 21 is a selector.

The control circuit 22 is a control circuit that generates signals for reading and writing the buffer 3, strobes the registers, and switches input/output of the registers.

Next, the operation of the present instruction fetching device will be explained with reference to FIGS. 1 and 2. When the control circuit 22 receives an instruction to start fetching an instruction, it sets the upper 23 bits of the initial IC in the instruction counter 12 via the selector 11, and sets the lower 7 bits of the initial IC.
The bit is set in the in-block word number part and the word white talk number part of the instruction pointer 7.

At the time when the start instruction is received, no valid instruction word is loaded into the instruction buffer 3, and the start address register 1
Validity display bits (V pits) 27 and 28 provided corresponding to numbers 4 to 15 are all in a reset state. Therefore, there is no hit among blocks O to 3, and the instruction counter 12
A block load request is sent to the cache memory using the value of as the access address.

The value of the load destination block number register 19 is selected as the load destination block number. The register 19 is incremented when the first response is returned from the cache memory at the time of loading, and holds the block number of the ninth load destination.

Here, it is assumed that block O is selected first.

When the control circuit 22 receives a response signal from the cache memory, it receives the 32 bytes x 1 sent through the data line 23.
Write six times of information to each word of block 0 of instruction buffer 3. The information is sent 16 times starting with 32 bytes including request address information.

When the control circuit 22 also receives the response signal, the command counter 1
A value of 2 is set in the start address register 14, and at the same time, the V bit corresponding to this register is set. As a result, the output of the comparator 16 becomes II I TJ, and the encoder 18 outputs the bit signal 25 and block number signal 20.
is output. Here, the control circuit 22 sets the block number signal 20 to the block number portion of the instruction pointer 7 via the selector 6, and thereafter sequentially increments the lower seven bits of the instruction pointer 7. As a result, predetermined instruction words are sequentially read into the instruction register 5.

Here, a request is issued to the cache memory, and the block destination block number registers 8 to 9 are updated using the time it takes for response information to be returned. The instruction counter 12 now contains the upper 2 addresses of the block into which the response information from the cache memory is loaded, that is, block 0.
3 bits are set. Therefore, instruction counter 12
By adding 1 to 1 in the +1 adder 13, the address of the block ahead of block 0 is obtained. +1 value of instruction counter 12 and start address register 14.15
If a matching output is obtained, set the block number of the block destination in the block destination block number register 8゜9 corresponding to block O, and check the validity of the values of these registers 8 and 9. Set the V pit shown. If no matching output is obtained, the V bits of registers 8 and 9 corresponding to block O are reset, and a block whose block image destination is block O is searched for. First, the high-order 23 bits of the address of block 0 are decremented by 1 by the adder 26 to find the start address (high-order 23 bits of the address) of the block whose block destination should be in block 0. Set to . Next, the value of the instruction counter 12 is transferred to the start address register 14.
．． Compare the values of 15. If a matching output is obtained, the value of register 19, that is, the block number of block O, is set in registers 8 and 9 corresponding to the block indicated by block number signal 20, and the corresponding V bit is set. If no matching output is obtained, block 0 is not continuous with any other block on the instruction buffer 3.

After the block destination block number registers 8 and 90 have been updated, the upper 23 bits of the address of the block to be loaded, that is, block 0, are set again in the instruction counter 12. The block indicated by the load destination block number register 19 is the block to be replaced when the first request signal is issued. Therefore, the block destination block number registers 8 and 9, which indicate the same block as the load destination block signal and Zosta 19, correspond to bits 27 and 28 because the contents are not guaranteed when the next request signal is issued.
must be reset frequently.

FIG. 3 shows the details of the control circuit of V-Pi) 27 and 28 and its surroundings. Compare the load destination block number register 19 and the block destination block number registers 8 and 9 that have the V bit set, and if there is a matching register 8 and 9, the corresponding V bit will be set at the timing when the request signal is issued. 27. Reset 28. 29 and 30
is a controller.

When the lower 7 bits of the instruction pointer 7 become all "1", that is, when the address of the last instruction word of the block is set, the register 8 corresponding to the block being read is
, 9 are valid, the values of registers 8 and 9 are set in the block number field of the read address counter 7, and the block crossing is performed without a hitch, and the instruction word is successively read from the block ahead of the block. . If the values in registers 8 and 9 are not valid, a request is issued to the cache memory when a block is moved.

〔Effect of the invention〕

As described above, the present invention has the effect of completely improving the processing speed of an information processing apparatus including the instruction fetching device by fetching the instruction word at the end of the block picture faster than the instruction buffer and supplying it to the execution stage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire instruction fetching device according to the present invention, FIG. 2 is a diagram showing the format of the instruction pointer 7 and the write address register 1 shown in FIG. 1, and FIG. FIG. 6 is a diagram showing details of the control circuit for bits 28 and 29; Explanation of symbols: 1 is write address counter, 2 is write data register, 3 is instruction buffer, 4 is separator, 14 to 1
5 is a start address register, 16 to 17 are: + encoder, 18 is an encoder, 19 is a load destination block number register, 21 is a selector, 22 is a control circuit, 26 is a -1 adder, 27 and 28 are V bits. Each one is having a hailstorm.

Claims (1)

[Claims] 1. An instruction buffer that holds instruction words read from the storage device in blocks, and an address that holds the address of the instruction word held in the block group corresponding to one or several blocks on the instruction buffer. The instruction counter includes a holding means, an instruction counter that holds the upper bits of the address of the instruction word being read from the instruction buffer, and an instruction pointer indicating a block number and an address within the block of the instruction word being read from the instruction buffer. The instruction fetching device includes block number holding means for holding a number of a block following the block from the address of the storage device corresponding to each block on the instruction buffer, and a block in the block number holding means. Indicating means for indicating whether or not a block corresponding to the number exists in the instruction buffer;
It is detected from the instruction pointer that the instruction word read from the instruction buffer is the last instruction word of the block, and a block corresponding to the block number in the block number holding means of the block exists in the instruction buffer. In the first case where the indicating means indicates that the value is put into the instruction pointer, and the instruction pointer indicates that the instruction word read from the instruction buffer is the last instruction word of the block. In the second case where the indicating means indicates that the block corresponding to the block number in the block number holding means of the block detected by the block number holding means does not exist in the instruction buffer, A request is issued to the storage means that stores the block corresponding to the block number of , and while the response information is returned, the value of the instruction counter or the value obtained by adding or subtracting the value of the instruction counter in binary form and the address are held. and a means for comparing the value of the block number holding means, whereby in the first case, reading of the command word is continued, and in the second case, the value of the block number holding means is updated. instruction fetching device.