JPH04125747A - Cache memory controller - Google Patents

Abstract

PURPOSE:To cope with the delay of the actual information read time to the shortest information read time by discriminating whether read information has error or not. CONSTITUTION:Read information is supplied to an error discriminating part 25, and it is discriminated whether this information has error or not. If error is detected, a microprocessor 22 is switched to the reread mode. An access control part 24 instructs a wait control part 26 to add a wait cycle corresponding to one system clock (1CK). Thereafter, the control is returned to a step S1, and the same information is read again. In this case, information is surely read out because the wait cycle is added. Thus, information is surely read out without degrading the system performance.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a cache memory control device, a cache memory control device is provided that can cope with a delay in real information read time relative to the shortest information successive time without degrading system performance. The purpose is to read information from a cache memory, and the information reading means is capable of setting a rereading mode in which the same information is read continuously, and the information read by this information reading means contains an error. error determining means for determining whether or not;
When the error determining means determines that there is an error, the rereading mode setting means sets the information reading means to the rereading mode, and the error determining means determines that there is an error. and standby cycle adding means for adding a standby cycle to the information reading cycle of the information reading means when the information reading means is read out.

[Industrial application field] The present invention relates to a cache memory control device.

In recent years, in computer systems, with the demand for faster processing, arithmetic processing units and main memories are becoming faster.

However, the operating speed of the main memory is still considerably slower than the operating speed of arithmetic processing, so no matter how fast the arithmetic processing device is made, this operating speed cannot be fully utilized.

Therefore, cache memory is often used in computer systems.

In other words, by placing a cache memory that is faster than the main memory between the main memory and the processing unit, and reading information such as instructions and data from this cache memory, the processing unit and the main memory can be This compensates for the difference in operating speed.

By the way, when using a cache memory, it is preferable to read out information within the shortest information reading time of the arithmetic processing unit.

For this purpose, a high-speed cache memory can be used.

However, even if a system is constructed using high-speed cache memory that can theoretically meet the shortest information read time, due to the delay time of the peripheral hardware of the arithmetic processing unit, etc. In reality, there may be cases where it is not possible to make it in time.

In such a case, if left as is, the system will run out of control and reliability will drop significantly.

Therefore, when using a cache memory, it is necessary to consider the delay in actual information read time relative to the shortest information read time.

[Prior Art] Conventionally, in order to deal with the delay in the actual information read time relative to the shortest information read time, a rule has been applied to the shortest read cycle, regardless of whether the actual information read time is in time for the shortest information read time. A standby cycle was added to the

According to such a configuration, even if the actual information read time does not meet the shortest information read time, the information can be read reliably, and runaway of the system can be prevented.

However, in such a configuration, even if the actual information read time is within the shortest information read time, a standby cycle is added, so there is a problem that system performance deteriorates.

[Problem to be solved by the invention]

As described above, conventionally, in order to deal with the delay in the actual information read time relative to the shortest information read time, a standby cycle has been regularly implemented, regardless of whether the actual information read time is in time for the shortest information read time. However, there was a problem in that system performance deteriorated.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a cache memory control device that can cope with a delay in actual information read time relative to the shortest information read time without substantially reducing system performance.

[Means to solve the problem]

FIG. 1 is a block diagram showing the basic configuration of the present invention.

In the figure, 11 is information reading means having a rereading function. The information read from the cache memory 12 by the information reading means 11 is supplied to the error determining means 13, and it is determined whether or not there is an error. When a result of this determination is that there is an error, the rereading mode setting means 14 sets the rereading mode of the information reading means 11. Further, the standby cycle adding means 15 adds a standby cycle to the read cycle of the information reading means 11.

[Operation] If the actual information read time does not meet the shortest information read time, there is a very high possibility that an error will occur in the read information.

Therefore, as described above, according to the configuration for determining whether or not there is an error in the read information, it is possible to determine whether the actual information read time is within the shortest information read time.

Further, in the present invention, when it is determined that an error has occurred in the read information, a standby cycle is added and re-reading is executed, so that the information can be reliably read.

However, in such a configuration, additional time is required for rereading, but this rereading only needs to be performed when an error occurs, so there is almost no deterioration in system performance.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.

In the figure, 21 is a main memory.

22 is a microprocessor for reading information from this main memory 21.

A cache memory 23 compensates for the speed difference between the main memory 21 and the microprocessor 22 by temporarily holding information stored in the main memory 21.

Reference numeral 24 denotes an access control unit that performs replacement processing for transferring information in the main memory 21 to the cache memory 23.

Reference numeral 25 denotes an error determination unit that determines whether or not there is an error in the information read from the cache memory 23. The error determination unit 25 determines errors using, for example, an error correction code.

26 is a standby control unit that performs standby control of the read cycle of the microprocessor 722. This standby control section 26 is driven by the access control section 24 described above.

The microprocessor 22 has a rereading function,
When the error determining section 25 obtains a determination result that there is an error in the read information, a transition is made to the re-reading mode.

The cache memory 23 includes an information section 231 and a tag section 2.
Consists of 32.

The information section 231 stores information transferred from the main memory 21 under the control of the access control section 24. Tag part 2
32 has a dictionary indicating the transfer source address of the main memory 21 in this case. Then, based on this dictionary and the read address signal of the main memory 21 supplied from the microprocessor 22, it is determined whether or not the information section 231 contains the target information.

Note that the cache memory 23 is, for example, a set associative type memory.

That is, the read address signal output from the microprocessor 22 is composed of a set address, a block address, an intra-block address, etc. of the main memory 21.

The tag section 232 selects a cent on the dictionary based on the cent address of this read address signal. Next, compare the multiple block addresses stored in this cent with the block address included in the above address signal,
If there is a matching block address, a hint signal is output. On the other hand, if there is no matching block address, a miss hint signal is output.

When the hit signal is obtained from the tag section 232, the information section 231 selects a set on the storage area based on the set address of the read address signal. Next, a target block is selected from among the plurality of blocks stored in this set based on the hit signal. Finally, target information is read from this block based on the address within the block.

When a miss hint signal is obtained from the tag unit 232, the access control unit 24 transfers the information of the block selected by the read address signal output from the microprocessor 22 to the information unit 231, and address is written in the dictionary of the tag section 232. Along with this, the access control unit 24 causes the standby control unit 26 to
Instructs standby control for a predetermined system clock (nCK). As a result, a standby cycle corresponding to a predetermined system clock (nCK) is added to the shortest read cycle of the microprocessor 22. As a result, microprocessor 2
2 enables the access control unit 24 to take in information read from the main memory 21.

The access control unit 24 also includes a microprocessor 22
When it shifts to the reread mode, it instructs the standby control section 26 to perform standby control for one system clock (ICK). As a result, the standby control unit 26 controls the micropro sensor 22.
One system clock (ICK) is required for the shortest read cycle of
) minutes of standby cycles are added. As a result, in re-read mode, 1 system chroma and 7
Information is read in a cycle that is as long as (ICK).

In the above configuration, the operation will be explained.

FIG. 3 is a flowchart showing the information read operation.

In this information read operation, first, a read address signal of the main memory 21 is supplied from the microprocessor 22 to the information section 231 and tag section 232 of the cache memory 23 (step 1).

As a result, the tag unit 232 determines whether or not the information of the block selected by the read address signal is stored in the information unit 231 (step 2).

If the information of the target block is stored in the information section 231, a hit signal is output from the tag section 232 (step S3).

As a result, the information selected by the read address signal is read from the information section 231 (step S4).

This read information is supplied to the error determining section 25, and it is determined whether or not there is an error (step S5).

If there is no error, the read information is taken in by the microprocessor sensor 22 (step S6).

On the other hand, if there is an error, the microprocessor 22 shifts to reread mode (step S7).

As a result, the access control unit 24 instructs the standby control unit 26 to add a standby cycle for one system clock (ICK) (step S8).

After this, the process returns to step S1, and the same information is read out again. In this case, since a standby cycle is added, the information can be reliably read.

Note that when a determination result of a miss is obtained in step S2, a miss hint signal is output from the tag section 232 (step S9).

Thereby, the access control unit 24 executes replacement processing (step 510).

Thereafter, the access control unit 24 instructs the standby control unit 26 to add a standby cycle for a predetermined system clock (nCK).

Thereby, the microprocessor 22 becomes able to take in the information read from the main memory 21 through the replacement process (step S6).

FIG. 4 is a timing chart showing transition to reread mode.

In the figure, (a) shows the system clock CK.

Here, T1 indicates the shortest read cycle, and T2 indicates the read cycle during re-reading.

(b) shows a read address signal output from the microprocessor 22. The figure shows a case where this read address signal is output during the high level period of the system clock CKO.

(c) shows the output timing of the hint signal output from the tag unit 232. Here, the hit signal is output during the low level period. Therefore, in the illustrated example, the determination as to whether there is information is made during the high level period of the system clock CK2.

(d) shows read information from the cache memory 23.

(e) shows the error determination signal of the error determination section 25. This error judgment signal becomes low level if there is no error,
If there is an error, the level will be high.

Therefore, in the illustrated example, the determination as to whether or not there is an error is made at the rising timing of the processor clock CK4. Note that the microprocessor 22 checks the error determination signal at the falling timing of the system clock CK4.

In the timing chart described above, the information read timing varies around the rising timing (error determination timing) of the system clock CK4. Therefore, there may be cases where the information read timing is not in time for the determination timing of the error determining section 25. When such a case occurs, the error determination signal becomes high level. Thereby, the microprocessor sensor 22 shifts to the re-read mode at the stage where the shortest read cycle Tl ends. In this reread mode, a standby cycle (system clock CKW) is added to the shortest read cycle T1. As a result, information is available at the rising timing (error determination timing) of the system clock CK4.

Therefore, this time, the error determination signal of the error determination section 25 does not become high level, and the microprocessor 22
Information is captured by

As described in detail above, this embodiment determines whether or not there is an error in the read information, and if there is an error, it is assumed that the actual information read time will not meet the shortest information read time, and the standby cycle is started. Since rereading is performed with the addition of , information can always be read out reliably.

In this case, although a new rereading period is required, this rereading only needs to be performed when an error occurs.
It has little effect on system performance.

Furthermore, in this embodiment, errors in the read information are determined using the error correction code that the information normally has, so the error determination function can be easily realized.

In addition, in the previous explanation, a case was explained in which an error correction code is used to determine whether or not an error has occurred. Alternatively, it may be determined whether or not.

It goes without saying that this invention can be modified in many other ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, the present invention determines whether or not the actual information read period is in time for the shortest information read time by determining whether or not there is an error in the read information. Since re-reading is performed with additional information, the information can be reliably read out with almost no deterioration in system performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of this invention. FIG. 2 is a block diagram showing the configuration of an embodiment of this invention. FIG. 3 is a flowchart diagram for explaining the operation of FIG. 2. , FIG. 4 is a timing chart for explaining the operation of FIG. 2. In the figure, 11... Information reading means, 12... Cache memory, 13... Error determining means, 14... Rereading mode setting means, 15... Standby cycle adding means. Calculation diagram of the present invention Diagram 1 Large scale diagram, 1 Hei flow diagram, Nogu diagram

Claims (2)

[Claims] (1) An information reading means (11) for reading information from a cache memory (12), which can set a rereading mode in which the same information is read out continuously; an error determining means (13) for determining whether or not there is an error in the information; and when the error determining means (13) determines that there is an error, re-reading the information reading means (11); rereading mode setting means (14) for setting the mode, and when the error determining means (13) determines that there is an error, a standby cycle is added to the information reading cycle of the information reading means (11). 1. A cache memory control device comprising: additional standby cycle adding means (15). (2) The error determining means (13) is configured to use an error correction code to determine whether or not there is an error in the information read out by the information reading means (11). The cache memory control device according to claim 1.