JPH02128254A - Cache control system - Google Patents

Cache control system

Info

Publication number
JPH02128254A
JPH02128254A JP63283327A JP28332788A JPH02128254A JP H02128254 A JPH02128254 A JP H02128254A JP 63283327 A JP63283327 A JP 63283327A JP 28332788 A JP28332788 A JP 28332788A JP H02128254 A JPH02128254 A JP H02128254A
Authority
JP
Japan
Prior art keywords
cache
memory
cache memory
error
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63283327A
Other languages
Japanese (ja)
Inventor
Takumi Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP63283327A priority Critical patent/JPH02128254A/en
Publication of JPH02128254A publication Critical patent/JPH02128254A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the degraded operation of a cache memory by changing the value of an address register when an error is generated, and using a physically different address part as the cache memory.
CONSTITUTION: A cache directory 1 consists of memory elements having several- folded capacity of desired words, a cache directory write circuit 2, a cache memory 3 consisting of the memory elements having the several-folded capacity of the desired words in the same way as the cache directory 1, and a cache memory write circuit 4 are included. When the error is detected, an error factor is discriminated, and by adding '1' to a D register 10 or an M register 11 corresponding to the cache directory 1 or the cache memory 3, in which the error is generated, the different address part is used when the next main memory accesses. Thus, the degraded operation of the cache memory can be prevented.
COPYRIGHT: (C)1990,JPO&Japio
JP63283327A 1988-11-08 1988-11-08 Cache control system Pending JPH02128254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63283327A JPH02128254A (en) 1988-11-08 1988-11-08 Cache control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63283327A JPH02128254A (en) 1988-11-08 1988-11-08 Cache control system

Publications (1)

Publication Number Publication Date
JPH02128254A true JPH02128254A (en) 1990-05-16

Family

ID=17664037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63283327A Pending JPH02128254A (en) 1988-11-08 1988-11-08 Cache control system

Country Status (1)

Country Link
JP (1) JPH02128254A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05165722A (en) * 1991-12-17 1993-07-02 Fujitsu Ltd Cache memory fault processing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58188399A (en) * 1982-04-27 1983-11-02 Nec Corp Data buffer memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58188399A (en) * 1982-04-27 1983-11-02 Nec Corp Data buffer memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05165722A (en) * 1991-12-17 1993-07-02 Fujitsu Ltd Cache memory fault processing system

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