JPS61214039A - Cache memory - Google Patents

Abstract

PURPOSE:To increase the stored data quantity with the same chip area and also to suppress the increase of overhead in a mishit mode by storing the new data in a memory part based on a flag showing an effective data memory state for each word of a data part. CONSTITUTION:The signals 12 and 18 are supplied to the associative memory 2 of a cache memory 1 in the form of the associative write input and a valid flag respectively. The hit/mishit states, i.e., the associative results are delivered to a signal 33, and a specific row that received a hit is delivered to a signal 40. Both RAM 3a and 3b are addressed by the signal 40, and signals 14, 34 and 11 are supplied in the form of the write inputs together with signals 31, 32, 35 and 36 supplied as the read outputs respectively. The memory 2 stores the 29-bit associative information and a 1-bit valid flag and compares the signal 12 with the associative information stored in each row when a signal 19 is kept off. Then the signal 33 is turned on when a coincident row exists and the valid flag of the row is equal to '1'. The value of the signal 12 and the value of the signal 18 are written to a designated row in the form of the associative information and a valid flag respectively when the signal 19 is kept on.

Description

Detailed Description of the Invention [Field of Application of the Invention] Relating to an on-chip cache memory suitable for computer processing [Background of the Invention] The Motorola MC68020 IEEE Micro, August 1984, pages 101-118 (The Motorola MC68020 IEEE
11icr.

August 1984 ppl, 0l-118)
The 32-bit microprocessor MC6 described in
8020 has cache memory on the chip.

In this cache memory, 32 bit data corresponds to one address storage section. Since the address storage section stores only address information and does not contribute much to the hit rate of the cache memory, the hit rate can be increased by increasing the capacity of the data storage section relative to the area of the entire cache memory.

Therefore, IBM's system 370 allocates 64 or 128 pits of data to one address. However, when trying to incorporate a similar method into a 32-bit microprocessor, the following problems arise. In the system 370, the width of the data bus connecting the CPU and memory is 64 or 128 bits, so in the case of a miss, the transfer from memory to cache memory is completed once, but the data bus width of a 32-bit microprocessor is 32 bits or more. Because of the following, transfers may occur twice or more than four times in the event of a mishit.

There is no problem if all the data transferred to the cache memory is used, but if new data is required without using the remaining data transferred due to execution of a branch instruction, etc., it becomes an overhead.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory that can store a large amount of data with the same chip area and that does not increase overhead when a miss occurs.

[Summary of the invention]

One ROW of the cache memory consists of a data section consisting of one address information of an associative section and a plurality of words with the external data bus width as a unit, and each word of the data section is checked to see if the data stored in that word is valid. By providing a flag (hereinafter referred to as a VALID flag) indicating whether or not the data is valid, the area of the associative part per word of stored data can be reduced.
In the event of a mishit, only the relevant data is written, thereby eliminating the need for increased overhead.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

The microprocessor with built-in cache memory 1 is
For example, it is assumed that memory data can be addressed in bytes and has a 32-bit address space, and that data is transferred to and from the memory using 32 bits as a basic unit (hereinafter referred to as a word). Furthermore, to simplify the explanation, it is assumed that the cache memory does not hold data but only holds instructions.

The cache memory 1 receives a signal 12 of the upper 29 bits (A31 to A3) and a signal 11 of the 30th bit (A2) as an instruction fetch address, and a signal 14 of 32 bits as an instruction input.

A 32-bit instruction read from cache memory 1 is output from signal 13, and information regarding hits/misses ζ is output from signals 15, 16 and 17, respectively. The cache memory 1 receives signals 18, 19, 20 as control signals.
, 21.22 are input.

The associative memory 2 receives a signal 12 as an associative fist writing input.
A signal 18 is input as a VALID flag, a hit/miss in the association result is output as a signal 33, and a signal 40 indicates which ROW was hit. The RAMs 3a, 3b are t-addressed by the signal 40, the write input is the signal 1434.11, and the read output is the signal 3132.35.36. The output corresponding to the input signal 14 of the RAM 3a is the signal 31. The output corresponding to the input signal 34 is the signal 35, the output corresponding to the input signal 14 of the RAM 36 is the signal 32, and the output corresponding to the input signal 411 is the signal 36. Signal 31 inputted to selector 4.
32 is selected by signal 11, and when it is 0, signal 31
When the value of is 1, the value of signal 32 is output as signal 13. The signal 19 is a write instruction signal for the content addressable memory 2, and the signal 20 is a signal specifying the ROW to be written. Signal 21 is R
This is a write instruction signal for AM3a, and signal 22 is a write instruction signal for RAM3.
This is a write instruction signal of b.

Associative memory 2 has 29 bits of associative information and 1 bit of VA.
The LID flag is stored, and when the signal 19 is off, the signal 12 is compared with the association information stored in each ROW, and if there is a matching ROW and the VALID flag of that ROW is 1, the signal 33 is activated. Turn on, that R of signal 40
Turn on the line corresponding to OW. When the signal 19 is on, the value of the signal 12 is sent as the VALID flag to the ROW specified by the signal 20 as associative information.
Write a value of 8 and turn on the line of signal 40 corresponding to that ROW. RAM3a and RAM3b hold instructions for even word addresses and odd word addresses, respectively. In addition to this, the cache memory 1 includes an inverter 5.
e, AND gates 7, 8, 9, and OR gate 10.

The status of each ROW of associative memory 2 and RAM 3a, 3b is 4.
Take control of two states. As shown in FIG. 2, in each of these states, the VALID flag of the associative memory 2 is O
A state in which no valid C instruction is stored in W, ■ A state in which a valid instruction is stored only on the even word side ■, A state in which a valid instruction is stored only in the odd word side ■, A state in which both even and odd numbers are stored Both are in a state (■) in which valid commands are stored.

FIG. 3 shows an example of a cache memory write control circuit of a microprocessor incorporating the cache memory 1.

The write control circuit includes inverters 101, 102 . OR gate 103, 104゜105, AND gate 106
, 107, and 108, and receives the write signal 50, address (A2) signal 11, output signal 15 and signal 18 from the cache memory 1, and outputs control signals 19, 21, and 22 for the cache memory 1.

The operation of cache memory 1 is described below.
) (clearing the cache memory), reading, and writing will be explained in this order.

PURGE is to set all the values of the VALID flags stored in the associative memory to O. First set signal 18 to 0
Then, the write signal 50 is turned on so that the signal 20 points to the first ROW. Thereafter, the signal 20 is changed to point to the next ROW and this process is repeated sequentially. When the signal 18 is set to 0 and the write signal 50 is turned on, the input terminal 102 of the write control circuit of FIG. OR gate 105, AND
The action of gate 108 turns on signal 19. When the signal 19 is turned on, writing to the content addressable memory 2 is performed, but since the signal 18 is 0, the VALID flag of the corresponding ROW is set to 0. Therefore, V of all ROWs of content addressable memory 2
The ALID flag is set to O and PURGE is completed.

Next, the read operation will be explained. When reading is to be performed, the write signal 50 is turned off and the address of the read command is input from the signals 11 and 12. Since the write signal 50 is off, the AND gate 10 of the write control circuit
Associative memo by 6,107,108! J2, RAM3
Signals 19, 21 and 22 instructing writing to a and 3b are also turned off. Since the signal 19 is off, the content addressable memory 2 performs association using the signal 12, and the results are the signals 33 and 40.
is output to. If the address is not stored, the signal 33 is turned off, and the AND gate 37, 38 and the OR gate 10 turn off the signal 16, indicating that the corresponding instruction is not held in the cache memory 1. Be notified.

When the instruction address is an odd word address and the state is ■, the signal 11 is 1. Since the signal 36 is 0, the inverter is A.
The functions of the ND gate 7, the AND gate 8, and the OR gate 10 turn off the signal 16 to notify that the command is not held.

Instruction address is odd word address, status is ■ or ■
In the case of , the signal 11 is 1 and the signal 36 is 1, so the AND game) 8, the signal 16 is turned on by the action of the OR gate 10. Further, the value of the signal 32 is outputted to the signal 13 via the selector 4.

Next, the write operation will be explained. A write operation is performed when the instruction to be read is not stored at all, or when the address is stored in the associative memory 2 but not in the RAM 3a or RAM 3b, as in state ■ or ■ in Figure 2. It will be held in To write to the cache memory, set signal 18 to 1 and set the address of the instruction to write to signal 1.
This is done by turning on the write signal 50 with a write command given to the signal 14 and the write command to the signals 1 and 12.

Only when the address is stored, the signal 33 is turned on. Also, since the signals 21 and 22 are off, the contents of the ROW indicated by the (AM3a and RAM3b (7) signal 40 are read out to the signals 31, 32, 35, and 36. is an even word address or an odd word address,
In addition, the states of RAM3a and RAM3b are as shown in Figure 2.
■.

■It depends on the state of either.

The instruction address is an even word address and the status is ■ or ■
In this case, since the signal 11 is O1 and the signal 35 is 1, the inverter 6 and the AND gate 7 turn on the signal 16 due to the action of the OR gate 10, notifying that the corresponding command is held, and the value of the signal 31 becomes It is output as a signal 13 via the selector 4.

If the instruction address is an even word address and the state is ■, the signal 11 is O2 and the signal 35 is O, so the inverter 6,
The AND gate 7, the AND gate 8 and the OR gate 10 turn off the signal 16 and notify that the command is not held.

If the instruction to be read is not stored at all, the signal 33 of the associative memory 2 is turned off, and the output signal 15 of the inverter 5 is turned on. Since the write signal 50 is turned on and the signal 15 is turned on in the write control circuit, Of gates 103, 104, 105 AND gates 106, 107 .
Due to the action of signal 108, signals 19, 21, and 22 are all turned on. When signal 19 turns on, signal 2 of associative memory 2
The values of signals 12 and 18 are written to the ROW designated by 0. If the address of the instruction to write is an even word address, the signal 11 is 0 and the output signal 34 of the inverter 6 is 1, so the instruction of the signal 14 is written to the RAN3al, the VALID information is set to 1, and the RAM 3b is set to 1. Although the command of signal 14 is written, the VALID information is set to O, resulting in the state 2 in FIG. 2. When the address of the write instruction is an odd word address, the signal 11 is 1 and the output signal 34 of the inverter 6 is O, so that the state 2 is reversed to the above.

When writing a command in state ■, that is, when the signal 11 is 1 at an odd word address, the signal 33 is turned on and the output signal 15 of the inverter 5 is turned off. As a result, signal 22 is turned on, but signal 19 and signal 21 remain off. Since signal 22 is turned on, RAM3
The command of signal 14 is written to b, and the VALID information is 1.
be made into As a result, the state of the cache memory 1 becomes ■.

When writing a command in state (2), that is, when the signal 11 is O at an odd word address, the signal 21 among the outputs of the write control circuit is turned on, and the signals 19 and 22 are turned off. Since signal 21 is turned on, signal 14 is stored in RAM3a.
This command is written and the VALID information becomes 1t. Therefore, the state of the cache compilation memory 1 becomes ■.

The input of the AND gate 9 is the signal 17, which is the signal 33 and the signal 36.
Therefore, regardless of the value of the instruction switch address, it indicates whether the odd word address side has been hit or not, so it can be determined whether the next instruction is in character memory 1 when reading the even word address. When the next instruction is in the cache memory, the next instruction has been read out from the RAM 3b, so by setting the address signal 11 to 1 and switching the selector 4, the next instruction is output as the signal 131.

According to this embodiment, when reading the next instruction after an even word address t, if the relevant instruction is in the cache memory, it can be read immediately, and even if the relevant instruction is not present, it can be determined without performing a read operation. This has the effect of shortening the average instruction fetch time.

In this embodiment, the number of words of the RAM corresponding to the associative memory is set to 2, but it is obvious that it can be easily expanded to a power of 2.

According to the present invention, it is possible to associate a plurality of word data sections with one word of the address association section, and it is not necessary to write valid data in all the corresponding data sections, so a large amount of data can be stored in a small area. Cache memory can be configured, and unnecessary memory access can be avoided without increasing the number of data lines between the processor and main memory. Effective in speeding up the processor.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a cache memory according to an embodiment of the present invention, FIG. 2 is an internal state diagram of the cache memory, and FIG. 3 is a write control circuit. 1...Cache memory, 2...Associative memory, 3a
13b... Random access memory, 4... Selector, 5.6... Inverter, 7, 8.9... AND
Gate, 10...OR gate. Agent: Patent Attorney Katsoo Ogawa Figure 7

Claims (1)

[Scope of Claims] 1. In a cache memory consisting of an associative part that stores address information and detects a match, and a data part that stores a plurality of words for one address information of the associative part, for each word of the data part. A cache memory characterized by providing a flag indicating whether or not valid data is stored in a corresponding word, and storing new data in the storage unit based on the flag. 2. The cache memory according to claim 1, wherein the association section has the flag separately from the data section. 3. The cache memory according to claim 1 or 2, wherein the flags corresponding to each word of the data section are paired, and writing can be performed independently between each word. 4. The cache memory according to any one of claims 1 to 3, wherein the flags of the data portion corresponding to the plurality of words can be read simultaneously. 5. The cache memory according to any one of claims 1 to 4, wherein the plurality of words correspond to consecutive addresses.