JPS63201852A - Access control system for cache memory - Google Patents

Access control system for cache memory

Info

Publication number
JPS63201852A
JPS63201852A JP62033495A JP3349587A JPS63201852A JP S63201852 A JPS63201852 A JP S63201852A JP 62033495 A JP62033495 A JP 62033495A JP 3349587 A JP3349587 A JP 3349587A JP S63201852 A JPS63201852 A JP S63201852A
Authority
JP
Japan
Prior art keywords
processor
clear
signal
cache
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62033495A
Other languages
Japanese (ja)
Inventor
Toshikatsu Mori
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP62033495A priority Critical patent/JPS63201852A/en
Priority claimed from CA000559045A external-priority patent/CA1299767C/en
Publication of JPS63201852A publication Critical patent/JPS63201852A/en
Priority claimed from CA000616197A external-priority patent/CA1313422C/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate the overhead of a processor by automatically switching the cache access of a processor during a valid bit clear to a bypass mode in a cache memory side.
CONSTITUTION: When a clear period state holding register 4 is set according to a reset signal or a clear command from the processor, a clear period signal 10 is outputted from the register 4. According to this signal 10, a clear address counter 2 and a write control circuit 3 start the respective operations thereof and the valid bit of a valid bit memory 1 is cleared. The signal 10 is inputted to a processor access converting circuit 5 and while the signal is outputted, all the cache accesses from the processor is converted to a cache bypass access. Accordingly, the processor can make access to the cache memory without sensing the clear period of the valid bit.
COPYRIGHT: (C)1988,JPO&Japio
JP62033495A 1987-02-18 1987-02-18 Access control system for cache memory Pending JPS63201852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62033495A JPS63201852A (en) 1987-02-18 1987-02-18 Access control system for cache memory

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
JP62033495A JPS63201852A (en) 1987-02-18 1987-02-18 Access control system for cache memory
CA000559045A CA1299767C (en) 1987-02-18 1988-02-16 Cache memory control system
EP95102266A EP0655689A3 (en) 1987-02-18 1988-02-17 Cache memory control system.
AU11791/88A AU602952B2 (en) 1987-02-18 1988-02-17 Cache memory control system
DE3855893T DE3855893T2 (en) 1987-02-18 1988-02-17 Cache control arrangement
SG1996001717A SG45227A1 (en) 1987-02-18 1988-02-17 Cache memory control system
EP88102288A EP0279421B1 (en) 1987-02-18 1988-02-17 Cache memory control system
AU58608/90A AU617948B2 (en) 1987-02-18 1990-07-02 Cache memory control system
CA000616197A CA1313422C (en) 1987-02-18 1991-10-15 Cache memory control system
HK98101188A HK1002241A1 (en) 1987-02-18 1998-02-16 Cache memory control system

Publications (1)

Publication Number Publication Date
JPS63201852A true JPS63201852A (en) 1988-08-19

Family

ID=12388132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62033495A Pending JPS63201852A (en) 1987-02-18 1987-02-18 Access control system for cache memory

Country Status (1)

Country Link
JP (1) JPS63201852A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237538A (en) * 1990-02-14 1991-10-23 Koufu Nippon Denki Kk Buffer storage device
JP2007048296A (en) * 2005-08-11 2007-02-22 Internatl Business Mach Corp <Ibm> Method, apparatus and system for invalidating multiple address cache entries

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03237538A (en) * 1990-02-14 1991-10-23 Koufu Nippon Denki Kk Buffer storage device
JP2007048296A (en) * 2005-08-11 2007-02-22 Internatl Business Mach Corp <Ibm> Method, apparatus and system for invalidating multiple address cache entries

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