JPS63201852A - Access control system for cache memory - Google Patents

Abstract

PURPOSE:To eliminate the overhead of a processor by automatically switching the cache access of a processor during a valid bit clear to a bypass mode in a cache memory side. CONSTITUTION:When a clear period state holding register 4 is set according to a reset signal or a clear command from the processor, a clear period signal 10 is outputted from the register 4. According to this signal 10, a clear address counter 2 and a write control circuit 3 start the respective operations thereof and the valid bit of a valid bit memory 1 is cleared. The signal 10 is inputted to a processor access converting circuit 5 and while the signal is outputted, all the cache accesses from the processor is converted to a cache bypass access. Accordingly, the processor can make access to the cache memory without sensing the clear period of the valid bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and particularly to an access control method for a cache memory.

[Conventional technology]

By installing a small capacity high-speed buffer memory between the processor and main memory, the effective main memory access time can be speeded up.

Computing Survey (Computing 5
survey) Volume 14, No. 3, 1982, 473-530
Generally well known as detailed on the page.

This method is usually called cache memory and is widely used in computer systems. This takes advantage of the property that there is locality in memory access of programs executed on computer systems. By fetching the contents of storage locations (usually called blocks) from main memory into cache memory, most memory accesses are performed by accessing the high-speed cache memory.

Access to slow main memory can be made unnecessary.

A cache memory is usually composed of a data memory, an address tag indicating the location of the data memory in main memory, and a valid bit indicating the validity of the data memory. These are implemented using random access memory (RAM), and their values are undefined immediately after power is turned on. Therefore, it is necessary to clear at least all valid bits before accessing the cache memory. On the other hand, in a computer system using a virtual memory method, it is necessary to clear the cache memory (valid pit) when switching virtual spaces.

Conventionally, when clearing cache memory, a control circuit for clearing was provided on the cache memory side.

The clearing circuit is activated by power-on or by a command from the processor, and use of the cache memory is started by notifying the processor of the completion of clearing.

[Problem that the invention seeks to solve]

In the conventional valid pit clear control method described above, the processor side detects the end of clearing and decides whether to access the cache or not.

This has the drawback of incurring processor overhead.

[Means for solving problems]

The valid pit clear control method of the present invention includes a valid bit clearing circuit that indicates the validity of data and address information held in a cache memory.

A clearing period state holding means indicating that the clearing period is in progress and a value of this clearing period state holding means are used to convert accesses from the processor into cache accesses or cache universal accesses. It has a processor access conversion circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, 1 is a valid pit memory, 2 is a clear address counter, and 3 is a write control circuit.

4 is a clear period state holding register (hereinafter simply referred to as a register) that holds the clear period state, and 5 is a power '7° four processor access conversion circuit also called a processor status decoder. Register 4 is set.

When the register 4 is set, the clear period signal 10 output from the register 4 enables the shift rear address counter 2 and the write control circuit 3, and each starts its operation. In addition, the output 11 of the address counter 2 is
Nonorid bit memory 1 via multiplexer 6
given as the address of The address counter 2 generates a predetermined address and generates a clear completion signal 12 when the clearing of the no-read bit is completed. Clear signal 1
2, the register 4 is reset and the address counter 2 and write control circuit 3 are disabled.

During the clear period, the signal 10, which is the output of the register, is input to the processor access conversion circuit 5 and output 10.
During the facdip, all cache accesses from the processor are converted to cache i4 accesses.

FIG. 2 shows an operation timing chart at the time of reset of the first embodiment.

The above is an explanation of the control unit A showing the access control method of the present invention shown in the lower half of FIG. Explain the operation.

Cache memory section 20 includes a directory and data memory. However, the write data base is omitted. The path controller 21 issues a main memory control signal to start main memory access when a cache access occurs and a miss (MISS) occurs or a cache bypass access occurs.

Data from the main memory is latched into the input latch 22 and output to the data bus on the processor side via the multiplexer 23. The output of the input latch 22 is also connected to the cache memory section 20, and updates cache data in the case of cache access. multiplexer 2
3 selects cache data in cases other than the above, and outputs the cache data as is to the processor side data bus when there is a cache hint.

〔Effect of the invention〕

As explained above, the present invention automatically switches the cache access of the processor during valid pit clearing to pinos9th mode on the cache memory side, and also automatically switches to cache access mode after valid bit clearing is completed. This has the effect that the processor can access the cache memory without being aware of the valid bit clearing period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
It is a figure which shows the timing chart in the Example of a figure. Explanation of symbols: 1 is valid pit memory, 2 is clear address counter, 3 is write control circuit. 4 is a register (clear period status holding register). 5 is a processor access conversion circuit, 6 is a multiplexer, 10 is a clear period signal, 11 is a clear address signal, 12 is a clear end signal, 13 is a write pulse, 20 is a cache memory section, 21 is a bus controller, 22 is an input latch , 231d-r rutizolexa, respectively.

Claims (1)

[Claims] 1. In a cache memory that speeds up the effective main memory access time by installing a small capacity high-speed buffer memory between the processor and the main memory, the data and address information held in the cache memory A clearing means for clearing a valid bit indicating the validity of the valid bit, a clearing period state holding means indicating that the valid bit is being cleared, and information of the clearing period state holding means is used to determine whether this information is valid during the valid bit clearing period. 1. A cache memory access control method, comprising processor access conversion means for converting an access from a processor into a cache bypass access.