JPH06348592A - Write buffer control method - Google Patents

Abstract

(57) [Summary] [Objective] The optimum write buffer operation mode is selected according to the operation mode of the internal cache memory of the CPU.
The write buffer operation mode is selected by the CPU and the bus master other than the CPU, and the optimum write buffer operation mode is selected for the bus master performing the write operation. This will speed up the write operation to the main memory of the system. A write buffer capable of switching between a write-through method and a copy-back method is provided between a CPU and a main storage device, and an operation mode of a cache memory with built-in CPU or a type of a bus master for writing is determined, and an operation of the write buffer is performed. The mode is controlled by the write buffer control circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to speeding up access to a main storage device of a small information processing device such as a personal computer or a workstation.

[0002]

2. Description of the Related Art Generally, a high-speed central processing unit (hereinafter referred to as CP
A write buffer, which is a speed-up means equivalent to a memory system, is employed in order to perform a write operation from abbreviated as U to a low-speed main memory at high speed. This write buffer generally has the following two control methods. In this specification, these two methods will be referred to as a write-through method and a write-back method, and the respective methods will be described below.

(1) Write Through System FIG. 4 is a diagram showing the configuration of the "write through system". In FIG. 4, reference numeral 72 denotes the CPU 101 to the write buffer 10.
0 is a signal indicating a write request, 73 is a signal indicating that the write buffer 100 has completed receiving the write address and data from the CPU 101, and 75 is a signal indicating a write request from the write buffer 100 to the main memory 108. Reference numeral 76 indicates that the main memory 108 is the write buffer 1
00 is a signal indicating that the reception of the write address and data from 00 is completed, and 104 is a control circuit.

Next, the operation will be described. CPU 101
When a write request is generated from the main memory 108 to the main memory 108, the write buffer 100 receives the write request signal 72, and writes the write address and the write data to the register 1 respectively.
Take in 4,15. Immediately after the capture is completed, the reception completion signal 73 is output to the CPU 101, and at the same time, the write request signal 75 to the main storage device 108 is output to start the write operation to the main storage device 108. CPU
101 When the reception completion signal 73 is received, the main memory 1
Since the next operation is started without waiting for the completion of writing to 08, the execution speed of the entire system is improved. On the other hand, when the write operation to the main storage device 108 continues, the write buffer 100 cannot move to the next process until the main storage device 108 outputs the data reception completion signal 76. Therefore, when the write operation from the CPU 101 continues, the write address and the write data cannot be taken into the register, so that the CPU 101 has to wait.

Regarding the write-through method described above,
For example, it is shown in "Write Buffer Method" of Japanese Patent Laid-Open No. 55-105881.

(2) Write Back Method Next, the write back method will be described. FIG. 5 is a diagram showing the configuration of the “write back method”. 7 in FIG.
2 is a signal indicating a write request from the CPU 101 to the write buffer 200, and 73 is a CP for the write buffer 200.
A signal indicating that the reception of the write address and data from U101 is completed, and 75 is the write buffer 200.
From the memory to the main memory 108, 7
Reference numeral 6 is a signal indicating that the main memory device 108 has completed receiving the write address and data from the write buffer 200, and 104 is a control circuit.

Next, the operation will be described. In FIG. 5, when the CPU 101 issues a write request to the main storage device 108, the write buffer 200 causes the write request signal 7
2 and receives the write address and the address stored in the register 24 in the previous write operation from the comparator 1
The comparison is made at 07, and if the addresses are the same, the contents of the register are replaced with the combination of the write address and data of this time. In this specification, the case of the same address is called a write buffer hit, and the case of not the same address is called a write buffer miss hit. In the case of a write buffer hit, only the contents of the registers 24 and 25 are rewritten and the writing to the main storage device 108 is omitted. Therefore, when writing to the same address in the main storage device 108 continues a plurality of times, the writing speed of the old data is omitted to improve the execution speed of the entire system. In the case of a write buffer mishit, a write request signal 7 to the main memory 108
5 is output and the write operation to the main memory 108 is started. On the other hand, when writing to the main memory 108 is in progress, CP
When the next write request is issued from U101, the write buffer 200 cannot fetch the write address and write data from the CPU 101 into the registers 24 and 25 until the main storage device 108 outputs the data reception completion signal 76. The CPU 101 has to wait.

This write-back method is disclosed, for example, in Japanese Patent Application Laid-Open No. 61-237145.

[0009]

As described above, the write-through method has a simple structure and can write a write address and data from the CPU at the same time and return a cycle completion signal to the CPU. Can immediately perform the following actions. If the writing from the write buffer to the main memory is completed before the write from the next CPU occurs, the CPU can complete the next write cycle at high speed. For example, when a low-speed bus master other than the CPU continuously writes, there is an interval between the normal write cycle and the next write cycle, and the write buffer writes data to the main storage device within this time. Since the operation is performed, the bus master hits the write buffer every time and can complete the writing at high speed. However, if the write cycles are continuously generated from the high-speed CPU, the CPU cannot complete the next write until the write from the write buffer to the main memory is completed. Alternatively, in a continuous write operation to the same address in the main memory, there arises a problem that the same address is repeatedly written. For example, when 1-byte data within the same 4-byte width address boundary is written four times in succession to a write buffer having a 4-byte (1 byte = 8 bits) data width, the main storage device The data is written four times from the write buffer to the same address. In the first write cycle, the CPU receives the cycle completion signal from the write buffer and can complete the cycle at high speed, but in the next three cycles, the CPU waits until the write operation from the write buffer to the main storage device is completed. Almost no effect.

On the other hand, the write-back method is advantageous in terms of performance, such as reducing the number of times of writing for successive write operations to the same address in the main memory. For example, the four write operations for the addresses within the same 4-byte boundary as described above can be combined into one write. CPU
Can complete the write cycle at high speed as long as the address hits the write buffer. But CP
If write buffer misses continue in the write cycle from U, first latch the address and CP
Compare with the write address of U, and if it is a next hit, write the currently latched data to the main memory,
After that, the address and data of the CPU are latched. Since this operation is repeated, compared to the case where there is no write buffer or the write-through method, it takes a longer time to complete the cycle at the time of a mishit and the penalty is large. Further, since it takes time to compare the latched address and the CPU address, there is a problem that it takes some time to receive the address and the data.

As described above, the write-through method speeds up the write cycle when there is time between the write cycle and the next write cycle, or when the number of times of writing from the CPU and the bus master to the same address is small. Can be completed, which is advantageous in terms of performance. On the other hand, the write-back method is advantageous in terms of performance when the number of times of continuous writing to the same address in the main storage device is large. This is particularly effective when writing data of consecutive 1-byte addresses in a write buffer having a data width of a plurality of bytes.

By the way, when the CPU writes data to the main memory, the way of generating a write cycle to the main memory differs depending on the structure of the CPU. For example, in a CPU having no built-in cache memory or a CPU having a built-in write-through cache memory, the write cycle of the CPU is directly written to the main storage device. Therefore, when the CPU writes data to consecutive addresses in byte units, writing also occurs in continuous addresses in byte units in the main storage device as it is. On the other hand, if a CPU with a built-in write-back type cache memory or a write-back type cache memory is added to the outside of the CPU, C
The PU write cycle is not directly written to the main memory. When the cache memory has a write-back method, the CPU writes only to the cache memory. Most write operations to the main memory are performed by the write-back cache. The write-back type cache memory normally performs a write operation in the minimum unit for managing data with a cache. Therefore, even when the CPU writes data to consecutive addresses in byte units, the write-back cache uses this as the minimum unit of data, for example, 4 bytes.
It is known to write data collectively in a byte width. For the write-through and write-back cache memory described above, the Information Processing Society of Japan (Information Processing v
ol21, No4, p332-340; 1980, 4
Month).

Further, since the bus masters other than the CPU usually do not have a cache memory, the write operation of the bus master is executed as it is to the main storage device as in the case of a CPU having no cache memory. Further EISA
When accessing a main memory from a bus master connected to an I / O bus such as a bus or an MCA bus, the I / O bus operates slower than the operation of the main memory, so that the bus master continuously performs write cycles to the main memory. Even if you go
In the main memory device, there may be a sufficient space between a write cycle and the next write cycle. For the I / O bus such as EISA bus and MCA bus, for example, 19
It is described in the Nikkei Bytes magazines P202 to P247 issued in January 1990.

An object of the present invention is to provide a write buffer control system which switches the operation mode of the write buffer according to the CPU configuration and the control system of the cache memory and selects the optimum operation mode.

Another object of the present invention is to switch the operation mode of the write buffer between a case where the CPU writes to the main memory and a case where the bus master writes in a system having a CPU and another bus master. It is to provide a write buffer control method for selecting an optimum operation mode.

[0016]

To achieve the above object, the write buffer is configured to operate in a plurality of operation modes, and means for switching the operation modes is provided. Further, there is provided a means for providing a signal for judging the operation mode of the cache memory of the CPU, monitoring this with a write buffer, and switching the operation mode of the write buffer.

Further, there is provided means for providing a signal for determining the CPU and the bus master other than the CPU, monitoring the write buffer, and switching the operation mode of the write buffer.

[0018]

When a write request is issued from the CPU, the write buffer switches the operation mode of the write buffer based on a signal for judging the operation mode of the internal cache memory of the CPU. Therefore, it is possible to always select the optimum write buffer operation mode according to the operation mode of the CPU and improve the system performance.

Further, in a system having a CPU and a bus master other than the CPU, when there is a write request to the main storage device, the CPU or the bus master is judged based on the signal for judging the bus master in the write buffer. Then, the write buffer operation mode is selected according to the result. Therefore, it is possible to select the optimum write buffer operation mode according to the operation of the bus master or the CPU that intends to perform the write operation.
The system performance can be improved.

[0020]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, the CPU 1 has a built-in cache memory 102, and the built-in cache 102 controls an operation mode by a cache control signal 109 output from a cache control unit 103. A write buffer 100 surrounded by a dotted line is located between the main storage device 108 and the CPU 101, and writing from the CPU 101 to the main storage device 108 is performed through the write buffer 100. The write buffer 100 operates in the write through mode or the write back mode, and the operation mode is switched by the mode switching signal 118 output from the write buffer control circuit 104.

The write operation will be described below with reference to the flow chart shown in FIG. After starting in process 601, the write request 110 is output from the CPU 101 in FIG. 1 to start the write cycle (process 602). The write buffer control circuit 104 determines the cache operation mode of the CPU by monitoring the cache mode signal 116 output by the cache control unit 103 (process 603). When the internal cache 102 is operating in the write through mode, the write buffer control circuit 104 sets the write buffer to the write back mode by using the mode switching signal 118 (process 604). After that, data latch signal 1
14. Using the address latch signal 117, the data on the data bus 113 and the address on the address bus 112 are latched (process 605). At the same time, cycle completion signal 11
1 is output, and the CPU write cycle ends. (Process 606) In process 603, the internal cache 10
2 is operating in the write back mode, the mode switching signal 118, the data latch signal 114 and the address latch signal 117 are used to write out the write data currently latched by the write buffer to the main memory 108. Perform processing. (Process 607). After that, the write buffer is set to the write-through mode using the mode switching signal 118, (process 608) the data and address are latched, and then the cycle end signal 111 is set.
Is output (process 609). After that, the memory write request 112 is output, the latch address of the address latch circuit is output to the memory address bus 120, the latch data of the data latch circuit is output to the memory data bus 119, and the write operation is performed (process 610). Main memory 1
After the writing is completed, 08 outputs the write completion signal 123 to complete the write cycle (process 611). In the processing described above, the basic operations in the write-through and write-back modes will be described with reference to FIGS.
Since it is the same as the conventional example described below, it is omitted here.

Next, FIG. 2 shows another embodiment of the present invention. In FIG. 2, the CPU 101, the write buffer 100, and the I / O bus bridge 208 are connected to the host bus 201. The bus master 202 is connected to the I / O bus bridge 208 through the I / O bus 203. Further, the write request signal 206 from the bus master 202 to the I / O bus bridge 208, the I / O bus bridge 208
The cycle end signal 207 is converted into the memory write request 204 and the memory write completion signal 205 by the I / O bus bridge 208, and the write buffer 1
Connected to 00.

The operation of this embodiment will be described below with reference to the flow chart shown in FIG. In the flowchart shown in FIG. 7, when the CPU 101 or the bus master 202 makes a write request to the main storage device 108 (process 701), in process 702, it is determined whether the CPU or the bus master other than the CPU is a bus master. CPU
Is outputting the write request 110, the CPU determines that it is the CPU and sets the write buffer to the write through mode in step 608. After that, the write address and write data on the host bus 201 are latched and the cycle completion signal 111 is output (process 609). After that, the latch data is written to the main storage device 108 (process 610) and the bus cycle ends (process 611). Further, the above processing 70
If the memory write request 204 is output from the I / O bus bridge 208 when determining the bus master in step 2, it is determined that the write is from the bus master 202 connected to the I / O bus 203, and the write is performed in step 604. The buffer is set to the write-back mode, the write data is latched (process 605), and the cycle completion signal 60
Output 6 and end. The other operations of the above-described embodiment are the same as those of the first embodiment described in FIG. 1, and therefore will be omitted here.

FIG. 3 is a diagram showing still another embodiment of the present invention. In FIG. 3, the host bus master 301 is connected to the host bus 201, and like the CPU 101, is connected to the write buffer 100 by the bus master write request 302 and the bus master cycle completion signal 303. The operation of the embodiment shown in FIG. 3 is almost the same as the operation of the embodiment shown in FIG. 2, and in the flowchart shown in FIG.
If the write request 110 from the CPU 101 is output, it is determined that the write is from the CPU 101 and the write buffer is set to the write through mode 60.
8 or less operation is performed. On the other hand, bus master write request 3
If 02 is output, it is determined that the writing is from the host bus master 302, and the operation of processing 604 and subsequent steps for setting the write buffer to the write back mode may be performed.

In the above-described embodiment, it is the CP that is going to perform the write operation to the main memory 108.
The essence of the present invention is to switch the operation mode of the write buffer depending on whether it is U or a bus master other than the CPU. Therefore, the bus master other than the CPU may be, for example, an adapter card connected to a standard expansion bus such as ISA, EISA, or MCA, or an FPU, a coprocessor, a display controller connected to the system DMA controller or the host bus. Further, it may be a high-speed local bus such as a VESA-VL bus, an expansion card connected to a PCI bus, a SCSI controller, or a display controller.

Similarly, the operation mode of the write buffer is not limited to the two modes of write-through and write-back, and the ON / OFF of the write buffer may be switched, or another operation mode may be provided. The operation may be changed, or two or more operation modes may be switched.

[0027]

According to the present invention, the optimum operation mode of the write buffer can always be selected according to the operation mode of the cache memory incorporated in the CPU, so that the system performance can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a write buffer system of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing still another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a “write-through method” which is a conventional technique.

FIG. 5 is a block diagram showing a configuration of a “copyback method” which is a conventional technique.

FIG. 6 is a flowchart illustrating the operation of the exemplary embodiment of the present invention.

FIG. 7 is a flowchart illustrating the operation of another embodiment of the present invention.

[Explanation of symbols]

100 ... Write buffer, 101 ... CPU, 102 ... C
PU built-in cache memory, 103 ... Built-in cache memory control unit, 104 ... Write buffer control circuit, 105
... address latch circuit, 106 ... data latch circuit, 1
07 ... Comparator, 108 ... Main memory device, 109 ... Cache control signal, 110 ... Write request, 111 ... Cycle completion signal, 112 ... Address bus, 113 ... Data bus, 114 ... Data latch signal, 116 ... Cache mode signal, 117 ... Address latch signal, 118 ... Write buffer mode signal, 119 ... Memory data bus, 1
20 ... Memory address bus, 201 ... Host bus, 20
2 ... Bus master, 203 ... I / O bus, 204 ... Memory write request, 205 ... Memory write completion signal, 20
8 ... I / O bus bridge, 301 ... Host bus master,
302 ... Bus master write request, 303 ... Bus master cycle completion signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Ichieda No. 1 Ikegami, Haruoka-cho, Owari-shi, Aichi Hitate Works Ltd. Office Systems Division

Claims (10)

[Claims] 1. An information processing system having at least a central processing unit CPU, a main storage device, and a write buffer between the CPU and the main storage device, wherein the write buffer has at least two or more operation modes. A write buffer control system comprising means for switching between two or more operation modes of the write buffer according to the operation of the CPU. 2. The operation mode of the write buffer according to claim 1, wherein when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, and then a write operation is performed from the write buffer to the main memory device. In the mode (this method is called a write-through method in this specification), when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, but immediately a write operation from the write buffer to the main memory device is performed. Alternatively, if writing from the CPU to the same address in the main memory continues, writing of old data is omitted (in this specification, this method is referred to as a write-back method). A write buffer control method characterized by having an operation mode. 3. The operation mode of the write buffer according to claim 1, wherein when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, and then a write operation is performed from the write buffer to the main memory device. In the mode (this method is called a write-through method in this specification), when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, but immediately a write operation from the write buffer to the main memory device is performed. Without the above, when writing from the CPU to the same address in the main memory continues, at least two types of operation modes (an operation mode in which writing of old data is omitted (this method is referred to as a write-back method)) are omitted. A write buffer control method characterized by having a mode. 4. The write buffer control method according to claim 3, wherein when the CPU has a built-in write-back cache or has an external write-back cache, a write-through write buffer operation mode is selected. A write buffer control method, wherein when the CPU does not have a cache or has a write-through cache, a write-back operation mode is selected. 5. The operation mode of the write buffer according to claim 1, has two operation modes, at least a disable mode for stopping the operation of the write buffer and an enable mode for permitting the operation of the write buffer. A write buffer control method characterized by having. 6. An information processing apparatus comprising at least a CPU, a main memory device, a bus master for accessing the main memory device other than the CPU, and a write buffer located between the CPU and the main memory device. The write buffer has at least two or more operation modes, and the write buffer is used when the CPU writes to the main memory and when a bus master other than the CPU writes to the main memory. A write buffer control system characterized by comprising means for switching the operation mode of 7. The operation mode of the write buffer according to claim 6, wherein when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, and then a write operation is performed from the write buffer to the main memory device. In the mode (this method is called a write-through method in this specification), when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, but immediately a write operation from the write buffer to the main memory device is performed. Alternatively, if writing from the CPU to the same address in the main memory continues, writing of old data is omitted (in this specification, this method is referred to as a write-back method). A write buffer control method characterized by having an operation mode. 8. The operation mode of the write buffer according to claim 6, wherein when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, and then a write operation is performed from the write buffer to the main memory device. In the mode (this method is called a write-through method in this specification), when a write address and data are received from the CPU, a cycle completion signal is returned to the CPU, but immediately a write operation from the write buffer to the main memory device is performed. Without the above, when writing from the CPU to the same address in the main memory continues, at least two types of operation modes (an operation mode in which writing of old data is omitted (this method is referred to as a write-back method)) are omitted. A write buffer control method characterized by having a mode. 9. The operation mode of the write buffer according to claim 6, has two operation modes, at least a disable mode for stopping the operation of the write buffer and an enable mode for permitting the operation of the write buffer. A write buffer control method characterized by having. 10. The write buffer control method according to claim 6, wherein when the CPU writes to the main memory measure, a write buffer operation mode of a write through method is selected, and a bus master other than the CPU is selected. A write buffer control method, wherein an operation mode of a write back method is selected when writing to the main storage device.