JPS62298850A - Buffer memory device - Google Patents

Abstract

PURPOSE:To reduce the frequency of copying-back operation by inhibiting a block stored in a buffer memory from being copied back if the block has an ineffective area. CONSTITUTION:There is the ineffective area between a head address (TA) and an end address (EA) and an address that a stack extends most at this point of time to reach to '18, 80, 6'. When access is attained with address information '30, 60, 2' in the state shown in a figure A, an address array 51 is referred to and the contents of an address 60 in the address array 51 are read out of columns 1 and 2 with a column address '60', thereby outputting '16' and '25' to coincidence circuits 52 and 53. Other inputs of those coincidence circuits 52 and 53 are a row address '30' of address information, so dissidence is detected. This dissidence information is inputted to a buffer control circuit 17 to decide which of blocks in the columns 1 and 2 is expelled.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a buffer memory device used in an information processing device.

[Prior art and its problems]

Buffer memory is a storage unit configured with high-speed storage elements to store part of information in main memory and enable high-speed access. Its operation is based on locality, which is a characteristic of dynamic memory access of a program in that the storage area of data and instructions to be accessed is concentrated within a very short time.

In other words, by taking advantage of this characteristic and storing information that is likely to be repeatedly accessed in buffer memory so that it can be accessed at high speed, effective access can be achieved compared to a storage device that consists only of main memory. A fast storage device can be realized.

Buffer memory management methods include a set associative method and a fully associative method. In either method, data is transferred between the main memory and the buffer memory in units of blocks consisting of multiple words.

Regarding the handling of write data from the processor, there are two main types of control methods between the buffer memory and the main memory: a write-through method and a copy-back method. The write-through method is a method in which data is always written to the main memory when it is written from the processor. On the other hand, in the copyback method, writing is performed to the buffer memory. Thereafter, the data write operation from the processor to the main memory is completed by transferring (copying back) the block written at the required time to the corresponding address in the main memory.

An example of the above-mentioned timing is when the data requested to be accessed by the processor does not exist in the buffer memory, so a new block area is created in the buffer to read the block requested to be accessed from the main memory into the buffer memory. There is a time when it is reserved in memory. That is, this is a case where a new block area is secured in the area of the block where writing has been performed.

To perform a copyback, the buffer memory is occupied for a period of time for a block read operation from the buffer memory, and the main memory is occupied for a period of time for an operation for writing to the main memory. Furthermore, it will exclusively occupy the data bus between the buffer memory and the main memory. Hence the buffer memory.

In order to increase the usage efficiency of main memory and data bus, it is necessary to reduce the frequency of copyback as much as possible.

Increasing the efficiency of these uses shortens the effective data access time from the processor, which is important for improving the processing efficiency of the processor.

Conventional copybacks do not sufficiently take into account how the processor's address space is used, resulting in an increased frequency of copybacks. - An example is the use of address space in implementing stacks.

Either a logical address or a physical address can be used as the address space.

FIG. 2 illustrates how the stack is used. FIG. 2(a) shows the state at the time when the stack has expanded. The starting address (indicated by the shaded area in the figure) of the stack
The area between TA) and the end address (EA) indicating the limit address allowed as a stack area is an invalid area, which is not used by the processor and is in an unused state. The stack is further extended, and the most extended state is shown in FIG. 2(b). At this time, Tut (indicates a large address).

Next, FIG. 2(C) shows a state in which the stack is shrunk. As a result, the area between TA in Figure 2(b) and TA in Figure 2(C) was an invalid area, and existed in the buffer memory in the state shown in Figure 2(b). Since there is a high possibility that
Even in the state shown in FIG. 2(C), there is a possibility that the area remains in the buffer memory.

In the conventional copyback method, blocks in the buffer memory included in this area are subject to copyback. However, this block is in the invalid area and does not need to be transferred to main memory. There is a problem in that by copying back this block, the utilization efficiency of the data bus between the buffer memory, main memory, and buffer memory main memory is reduced. (Objective of the Invention) The object of the present invention is to eliminate such conventional problems, and to avoid copying back by not copying back blocks that are in the buffer memory and do not need to be copied back to the main memory. Batza memory, which reduces the frequency of
An object of the present invention is to provide a buffer memory device capable of increasing the efficiency of using a data bus between a main memory and a buffer memory main memory, and increasing the processing efficiency of the entire information processing device.

[Means for solving problems]

The present invention provides a high-speed, small-capacity data array that divides and stores a portion of data stored in main memory into multiple blocks, and an address array that holds address information corresponding to each block within this data array. The method includes a memory having a memory having a data location, and refers to the address array based on a part of the address information for accessing the main memory to determine whether or not a data location to be accessed exists in the data array. In a buffer memory device that makes it accessible from the data array by specifying a position in the data array and updates data in main memory using a copy-back method, a starting address register for holding a starting address; an ending address register for holding an ending address of the invalid address space; means for generating an address corresponding to a block in the data array that needs to be copied back; an invalid block detector for detecting that the generated copy hack target address is in an invalid area between a block following the block indicated by the start address register and a block indicated by the end address register; The present invention is characterized in that it is characterized in that it is provided with an inverter control circuit that controls to omit copyback and store other data when the invalid block detector detects that the block currently in the data is an invalid area.

[Effect]

The present invention solves the problems of the prior art through the above-mentioned means.

According to the present invention, in order to prevent copy hacking into the main memory even if a block exists in the buffer memory and has been written by the processor, a function that can detect continuous invalid areas including this block is added and copy puncture control is performed. . When a block in the buffer memory is targeted for copyback, if it is included in the invalid area, the location in the buffer memory where that block exists is stored as information about other blocks without being copied back. I try to offer it for.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention. In the figure, IO is a main memory that stores data, 11 is a buffer memory that stores part of the data in the main memory 10 and is implemented using a set associative method to enable high-speed access, and 12 is a main memory. This is address information for accessing the memory 10 and buffer memo January 1. The address information 12 is divided into a row address, a column address, and a block address indicating a position within a block.

The buffer memo January 1 stores part of the data existing in the main memory 1o in two columns, and includes a high-speed, small-capacity data array 50 composed of multiple blocks, and a data array 50.
The address array 51 holds the information appearing in the row address field of the address information 12 corresponding to two columns (column 1 and column 2) and each block, and is accessed using the column address as an address, and the address information 12 matching circuits 52 and 53 that compare the row address information in the address array 51 read by the column address of the address information 12 with the row address of the address information 12 and detect whether or not they match for columns 1 and 2; If a match is found in any of the .53
A selection circuit 54 selects the output of the column in which a match is detected among the outputs of columns 1 and 2 in the data array 50 referenced by the column address of the address information 12 and sends the reference data. . In addition, in the case of write processing using address information 12, matching circuits 52 and 53
Writes to the column in the data array 50 on the side where a match has been detected.

Reference numeral 13 in FIG. 1 is means for generating the address of the block to be copied back, which is the target of copying among the outputs of columns 1 and 2 of the address array 51 referenced by the column address of the address information 12. A selection circuit 60 selects a column that holds information about the block in which the block is located;
Outputs the row address of the block to be copied back.

By combining this output and the column address information of address information 12 as a column address,
Generate the address of the block to be copied back. 14
1 is a start address register indicating the start of the invalid area of the address space, and 15 is an end address register indicating the end of the invalid area. Reference numeral 16 denotes an invalid block detector that detects that the address of the copyback pair i block, which is the output of the copyback address generation means 13, is in the following state.

Status: The value of the start address register <copyback target block address and copyback target block address ≤ value 17 of the end address register indicates that the output of the invalid block detector 16 detects that the copyback target block exists in an invalid area. Then, the buffer control circuit instructs to transfer data between the buffer memo 1 and the main memory 10 without copying back to the main memory 1o. The buffer control circuit 17 transfers the new block to the buffer memory I.
In addition to determining which block in the buffer memory January 1 is to be used for storage in the JII, it also outputs a control signal to the selection circuit 6o.

Next, the operation of this embodiment will be explained based on the usage status of the address space at a certain point in time of the operation shown in FIG. 3 and the state of the address array at that time.

The state of the address space is shown in FIG. 3(a). The stack area extends to the address position whose top address (TA) is "13.50°9". Address expressions are written in the order of row address, column address, and block address. The above TA is 13.50. 9 correspond to a row address, a column address, and a block address, respectively. The terminal address (EA) indicating the limit of the stack is “20
．． 10.15". Therefore, the area between this TA and EA is an invalid area. Also, the address reached by the longest stack up to this point is "1B, 80. 6
” is.

The state of the address array 51 is shown in FIG. 3(b).

"16.60.-" in Figure 3 (a) at address 60 in column l.
” has been registered, and its contents are row address “16”. 60 in column 2.
A block indicated by the address "25.60.-" is registered at the address.

In the state shown in Figure 3, @3G, 60. When accessing with the address information of ``2'', the address array 51 is referenced. With the column address ``60'', the contents of address 60 of the address array 51 are read from column 1 and column 2, and ``16'' and ``25'' match, respectively. It is output to the circuits 52 and 53. Since the other inputs of the matching circuits 52 and 53 are the row address "30" of the address information, a mismatch is detected. This mismatch information is input to the buffer control circuit 17, and the column l , determine which block in column 2 should be evicted.Here, 16.6 in column 1
0. I will explain the case where it is decided to get rid of the bloat.

Further, writing is being performed in the block "16.60.-", and the buffer control circuit 17 starts controlling copying back to the main memory 10. The selection circuit 6o selects the output "16" of column 1 according to instructions from the buffer control circuit 17. Furthermore, the address information at that time “30.60
．． 2" column address "60" is combined to obtain the address "16°60,-" of the block to be copied back. This address "16.60. -” is input to the invalid block detector 16, and the contents of the start address register 14 and end address register 15 are input at the same time.
Determine whether it is included in the invalid area. Here, the contents of the top address register 14 indicate the top of the stack “13
．． 50. 9”. Furthermore, the terminal address register 1
The content of 5 is the limit address of the stack “20.10
．． It is 15″.

As a result, the invalid block detector 16 detects that the copyback block address "16.60.-" is in the invalid area (
Between “13.50.9” and “20.10.15”)
Detects that it is included in. This result is output to the buffer control circuit 17, and the buffer control circuit performs control so that copyback is not performed when the block of "16.60°-" is ejected from the buffer memory 11.

〔Effect of the invention〕

According to the present invention, when a block stored in a buffer memory is included in an invalid area, as in the example of memory usage in a stack, this block is not targeted for copyback, thereby reducing the frequency of copyback. be able to. As a result, the time that the data bus between the buffer memory, main memory, and buffer memory main memory is dedicated for copyback processing can be reduced.
These can be used more efficiently. These improvements can improve the processing performance of the entire information processing device.

[Brief explanation of the drawing]

1st t! 1 is a block diagram showing one embodiment of the present invention;
The figure shows an example of address space usage in the stack, and FIG. 3 is a diagram showing the address space usage at a certain point in time and the state of the address array at that time. IO...Main memory 11...Buffer memory 12...Address information 13...Copyback address generation means 14...
- Start address register 15 that holds the address of one end of the invalid area in the address space...End address register 16 that holds the address of the other end of the invalid area...When the block to be copied back is in the invalid area Invalid block detector 17 that detects whether the block is included... Buffer control circuit that controls copyback etc. (a) Figure 2 (a) Figure 3

Claims (1)

[Claims] (1) A high-speed, small-capacity data array that stores part of the data stored in main memory divided into multiple blocks;
A buffer memory having an address array that holds address information corresponding to each block in the data array is provided, and the address array is referred to based on a part of the address information for accessing the main memory to locate the data to be accessed. determine whether or not exists in the data array, and if so, make it accessible from the data array by specifying the position in the data array;
In a buffer memory device that updates data in main memory using a copy-back method, there is a start address register that holds the start address of consecutive invalid address spaces, and an end address of the invalid address space. an end address register; means for generating an address corresponding to a block in the data array that requires copying; and a means for generating an address corresponding to a block in the data array that needs to be copied back; an invalid block detector that detects that the block is in an invalid area between the blocks indicated by the address register; and an invalid block detector that detects that the block to be copied back is in an invalid area between the blocks indicated by the address register; 1. A buffer memory device comprising: a buffer control circuit for controlling storage of other data while omitting a back buffer.