JPH04181343A - Cache memory system - Google Patents

Abstract

PURPOSE:To perform cache coincidence processing at a high speed by holding valid bits corresponding to the main storage addresses of a flash address array as a copy of an address array in a readable/writable storage means in the same machine cycle. CONSTITUTION:This system has the address array 16 wherein main storage addresses of data held on a cache memory 10 and valid bits indicating whether the data are effective are held corresponding to each other and the flash address array 13 which is referred to for the cache coincidence processing at the time of rewriting of a main storage device 4 by another processor and holds the main storage addresses in the address array 16. In this case, the system is provided with a storage means which holds valid bits corresponding to the main storage addresses held in the flash address array 13 and can be read and written in the same machine cycle. Consequently, even if requests for cache coincidence processing continue, the processing is performed without keeping following requests wait, so that the cache coincidence processing can be performed at a high speed.

Description

Description: TECHNICAL FIELD This invention relates to cache memory systems, and more particularly to the configuration of valid bits in a flash address array that is a copy of the address array that makes up the cache memory system.

Prior Art In a store-through type information processing device in which a plurality of processors each having a cache memory are provided, and the data in the main memory is rewritten at the same time as the data in the own cache is rewritten, one processor writes the data in the main memory. When rewritten, cache matching processing is performed to reflect this in the cache memories of other processors.

That is, the system control device sends the address of the data and a cache match processing request to all connected processors, and the processor that receives these addresses and cache match processing request caches the block data including the data indicated by the address. To determine whether the address of the data is present in the memory, search the flash address array that is a copy of the address array in which the address of the data registered in the memory is registered, and if the address is registered, - By erasing the valid bit on the address array indicated by that address, the data on the cache memory corresponding to that address is invalidated.

Conventionally, in a flash address array which is a copy of an address array, if the cache memory has one block of 64B (bytes) and a cache capacity of 64KB (kilobytes), it is necessary to hold IK addresses.

Therefore, since the flash address array is composed of highly integrated storage elements such as RAM (Random Access Memory), it is not possible to simultaneously execute a read operation and a write operation within the same machine cycle.

In such conventional cache memory systems, the flash address array cannot simultaneously execute a read operation and a write operation within the same machine cycle, so in the case of two consecutive cache matching requests, A read operation for a comparison check with the address sent from the system control device and a write operation of a valid bit for the result of the comparison check could not be performed simultaneously.

Therefore, it is necessary to perform the above two operations sequentially.
The disadvantage is that it takes two machine cycles to perform these two operations, and subsequent requests cannot be accepted during that time.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional methods as described above.Even when cache matching processing requests are consecutive, they can be processed without making the subsequent requests wait, and the cache matching processing can be processed without waiting. The purpose of the present invention is to provide a cache memory system that can be executed at high speed.

Composition of the Invention A cache memory system according to the present invention includes a cache memory that holds data stored in a main memory in units of blocks, and a valid address that indicates the main memory address of the data held in the cache memory and the valid state of the data. an address array that holds bits in correspondence with each other;
a flash address array that is referenced to perform cache matching processing when the main memory is rewritten by another processor and holds the main memory address held in the address array; The present invention is characterized in that a storage means is provided which holds the valid bit corresponding to the main memory address held in an address array and can be read and written in the same machine cycle.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a processor 1 has a cache memory 10 that performs data replacement in block units with a main memory 4, and when data is written to this cache memory 10, that is, stored, the data is stored in the main memory. A store-through method is adopted in which data is stored in the device 4 at the same time.

In the address array (AA) 16, block addresses existing on the cache memory 10 and valid bits indicating whether the address is valid or invalid are registered corresponding to each block address.

The flash address array (FAA) 13 and valid bit array (FAAV) 15 are copies of the block address and valid bit of the address array 16, respectively, and the block address of the memory where the store was stored in another processor 2 is stored in the cache in the own processor. memory 10
It is used to search for the existence of

This search is performed using the lower bits 112 of the address register (FARAR) 11 that stores the cache match request address 110 sent from the system control bag W3.

In other words, the read data 114 from the franchise address array] 3 read out by the lower bit 112 of the address register 11 and the upper bit 11 of the address register 11
1 using the comparator 17, and the comparison result is 1.17,
Flash address array] Read data 114 from 3
Address register 1 is read out at the same timing as
The AND gate 18 performs an AND with the read data 116 from the valid bit array 15 read out using the lower bit 112 of 1, and when the result of the operation is 11.8 or "1', the other processor 2 determines that there is a store. It is determined that the block address of the memory entered exists in the cache memory 1° within the own processor.

The calculation result 118 of the AND gate 18 is stored in the hit level register (FHR) 14, and the output 115 of this hit level register 4 becomes a write enable signal for the valid bit array 15 and address array 16.

Address register (AWAR) 1.2 is AND gate 1
The operation result of 8, 1.18, is stored in the hit level register] At the same timing as the address register 4, the lower bit 1.12 of 1 is stored, and this address register]
By rewriting the valid bits of the valid bit array 15 and the address array 16 designated by the address 113 from 2 to "0", the block designated by the above block address is invalidated.

At this time, at the same timing, valid bit array 15
is supplied with the lower bits 112 of the address register 11, and the lower bits], ! , 2 of the subsequent request is read.

Although not shown, the other processors 2 have the same configuration as the processor 1 and operate in the same way.

Here, when reading valid bits from a conventional flash address array, as shown in FIG. The storage capacity 4 of the storage area 6-4 of the storage element 6 is output to the read port 6d.

Note that the memory element 6 is provided with storage areas 6-1 to 6-n, each having a storage capacity of 1 to m. is stored.

In addition, when rewriting the valid bits of the flash address array, as shown in FIG. 4(b), the memory area 6-1 of the memory element 6 specified by the column address port
Writes the storage capacity l and sends “0” from the data port 6c.
Rewrite it.

As mentioned above, in conventional flash address arrays, the read and write operations for valid bits must be executed in separate machine cycles, and it is necessary to control the read and write operations so that they are executed sequentially. Therefore, the address register could only accept a cache match request address once every two machine cycles.

That is, as shown in FIG. 5, when cache match requests are made manually in succession, a read operation and a write operation according to the first cache match request address ■ and a read operation and write operation according to the next cache match request address ■ Each operation had to be executed in a separate machine cycle, and it was necessary to control the read and write operations of the valid bits of the flash address array to be executed sequentially. Only the percentage of times can match the request address ■,
I was unable to accept ■.

On the other hand, in this embodiment, as shown in FIG. 2, when the write enable terminal (WE) 5a is "1", the data is specified by the write column address port (WA) 5b, that is, by the first gear match request address. The memory content 1 of the memory area 5-1 of the memory element 5 is rewritten with "0" from the write data port 5d.

At this time, within the same machine cycle as that operation, the storage content 4 of the storage area 5-4 of the storage element 5 specified by the read column address port (RA) 5c, that is, the next cache match request address, is transferred to the read column address port (RA) 5c. 5e.

Note that the memory element 5 is provided with storage areas 5-1 to 5-n, each of which stores storage contents 1 to m.

Therefore, as shown in FIG. 3, when cache match requests are input successively, the write operation of the valid bit array 15 by the first cache match request address ■ and the write operation of the valid bit array 15 by the next cache match request address ■ 15 read operations can be performed within the same machine cycle, and cache matching requests can be executed consecutively.

In this way, by holding the valid bits corresponding to the block addresses held in the flash address array 13, which is a copy of the address array 16, in the valid bit array 15, which can be read and written in the same machine cycle, cache consistency is achieved. Even when processing requests are consecutive, they can be processed without making subsequent requests wait, and cache matching processing can be executed at high speed.

In one embodiment of the present invention, the write operation of the valid bit array 15 according to the first cache match request address (■) and the read operation of the valid bit array 15 according to the next cache match request address (■) are performed within the same clock cycle. However, the read operation and write operation of the valid bit array 15 according to the first cache match request address ■ and the read operation and write operation of the valid bit array 15 according to the next cache match request address ■ are performed separately and identically. It may be performed within a machine cycle, but is not limited to this.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, valid bits corresponding to main memory addresses of a flash address array, which is a copy of the address array, are held in a storage means that can be read and written in the same machine cycle. This has the effect that even if cache matching processing requests are consecutive, they can be processed without making the subsequent requests wait, and the cache matching processing can be executed at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the operation of the storage element of the valid bit array of FIG. 1, and FIG. 3 is a block diagram showing the operation of the embodiment of the invention. FIG. 4 is a timing chart showing the operation of a valid bit storage element in a conventional flash address array; FIG.
The figure is a timing chart showing the operation of the conventional example. Explanation of symbols of main parts 1.2...Processor 3...System control unit 4...Main storage device 10...Cache memory 11.12... Address register 13...Flash address array 14...
...Hit level register 15...Valid bit array 16...Address array

Claims (1)

[Claims] (1) A cache memory that holds data stored in the main memory in block units, and stores the main memory address of the data held in the cache memory in correspondence with a valid bit that indicates the valid state of the data. and a flash address array that holds the main memory addresses that are referenced to perform cache matching processing when the main memory is rewritten by another processor and that are held in the address array. A cache memory system comprising a storage means that holds the valid bit corresponding to the main memory address held in the flash address array and is readable and writable in the same machine cycle.