JPS63173146A - Cache memory control system - Google Patents

Abstract

PURPOSE:To obtain a system performance with a level higher than ever with the same quantity of hardware as that of a write through system, by rewriting a main memory device by adding a write buffer, and holding and processing the latest write request of a processor. CONSTITUTION:A cache memory (CM) control circuit 3, when no rewrite data exists in a CM2, set a signal Ext at an H. Thereby, a write control circuit 15 sets a signal Cenb at the H, and validates the buffer 14, and permits write on the memory device 5 through a system address of the main memory device 5 designated by the processor 1. When the data remains in the CM2, the content of an address register 12 is compared with the address of a present access at a comparator 13, and when they coincide, the circuit 15 sets a signal DS at the H, and fetches the data of the CM2 in a data register 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control system, and in particular improves the performance of a computer using a cache memory. Regarding improvement of the method.

[Prior Art] Conventionally, in order to maximize the performance of a high-performance processor, a cache memory 2 is often placed between a processor 1 and a main storage device 5, as shown in FIG.

The processor 1 can access the main storage device 5 via the system bus 4. In addition, cache memory 2 is
A high-speed memory that is controlled by a cache memory control circuit 3 that operates based on an address from the processor 1 and a read/write control signal (R/W), and holds a group of data that was last used in the main memory 5. be.

Therefore, if the data required by the processor 1 is in the cache memory 2, it can be retrieved directly at high speed without going through the system bus 3.
It is easily understood that the use of cache memory improves processing performance.

By the way, when a processor executes a write, the following two methods are known as methods for the cache memory to handle the write.

(1) Write/Throw One-way Cash Memory 11 Although accessed via the control circuit 3, the main memory 4 is always directly accessed without going through the cache memory and updated with new data. In other words, it is the same as if the cache memory does not exist when writing.

■Copy-back method Writing is performed to the cache memory 2, and when changing the data set stored in the cache memory, the data evicted from the cache memory is transferred to the main memory fl! 4
Write by copying to. In this case! Control is complex and costly.

[Problems to be Solved by the Invention] In systems using microprocessors, cost is important, so a write-through system that is generally easy to implement is often used.

However, in the conventional write-through method, all writes require access to the main memory 4, so that (1) when the ratio of write operations increases, the effectiveness of cache memory use decreases.

(1) Since writing one byte requires one bus cycle, with a 16-bit or 32-bit system bus, the system bus is used inefficiently and the overall processing performance decreases.

There is a drawback.

The purpose of the present invention is to eliminate such drawbacks, and to provide a cache memory control system that can achieve higher system processing performance with the same amount of hardware as the write-through type. be.

[Means for solving problems] One aspect of the present invention is to achieve such objects.

In a system in which a cache memory and a cache memory control circuit for controlling the cache memory are provided between a processor and a main storage device, a data register that holds data of the latest write operation.

an address register that holds an address in the latest write operation output from the processor; a comparator that compares the contents of the address register with a current write address given by the processor; the main storage device and the cache memory. a buffer that controls connection with a control circuit; a control signal necessary to control writing to the data register and the address register, and rewriting of the main memory, and an access cycle to the main memory; The present invention is characterized by comprising a write control circuit that generates a signal to notify the cache memory control circuit of completion.

[Operation] In the present invention, a write buffer consisting of an address register and a data register is added to a write-through type cache memory, and the write buffer holds the latest write request of the processor, and the latest write request of the processor is stored. A write request to an address is processed by rewriting the data in the write buffer. Then, by rewriting the main memory based on the contents of the write buffer at an appropriate time, the write operation is reflected in the main memory.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of main parts showing an embodiment of a cache memory control system according to the present invention.

In the figure, the portion within the broken line is a feature of the present invention. The cache memory 2 and the cache memory control circuit 3 constitute a known write-through type cache memory device.

Reference numeral 11 is a 3-state output data register that holds data of the latest write operation. 12 is an address register that holds the address in the latest write operation output from the processor 1;

A comparator 13 compares the contents of the address register 12 with the current write address (given by the processor), and sets the output signal Hit to true (HIGH) if the address is within the range stored in the data register 11.

Reference numeral 14 denotes a 3-state output buffer, which controls the connection between the system bus 4 and the cache memory control circuit 3 based on instructions from the write control circuit 15.

Reference numeral 15 denotes a write control circuit that generates control signals necessary to control writing to the data register 11 and address register 12, and rewriting of the main storage device 5, respectively. Furthermore, when the access cycle to the main memory device is completed, the cache memory control circuit 3 is notified of this by using the W ack signal.

16 is a 3-state output buffer. The output of the address register 12 is output to the system bus 13 via this buffer 16.

Write control circuit 15 from cache memory control circuit 3
The signal Ext given to is a signal that becomes true when there is no necessary data in the cache memory 2 and it is necessary to access the main storage device 5.

Further, the signal DS given from the write control circuit 15 to the data register 11 is a signal for instructing writing to the data register 11, and the signal AS given from the write control circuit 15 to the address register 12 is a signal for instructing writing to the address register 12. This is a signal that indicates.

The signal Cenb applied from the write control circuit 15 to the buffer 14 is a signal instructing to enable the output of the buffer 14, and the signal Cenb applied from the write control circuit 15 to the data register 11 and the buffer 16
nd is a signal indicating that the outputs of the data register 11 and buffer 16 are valid.

These signals, namely DS, AS+Cenb.

Wenb is output from the write control circuit 15.

The operation in such a configuration will be explained next with reference to the time charts of FIGS. 2 to 5.

(2) In the case of write mode In this case, the R/W signal from the processor 1 becomes LOW. Cache memory control circuit 3 first determines whether rewritten data exists in cache memory 2. If it does not exist, the signal Ex
Set t to HIGH.

This causes the write control circuit 15 to set the Cenb signal to HI.
GH, the buffer 14 is enabled, and writing to the main storage device 5 via the system bus 4 is enabled. Data output by the processor is written to an address in main memory specified by the processor.

If data remains in cache memory 2 (Ex
t signal goes LOW), the contents of the address register 12 and the address of the current access are compared by the comparator 13, and if they match (the output of the comparator 13 is
(becomes HIGH) The write control circuit 15 sets the DS signal to HIGH and takes in the data in the cache memory 2 into the data register 11. In this case, the main storage device 5 is not accessed. The same applies when the data register 11 and address register 12 are unused.

As a result of the comparison, if they do not match, as shown in FIG.
The main memory 5 is rewritten based on the contents of the data register 11 and address register 12 by setting the signal to LOW. After that, the W e n b signal is LOW, DS and A
Set the S signal to HI'G H and write the contents of the current write access to data register 11 and address register 1.
Store in 2.

(2) In the case of read mode If there is data to be read in the cache memory 2, it is fetched into the processor 1 in the same manner as before. The case where there is no data to read will be explained below. In this case, the R/W signal from the processor is HIGH as shown in Figure 5.
Then, the Ext signal of the cache memory control circuit 3 becomes HIGH. The write control circuit 15 thereby makes the Cenb signal HIGH, the Wenb signal, and OW.

As a result, desired data is read from the main memory device 5 via the buffer 14 and sent to the cache memory 2 or the processor 1. After that, the write control circuit 15
Set the nb signal to LOW, set the We'n b signal to HIGH,
Main memory 5 is rewritten based on the contents of data register 11 and address register 12.

In the above embodiment, the capacity of the data register is one word, but the present invention is not limited to this, and it is also possible to increase the number of words in the data register. That is, by increasing the capacity of the write buffer, the cache memory can be used before and after the latest write address. For example, Figure 6-
If the data register 11 is increased to four words as shown in FIG.

Writes within the range of 4111, including the most recent write, can be processed in the cache memory.Flag bits added to each word in each data register lla, llb, lie, 11d indicate that a write to each word is Used to indicate whether or not it has been carried out. The write control circuit 3 determines whether or not to rewrite the main memory by referring to the FZG bit.

By expanding the number of words in the data register in this manner, the probability that a write operation can be processed within the cache memory can be increased.

[Effects of the Invention] As described above in detail, the present invention has the following effects.

Because a write buffer is provided, fewer accesses to the main memory are required when writing is repeatedly performed to the same address.For example, Motorola's processor 6
When using the 8020, the ratio of write accesses to total accesses is about 20%. Assuming that the probability that the necessary data is present in the cache memory is fc90%,
In a write-through type cache memory, 72% of the total accesses are processed by the cache memory.

Higher system processing performance is achieved.

Furthermore, in the present invention, the effect of the cache memory can also be expected for write access.

Assuming that the probability of successive writes to the same or neighboring addresses, that is, the probability of being processed within the buffer, is 30%, 6% of the total accesses will be processed within the write buffer. At the same time, accesses to main memory decrease from 28% to 22% of total accesses. Therefore, according to the present invention, it is possible to improve the processing power of the processor by several percent, reduce the usage of the system bus of the processor to about 81111, and improve the overall performance.

[Brief explanation of the drawing]

FIG. 1 is a main part configuration diagram showing an embodiment of a cache memory control system according to the present invention. 2 to 5 are time charts for explaining the operation, FIG. 6 is a block diagram of a data register portion showing another embodiment of the present invention, and FIG. 7 is a block diagram of a conventional system using a cache memory. 101. Processor, 2... Cache memory, 3.
...Cache memory control circuit, 4...System bus, 5...Main storage device, 11...Data register, 1
2...Address register, 13...Comparator,
14°16... Buffer, 15... Write control circuit. Fig. 3 Te 2 □ Fig. 4 xt Te'ri Fig. 5 Wl〒11
Ikutaka and Memory Lf
1 push J 10 funeral 6 figure γ dore ^ Figure 7

Claims (1)

[Scope of Claim] A system provided with a cache memory and a cache memory control circuit for controlling the cache memory between a processor and a main storage device, comprising: a data register that holds data of the latest write operation; an address register that holds an address in the latest write operation output from the processor; a comparator that compares the contents of this address register with the address of the current write given by the processor; and the main storage device and the cache memory control. a buffer that controls connection with a circuit; a control signal necessary to control writing to the data register and the address register, and rewriting of the main memory, and completion of an access cycle to the main memory; [1] In a write operation, if there is no data to be rewritten in the cache memory, the data is written to the main storage device, and vice versa. If there is data to be rewritten in the cache memory, if the comparison result in the comparator matches, the data register is rewritten; if not, the main memory is first rewritten based on the contents of the data register and address register, and then the current [2] In the read operation, in the case of reading data that is not in the cache memory, the desired data is read from the main storage device and stored in the cache memory or the address register. A cache memory control system characterized in that a main storage device is rewritten based on the contents of the data register and address register after the data is sent to a processor.