JPS5815877B2 - Buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory control method that prevents information at the same address as a previous memory access from being written twice into the buffer memory in a storage method having a buffer memory. In particular, the present invention relates to one in which a flag is provided to indicate that a set of preceding access addresses is undergoing move-in processing.

□In a storage system that has a buffer memory, it is possible to prevent information at the same address as the preceding mail access from being written twice into the buffer memory, and
To prevent subsequent accesses from referencing blocks to be replaced in buffer memory, the address of the preceding access and the address of the subsequent access are conventionally
A comparison device was provided to compare the addresses, and when both addresses reached 2, subsequent accesses were suppressed until the previous access was completed.

The conventional method will be explained with reference to FIG.

In the figure, 1 is a buffer address register, 2°2' is a tag memory, 3.3' is a data memory, 4.5 is an address, register, 6.6' is a comparison-17 is a selector,
8 and 9 are comparators, 10 is an AND circuit with negation that is conductive when all inputs are logic "0", 11 is an AND circuit that is conductive when all inputs are logic "1", and 12 is a main memory address. It is a register.

When accessing the storage device, first the sofa memory number is accessed.

At this time, the access address to be accessed is temporarily written in buffer address register 1.

Comparators 6 and 6' compare all addresses of the same set as the access address stored in tag memories 2 and 2'.

If this happens, the data at the above access address is
If the data is stored in the data memory 3 or 3', a selector signal is sent from the tag memory 2 or 2' to the selector 7, and the data corresponding to the access address is
It will be sent as buffer memory read data.

However, if the data corresponding to the access address is not stored in the buffer memory, the comparators 6 and 6' output logic "0" and transmit it to the AND circuit 10.

The access address temporarily written in buffer address 1 is also transmitted to comparators 8 and 9.

The contents of the address registers 4 and 5 are transmitted to the comparators 8 and 9.

In address registers 4 and 5, the previous access address to the main memory is written.

Therefore, if the address written in the buffer address matches the previous access address, a logic "1" is output from the comparator 8 or 9 and transmitted to the AND circuit 10 with negation. A logic "0" is output from the AND circuit 10.

Since this "0" output is transmitted to the AND circuit 11, the AND circuit 11 outputs a logic "0".

Therefore, if the address matches the previous address, access to the main memory will be prevented.

However, the access address written in buffer address register 1 is different from the previous access address, and the access address is in tag memory 2 or 2.
′ is also not stored, AND circuit 1 with negation
All zero inputs become logic "0".

Therefore, the AND circuit 10 with negation outputs a logic "1" and transmits it to the AND circuit 11, so the address written in the buffer address register 1 is transferred to the address register via the AND circuit 11. 12 and accesses the main memory.

However, in the conventional device as described above, it is necessary to store the previous access address, and a plurality of address registers 4 and 5 are required for this purpose, which has the disadvantage of complicating the device.

For example, in the case of an interleaved main storage device,
This means that a large number of address registers must be prepared.

Therefore, an object of the present invention is to improve this problem, and for this purpose, in the buffer memory control method of the present invention, the main memory, a part of the data stored in the main memory, and In a set-associative buffer memory system having a buffer memory in which the address is written, a flag memory having a set corresponding to the set in the main memory device and a set check circuit are provided. If there is a preceding access to the storage device, turning on a flag of a set corresponding to the address of the preceding access destination in the flag memory to prohibit subsequent access to this set;
The set check circuit is configured to apply the output signal of the flag memory and the output signal of the tag memory in the buffer memory, and when there is a subsequent access request, the address of the access request is set. The present invention is characterized in that the main storage device can be accessed only when the address set is not the same as that of the preceding access.

An embodiment of the present invention will be described based on FIGS. 2 and 3.

In the figure, the same reference numerals as those in FIG.
7 is an address register, and 18 is a main memory.

As shown in FIG. 32, the main memory 18 is divided into 2n sets.

The items stored in the data memory 3゜3' are items stored in the same set of main memory 18 as those sets, and the addresses thereof are stored in the tag memories 2, 2'. There is.

As shown at the beginning of FIG. 3, the flag memory 13 has the same number of sets as the main memory 18.

The flag memory 13 is used as follows.

That is, there is a data access, the buffer memory is accessed, tag memories 2 and 2' are indexed, and
As a result, if it is found that the required data is not stored in the buffer memory, the main storage device 18 is accessed.

At this time, the flag is written to the same set in the flag memory 13 as the set to which the main memory 18 is accessed.

Therefore, a set with this flag has a previous access.

This flag is called a Move In flag.
Flag).

- In one embodiment of the invention shown in FIG. 2, when accessing data, the buffer memory is first accessed.

At this time, the address of the data to be accessed is temporarily written in buffer address register 1.

Then, as in the case of FIG. 1, the tag memory 2,
The address stored in memory 2' is indexed, and if the necessary data is stored, that data is transferred to data memory 3 or 3.
' and is introduced into the AND circuit 14 from the selector 7.

At this time, if the preceding access is not made to the same set as the read data, the flag memory 13
Logic “o” is output from and the AND circuit with negation 1
4, the AND circuit 14 with manual negation becomes conductive and outputs the buffer read data transmitted from the selector 7.

However, if the data to be accessed is not stored in the buffer memory as a result of indexing the tag memory lJ2, 2', a logic "0" is output from the comparators 6, 6', which is negated. The signal is transmitted to one input terminal of the AND circuit 15.

At this time, if there is no prior access to the data stored in the main memory in the same set as the data to be accessed, a logic "0" is output from the flag memory 13 and the corresponding AND circuit 15 is outputted. The rOJ output will be applied.

Therefore, the AND circuit with negation outputs a logic "1" and transmits it to the AND circuit 16.

Therefore, the address transmitted from the buffer address register 1 is passed through the AND circuit 16 as an address.
The data will be written into the register 17 and the main memory 18 will be accessed.

If there is a previous access in the same set, the flag memory 13 stores the move data to the part of that set.
Since the in flag has been written, a logic "1" is output.

Therefore, the AND circuit 15 with negation outputs a logic "0" and the AND circuit 16 is not conductive. Therefore, when accessing the main memory device, the flag written in the flag memory 13 after the previous access is completed. It will stop until it is deleted.

This prevents the same address information from the previous access from being stored twice in the buffer memory.

Of course, even if it turns out that the required data is stored in data memory 3 or 3' when tag memories 2 and 2' are first indexed, if that set has been previously accessed; Since the move-in flag is written in , the logic "1" is written from the flag memory 13.
is output and transmitted to the AND circuit 14 with a single power negation,
Since the AND circuit 14 with manual negation is turned off, data cannot be read until the preliminary access is completed.

This can prevent the subsequent access from referencing the block to be rewritten that is scheduled for the preceding access.

Furthermore, when accessing the main storage device 18,
As mentioned above, the move-in flag "1" is written to the corresponding set of the flag memory 13, but at this time the tag
Read memory 2 and read the address of the data to be rewritten at the same time.

Next, this will be explained based on FIG.

FIG. 4A shows the configuration of one embodiment, and FIG. 4A shows its time chart.

In the figure, the same reference numerals as in FIGS. 1 to 3 indicate the same parts, and 19 is LRU (Least Recently
20 is a selector, and 21 is a rewrite address register.

When data is accessed in the buffer memory, the tag memory 2 or 2' is first indexed and read, and if it is found that the required data is not stored in the buffer memory, the main memory 18 is accessed next. However, at this time, if the preceding access is not performed in the same set,
A move-in flag "1" is written in the flag memory 13 for the corresponding set.

Furthermore, the address of the data block for rewriting is transmitted from the replacement control circuit 19 to the selector 20.

Therefore, the address of the block specified by the replacement control circuit 19 is sent from the selector 20 and stored in the rewriting address register 21, thereby preparing for data rewriting in the buffer memory.

In other words, when controlling the buffer using the swap method, this rewriting address is required for move out.

Therefore, as shown in FIG. 4, when the move-in flag is written into the flag memory 13 in the next cycle after the tag memory 2 or 2' is indexed, the data write request is simultaneously written in parallel. You can read the address for

Therefore, processing can be performed in parallel in a short time using a pipeline system.

As explained above, according to the present invention, when there is a preceding access, subsequent accesses to the same set are stopped by setting a flag for that set, so information on the same address as the preceding access is duplicated. As in the past, many addresses and
This can be achieved with a simple configuration using a flag memory without using a complicated configuration using registers.

Moreover, it is also possible to prevent subsequent accesses from referring to the block to be rewritten in the buffer memory.

Then, when writing the flag indicating the existence of advance access in the flag memory, the address of the rewriting data block can be read in parallel, so even if the buffer is managed using the swap method, for example, the overall It is possible to process data in a short time.

[Brief explanation of the drawing]

FIG. 1 is a conventional buffer memory control system, FIG. 2 is a configuration diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between the main storage device, buffer memory, and flag memory in the present invention. FIG. 4 is a block diagram for reading a rewritten address in the present invention, and its explanatory drawing numbers. In the diagram, 1 is a buffer address register, 2°2' is a tag memory, and 3 and 3' are data・Memory, 4.5 is address register, 6, 6' is comparator, 7 is selector,
8 and 9 (are comparators, 10 is an AND circuit with negation, 11 is an AND circuit, 12 is a main memory address register, 13
is memory for flags, 14 is AND circuit with single power negation, 1
5 is an AND circuit with negation, 16 is an AND circuit, 17 is an address register, 18 is a main storage device, 19 is a replacement control circuit based on the LRU algorithm, 20 is a selector, and 21 is a rewriting address register.

Claims (1)

[Scope of Claims] 1. In a set-associative buffer memory system having a main memory device and a buffer memory in which a part of data stored in the main memory device and an address thereof are written, the main memory A flag memory having a set corresponding to the set of the device and a set check circuit are provided, and when there is a pre-access to the main memory, the flag memory having a set corresponding to the pre-access destination address of the flag memory is provided. The flag is turned on to prohibit subsequent access to this set, and the set check circuit is configured to apply the output signal of the flag memory and the output signal of the tag memory in the buffer memory, and 1. A buffer memory control method characterized in that when there is an access request to access a main storage device, the main storage device can be accessed only when the set of addresses of the access request is not the same as the set of addresses of the previous access. 2 The output of the tag memory is guided to a selector, and the selector is controlled by an LRU replacement circuit to determine the rewrite address, and the rewrite address is determined when writing the flag in the flag memory. A buffer memory control system according to claim 1, characterized in that