JPS5577072A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5577072A
JPS5577072A JP15064478A JP15064478A JPS5577072A JP S5577072 A JPS5577072 A JP S5577072A JP 15064478 A JP15064478 A JP 15064478A JP 15064478 A JP15064478 A JP 15064478A JP S5577072 A JPS5577072 A JP S5577072A
Authority
JP
Japan
Prior art keywords
access
memory
attained
flag
leading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15064478A
Other languages
Japanese (ja)
Other versions
JPS5815877B2 (en
Inventor
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53150644A priority Critical patent/JPS5815877B2/en
Publication of JPS5577072A publication Critical patent/JPS5577072A/en
Publication of JPS5815877B2 publication Critical patent/JPS5815877B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To prevent double write operation, etc., by a simple constitution by allowing access to a main memory unit only when a set of addresses of an access request disagree with those of addresses of leading access, by providing a flag memory.
CONSTITUTION: As a result of referring to indexes of tag memory 2', when no data to be accessed is found stored in data memory 3, comparators 6 and 6' output logic "0" and NAND circuit 15 outputs logic "1" to close AND gate 16, so that access to a main memory unit will be attained through buffer address register 1 and address register 17. In this case, when leading access of the same set is attained, memory 13 outputs logic "1" by a flag written at the set part of flag memory 13 and circuit 15 outputs logic "0" to close gate 16. Consequently, no access to the main memory unit is attained and the double writing operation to the buffer memory can be prevented by a simple constitution requiring no registers stored with leading access.
COPYRIGHT: (C)1980,JPO&Japio
JP53150644A 1978-12-05 1978-12-05 Buffer memory control method Expired JPS5815877B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53150644A JPS5815877B2 (en) 1978-12-05 1978-12-05 Buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53150644A JPS5815877B2 (en) 1978-12-05 1978-12-05 Buffer memory control method

Publications (2)

Publication Number Publication Date
JPS5577072A true JPS5577072A (en) 1980-06-10
JPS5815877B2 JPS5815877B2 (en) 1983-03-28

Family

ID=15501346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53150644A Expired JPS5815877B2 (en) 1978-12-05 1978-12-05 Buffer memory control method

Country Status (1)

Country Link
JP (1) JPS5815877B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02148329A (en) * 1988-11-30 1990-06-07 Fujitsu Ltd System for controlling register access competition
WO2007088591A1 (en) * 2006-01-31 2007-08-09 Fujitsu Limited Memory access control apparatus and memory access control method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60165691U (en) * 1984-04-10 1985-11-02 三菱電機株式会社 Heat exchanger

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02148329A (en) * 1988-11-30 1990-06-07 Fujitsu Ltd System for controlling register access competition
WO2007088591A1 (en) * 2006-01-31 2007-08-09 Fujitsu Limited Memory access control apparatus and memory access control method

Also Published As

Publication number Publication date
JPS5815877B2 (en) 1983-03-28

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