JPH02148329A - System for controlling register access competition - Google Patents

Abstract

PURPOSE:To suppress the increase of a hardware quantity and the lowering of the performance of a processor to the minimum by stopping preceding control when both outputs of a reference and rewriting registers are on. CONSTITUTION:When rewriting of a register is performed in a 3rd pipe stage 14, the flag of a rewriting register 16 is set and, when a succeeding instruction performs register reference, reference registers 10A and 10B are set in a 2nd pipe stage 7. When all the registers 16, 10A and 10B are turned on, a controlling section 19 outputs an execution stopping signal and stops the execution of the 1st and 2nd pipe states 1 and 7. Thus the preceding control is stopped. When rewriting is completed in the 3rd pipe stage, the flag of the register 16 is reset and the execution stopping signal is turned off, and thus, the preceding control is restarted.

Description

[Detailed Description of the Invention] [Summary] Regarding a register access contention control method in a processor of an information processing device that performs pipeline control, the present invention aims to minimize the increase in hardware ink and the performance deterioration of Processera 1. The purpose of the present invention is to provide a register access contention control method that provides a first pipe stage for analyzing an input instruction and detecting a register number to be referenced in a processor of an information processing device that performs pipeline control; a second pipe stage that has a reference register that holds a number and references the register if and detects the register number to be rewritten; and a rewriting register that has a flag that is set when rewriting is performed and reset when rewriting is completed. a third pipe stage that rewrites a register group; and a control unit that controls execution of the first pipe stage and the second pipe stage based on outputs from the reference register and the rewriting register, When the outputs of the reference register and the rewriting register are both on, execution of the first pipe stage and the second pipe stage is inhibited.

[Field of Industrial Application] The present invention relates to a register access contention control method in a processor of an information processing device that performs pipeline control.

In recent years, with the demand for faster computer systems,
There is an increasing demand for faster instruction execution.

For this reason, in processors, it has become common to perform advance control using a pipeline system that allows one instruction to be executed by a plurality of units and to process a plurality of instructions at the same time.

However, when accessing a register in each unit, control is required to avoid conflicts so that the next instruction that has been partially executed due to advance control is not executed before the contents of the register are rewritten.

[Prior Art] In pipeline processors, if registers are allowed to be rewritten independently in each pipe stage, resource contention between pipes will occur, so registers can only be rewritten in a specific pipe stage. This is because malfunctions will occur if the rewritten register values are not correctly reflected in subsequent instructions.

Therefore, instruction 1 that may rewrite registers
is executed, it checks whether the following instruction 2 references a register, and if there is a register reference, it checks whether that register will be rewritten by instruction 1, and if rewriting is performed, stops the preceding control of the subsequent instruction 2 until the instruction 1 is completed.

In other words, register rewrite instruction 1 has register number R.
If consecutive registers 1 to R2 can be rewritten, the reference register number of the subsequent instruction 2 is set as RX, and it is checked whether R1≦RX≦R2, and if that condition is met, the subsequent instruction Preliminary control of instruction 1 was stopped.

[Problem to be solved by the invention] However, in such a conventional control method,
When the number of registers referenced by subsequent instructions is large, it is necessary to compare the magnitude of R1/R2/RX for each referenced register number, resulting in an increase in bar draw.

In addition, as the number of registers increases, the size comparison circuit
There is also the problem that the performance of the processor decreases due to the increase in calculation time.

The present invention has been made in view of these conventional problems, and provides a register access contention control method that minimizes the increase in the amount of hardware and minimizes the deterioration in processor performance. It is intended to.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 1 is a first pipe stage that analyzes an input instruction and detects a register number to be referenced; 7 is a reference register 10A that holds the reference register number;
0B, the second pipe stage refers to the register group 8 and detects the register number to be rewritten, and 14 is a rewriting register 16 having a flag that is set when rewriting is performed and reset to 1 to 1 when rewriting is completed. The third register which rewrites the register group 8
Pipe stage 19 is the reference register 10A, 10
This is a control unit that controls the execution of the first pipe stage 1 and the second pipe stage 7 based on each output from the rewriting register 16 and the rewrite register 16.

[Operations] In the present invention, when a register is rewritten in the third pipe stage, the flag of the rewrite register is set, and when a subsequent instruction refers to a register, the reference register of the second pipe stage is set. is set. When both the rewriting register and the reference register are on, the control unit outputs an execution stop signal and stops execution of each of the first pipe stage and the second pipe stage. In this way, advance control is stopped. When rewriting is performed in the third pipe stage, the flag of the rewriting register is reset, the execution stop signal is turned off, and advance control is restarted.

In this way, register contention can be controlled without increasing the hard disk count or degrading processor performance.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a diagram showing an embodiment of the present invention.

In FIG. 2, 1 is the first pipe stage that analyzes the meaning of the instruction, and this first pipe stage 1 stores the data buffer 3 that holds the instruction code supplied from the instruction buffer 2, and the register number to be referenced. It has a decoding circuit 4 for detection, a logic circuit 5 for converting data held in a data buffer 3, and an AND circuit 6 to which a tarok and an execution stop signal Z are input.

A second pipe stage 7 refers to the register/meta group 8, and this second pipe stage 7 refers to the logic circuit 5.
A data buffer 9 holds the data supplied from the register, reference registers 10A and 10B hold the register number to be referenced and are set by the output of the decoding circuit 4 and select the output of the register group 8 to be referenced, and a register number to be rewritten is A logic circuit 1 that generates supply data using a decoding circuit 11 that detects, data held in a data buffer 9, and register reference data from a register group 8.
2, and an AND circuit 13 to which a clock signal and an execution stop signal Z are input.

14 is a third pipe stage that rewrites the register group 8, and this third pipe stage 14 includes a data buffer 15 that holds data supplied from the logic circuit 12 and processed data, and a flag indicating that the data is to be rewritten. , which is set by the output from the decoder circuit 11 and reset when the old rewrite is performed, generates rewrite data to the rewrite register 16 and register u8, and processed data to be set to the data buffer 15 via the multiplexer 17. It has a logic circuit 18.

19 is a control unit that controls the execution of the first pipe stage 1 and the second pipe stage 7, and this control unit 19 has the following functions:
Decode circuits 20Δ, 20B that generate reference signals (REFn) based on reference register numbers held in reference registers 10A, 10B; OR circuits 21A, 21 that receive reference signals (REFn) from decode circuits 2OA, 20B;
B, AND circuits 22A, 22B, and AND circuit 22A to which the outputs from the OR circuits 21A, 21B and the rewriting signal (RnW) from the rewriting register 16 are input.

It has an OR circuit 23 to which the output of 22B is input and outputs an execution stop signal Z. Note that 24.25 is set to register u8 by the select signal from reference registers 10A and 10B.
This is a multiplexer that outputs reference data from the logic circuit 12 to the logic circuit 12.

Next, the operation will be explained.

When an instruction 1 that rewrites the register group 8 comes in from the instruction buffer 2, when the instruction 1 passes through the data buffer 3 and the logic circuit 5 and is held in the data buffer 9 of the second pipe stage 7, the second pipe stage The decoding circuit 11 of No. 7 detects register numbers corresponding to the number of registers of the register RY8 to be rewritten and outputs them to the third pipe stage 14.

In the next cycle, instruction 1 is transferred to the data buffer 15 of the third pipe stage 14 through the logic circuit 12, and at the same time, the flag of the rewrite register 16 is set.

In the meantime, if the next instruction enters the first pipe stage 1 and that instruction is instruction 2 that refers to a register, then
The decode circuit 4 detects the register number to be referenced. At the same time that the register reference instruction 2 is set in the data buffer 9 of the second pipe stage 7, the register number is set in the reference registers 10A and 10B. Each output of the reference registers 10A and IOB is converted into a reference signal (REFn) by the decoding circuits 2OA and 20B of the control unit 19.
). A rewrite signal (
RnW) is output, so the AND circuits 22A, 2
2B is turned on, the OR circuit 23 is turned on, and an execution stop signal Z is output.

The execution stop signal Z inhibits the clocks of the AND circuits 6 and 13, and the data buffers 3 and 9 maintain their states.

In this way, the reference signal (REFn) and the rewriting signal (R
nW) are both on, the advance control is stopped until the rewriting is completed.

Next, when the register RY8 is rewritten in the third pipe stage 14, the flag of the rewrite register 16 is reset, the execution stop signal @7 is not output, and the clocks of the AND circuits 6 and 13 are suppressed. The data buffers 3 and 9 start executing.

Therefore, advance control will be restarted.

[Effects of the Invention] As explained above, according to the present invention, even when the number of registers to be referenced increases, the number of registers can be increased without increasing the hardware capacity and without degrading the performance of the processor. Conflicts can be controlled.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention. In the figure, 1: 1st pipe stage, 2: Instruction buffer, 3: Data buffer? , 4: Decode circuit, 5: Logic circuit, 6: AND circuit, 7: 2nd pipe stage, e: register number, 9: Data buffer? , 10A, 10B: reference register, 11: Decode circuit, 12: Logic circuit, 13: AND circuit, 14: 3rd pipe stage, 15: Data buffer, 162 rewrite register, 17: Multiplexer, 18: Logic circuit, 19: control unit, 2OA, 208: decoding circuit, 21△, 21B: OR circuit, 22A, 22B: AND circuit, 23: OR circuit.

Claims (1)

[Claims] A processor of an information processing device that performs pipeline control includes a first pipe stage (1) that analyzes an input instruction and detects a register number to be referenced, and a reference register (10A) that holds the reference register number.
A second pipe stage (7) that refers to the register group (8) and detects the register number to be rewritten, and a flag that is set when rewriting is performed and reset when rewriting is completed. A third pipe stage (14) having a register (16) and rewriting the register group (8), and each output from the reference registers (10A), (10B) and the rewrite register (16) a control unit (19) that controls execution of the pipe stage (1) and the second pipe stage (7);
10A), (10B) and the rewrite register (10B)
6) when both outputs are on, the first pipe stage (1) and the second pipe stage (7)
A register access contention control method characterized by inhibiting execution of the register access contention control method.