JPH07244588A - Data processor - Google Patents

Abstract

PURPOSE:To simultaneously execute a multi-cycle instruction(MI) and a reference instruction by adding the irreducible minimum of hardware. CONSTITUTION:An Ml is inputted to an instruction decoding circuit 1. An instruction execution control circuit 2 issues the MI to an MI executing circuit 5 in accordance with information from an MI execution managing circuit 8. An input circuit 3 and an output circuit 6 execute the operation of data necessary between a register and the circuit 5. When a reference instruction following the MI is inputted to the circuit 1, the circuit 2 issues the reference instruction to a reference instruction executing circuit 4 after confirming that the writing cycle of the MI in a register group 7 does not collide with the writing cycle of the reference instruction by the information from the circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor provided with an instruction control circuit capable of implementing a multi-cycle instruction having a low occurrence frequency and a high execution latency without adding a minimum required amount of hardware without causing performance degradation. It is a thing.

[0002]

2. Description of the Related Art Microprocessor control technology that enables parallel execution of instructions is drawing attention as a method that enables faster instruction execution.

Conventionally, when a functional unit dedicated to a multi-cycle instruction is provided in order to suppress overall performance deterioration,
When the hardware is increased and shared with other arithmetic units, the execution of other instructions is stalled, and the overall performance is reduced.

[0004]

The increase in the amount of hardware when a functional unit dedicated to multi-cycle is provided is as follows.
Examples include an input / output unit and a calculation unit of the functional unit.

Further, since there are a plurality of functional units, an arbitration process for selecting a functional unit to be written is required due to resource competition at the time of completion of calculation and at the time of using the output circuit, which causes increase in hardware.

[0006]

In order to solve the above problems, a data processing apparatus having an instruction execution control circuit of the present invention includes an instruction decoding circuit for decoding an instruction and an instruction execution for controlling execution of an instruction. A control circuit, a basic instruction execution circuit for executing basic instructions, a multi-cycle instruction execution circuit for executing multi-cycle instructions, a register circuit for storing data, and the basic instruction execution circuit for referencing the contents of the register An input circuit for processing as input data to the multi-cycle instruction execution circuit and a data output from the basic instruction execution circuit or the multi-cycle instruction execution circuit are input and necessary processing is performed to write to the register circuit. For controlling the operation of the multi-cycle instruction execution circuit without being controlled by the output circuit and the instruction execution control circuit. Comprising a multi-cycle instruction execution management circuit which, upon issuance of basic instructions subsequent to the multi-cycle instruction, and characterized by performing without stalling the basic instruction issuance by the instruction execution of the multi-cycle instruction.

Further, the data processing device detects a write collision or a main force by previously detecting, by the multicycle instruction execution management circuit, a write cycle to the register circuit at the end of the multicycle instruction and a cycle in which the output circuit is used by the multicycle instruction. It is characterized by suppressing the issuance of basic instructions that cause circuit competition.

[0008]

With the above-described structure, the present invention enables execution of basic instructions that are stalled by execution of multi-cycle instructions in the conventional structure.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing apparatus having an instruction execution control circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data processing apparatus having an instruction execution control circuit according to an embodiment of the present invention.

In FIG. 1, 1 is an instruction decoding circuit, 2 is an instruction execution control circuit, 3 is an input circuit, 4 is a basic instruction execution circuit, 5 is a multi-cycle instruction execution circuit, 6 is an output circuit,
Reference numeral 7 is a register circuit, and 8 is a multi-cycle instruction execution management circuit.

FIG. 2 shows an example of an instruction sequence for explaining the operation. F0 to F6 in the instruction sequence indicate register names.

Of these, the first letter F identifies the floating point register and the second number identifies the register name.

FADD represents a floating point addition instruction. FADD is an instruction of execution latency 3, FDIV
Is a multi-cycle instruction with an execution latency of 4.

It is assumed that they are executed by the functional units of the basic instruction execution circuit 4 and the multi-cycle instruction execution circuit 5, respectively. Although the execution latency of the multi-cycle instruction is fixed for the sake of explanation, this can be controlled by being variable.

The last digit in the instruction indicates the order of execution of the instruction. In the instruction operation, the first operand is the destination and the second and third operands are the sources.

FIG. 3 shows an example of pipeline operation for explaining the operation. Here, a pipeline operation when the instruction sequence of (FIG. 2) is executed is shown.

DEC is an operation in the instruction decoding circuit 1, EX1
Is an execution operation in the input circuit 3, EX2 is an execution operation in the basic instruction execution circuit 4, EX_MULTI is an execution operation in the multi-cycle instruction execution circuit 5, and EX3 is an execution operation in the output circuit 6. The operation of the data processing device having the instruction execution control circuit according to the embodiment will be described below with reference to FIGS.

The instruction sequence of FIG. 2 will be described. When the operation starts, FADD0 which is the first instruction
The instruction is read into the instruction decoding circuit 1.

The instruction decoding circuit 1 decodes the instruction, determines whether the decoded instruction is a basic instruction or a multi-cycle instruction, and notifies the instruction execution control circuit 2 of it. This instruction execution control circuit 2 has a plurality of instruction streams and instruction decoding circuit 1
There is a one-to-one correspondence with each other.

The instruction execution control circuit 2 inputs the information of the currently executed multi-cycle instruction from the multi-cycle instruction execution management circuit 8 through the multi-cycle instruction control line 13.

For the sake of explanation, it is assumed that, before the execution of the instruction sequence, the input from the multi-cycle instruction execution management circuit 8 to the instruction execution control circuit 2 has not sent a signal for inhibiting the issuance of the multi-cycle instruction.

According to the decoded instruction, the instruction execution control circuit 2 supplies a register, which is a source of the instruction executed by the basic instruction execution circuit 4 or the multi-cycle instruction execution circuit 5, through the register selection control line 14 so that the register circuit 7 is controlled. Select from

Further, the instruction execution control circuit 2 issues an instruction to the basic instruction execution circuit 4 or the multi-cycle instruction execution circuit 5 according to the decoded instruction or to a functional unit (not shown in the figure) which executes an instruction. .

(FIG. 2) FADD0 in the instruction sequence example
The instruction is decoded in the first cycle and issued to the input circuit 3 in the second cycle. In this second cycle, the FDIV instruction is read by the instruction decoding circuit 1 and decoded. The instruction execution control circuit 2 determines that this instruction is a multi-cycle instruction at the time of decoding this instruction, and the multi-cycle instruction execution management circuit 8 obtains information that the multi-cycle instruction is not executed. ,
The instruction execution control circuit 2 issues an instruction to the input circuit 3.

The control of issuing the multi-cycle instruction is the selection of the register as the source from the register group corresponding to the above-mentioned instruction sequence, the fetching of the source data into the input circuit 3, and the control of the multi-cycle instruction executing circuit 5.
The instruction execution control circuit 2 does this.

With respect to the issued multi-cycle instruction, the multi-cycle instruction execution management circuit 8 controls instruction execution in a plurality of cycles. Next, the instruction issuance in the third cycle, which is the next cycle after the multi-cycle instruction is issued, will be described.

The instruction following the multi-cycle instruction is decoded by the instruction decoding circuit 1. This instruction is either a basic instruction or a multi-cycle instruction or an instruction issued to another functional unit.

When this subsequent instruction is an instruction issued to another unit, it is issued in the same manner as in a normal data processing device having a plurality of functional units.

In this cycle, the execution latency of the FDIV1 instruction which is a multi-cycle instruction is 4, so if the basic instruction is issued in this cycle, the output circuit 6
Causes processing conflict.

With respect to the occurrence of this conflict, the multi-cycle instruction execution management circuit 8 manages the execution latency of the issued multi-cycle instruction, and when the conflict occurs, it notifies the instruction execution control circuit 2 of the occurrence of the conflict.

Further, the multi-cycle instruction execution management circuit 8
Detects in advance the execution cycle in which the writing to the register circuit occurs in the execution of the multi-cycle instruction,
The instruction execution control circuit 2 is notified of the case where the write cycle generated by the execution of the basic instruction conflicts with the write cycle of the multi-cycle instruction.

Thus, the write collision in the instruction stream can be avoided without the need for the arbitration circuit for avoiding the write collision.

In this fourth cycle, the basic instruction FAD
Decoding of D2 is performed by the instruction decoding circuit 1, and the basic instruction FA
The output circuit 6 executes DD0 and the multi-cycle instruction execution circuit 5 executes the multi-cycle instruction FDIV1.
It is done in. In this cycle, in the multi-cycle instruction execution management circuit 8, since the execution latency of the multi-cycle instruction currently being executed is 4 and the current execution cycle is the second, the write cycle of the multi-cycle instruction occurs after two cycles. To the instruction execution control circuit 2.

In response to this notification, the instruction execution control circuit 2 issues an instruction in the cycle next to the basic instruction FADD2 which is the execution latency 3.

Therefore, the register write operation is 5, 7,
In the 8th cycle FADD0, FDIV1,
Since it is performed with FADD2, a write collision does not occur.

The main circuit 6 is used in the 4th, 6th and 7th cycles, and no conflict occurs.

[0038]

As described above, according to the present invention, by providing the multi-cycle instruction execution management circuit, the instruction execution control circuit, the multi-cycle instruction execution circuit, the basic instruction execution circuit, the input circuit, and the output circuit, the minimum necessary Addition of hardware enables simultaneous execution of multi-cycle instructions and basic instructions. Further, the instruction execution control circuit issues a basic instruction when the execution of the multicycle instruction is completed by the multicycle instruction execution management circuit, that is, when the multicycle instruction writes to the register group and the cycle in which the multicycle instruction uses the output circuit. Therefore, it is possible to prevent the arbitration operation of conflict avoidance due to the basic instruction and the multi-cycle instruction simultaneously writing to the register circuit or simultaneously using the output circuit.

Therefore, the increase in hardware when the execution unit dedicated to the multi-cycle instruction is provided is suppressed, and the basic instruction is executed without causing the execution stall of the basic instruction due to the multi-cycle instruction. Can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention.

FIG. 2 is an instruction sequence diagram used to describe an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a pipeline operation used to describe an embodiment of the present invention.

[Explanation of symbols]

 1 instruction decoding circuit 2 instruction execution control circuit 3 input circuit 4 basic instruction execution circuit 5 multi-cycle instruction execution circuit 6 output circuit 7 register circuit 8 multi-cycle instruction execution management circuit

Claims (1)

[Claims] 1. An instruction decoding circuit for decoding an instruction, a register circuit for holding data, a basic instruction execution circuit for executing instructions having a plurality of pipeline stages, and a pipeline stage number in the basic instruction execution circuit. A multi-cycle instruction execution circuit that executes a multi-cycle instruction that requires a large number of execution stages, a multi-cycle instruction execution management circuit that manages the execution of the multi-cycle instruction execution circuit, and a basic instruction execution circuit from the register circuit. Alternatively, an input circuit for processing and passing data to the multi-cycle instruction execution circuit, an output circuit for processing and passing data from the basic instruction execution circuit or the multi-cycle instruction execution circuit to the register circuit, and a register at the time of instruction completion Running multi-cycle lives to avoid write conflicts The instruction execution control circuit is provided to prevent the basic instruction from using the output circuit at the same time when the instruction completes and in the cycle in which the multicycle instruction uses the output circuit. A data processing device comprising an instruction execution control circuit for performing execution control without hindering execution.