JP3493768B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction issue control device and a multi-cycle instruction decoding management which can implement a multi-cycle instruction having a low occurrence frequency and a high execution latency without adding performance degradation by adding a minimum required amount of hardware. The present invention relates to a data processing device including a device.

[0002]

2. Description of the Related Art Microprocessor control technology that enables parallel execution of instructions is drawing attention as a method that enables faster instruction execution.

Conventionally, a multi-cycle instruction which requires a plurality of cycles for execution has been realized by incorporating a microprogram in a decoding mechanism or an execution circuit and sequentially executing them. When this multi-cycle instruction is implemented in a microprocessor having a plurality of instruction streams, if a microprogram is provided for each plurality of instruction streams, an increase in hardware will occur.

[0004]

When the hardware is increased due to the existence of a plurality of multi-cycle instruction decoding mechanisms, or when the multi-cycle instruction decoding mechanism is shared, an arbitration process for causing resource competition and selecting a decoding mechanism is required. It was the cause of the increase in hardware.

[0005]

In order to solve the above problems, a data processor having a multi-cycle instruction decoding management circuit according to the first aspect of the present invention includes a plurality of instruction decoding circuits for decoding a plurality of instruction streams. , A register group for reading and writing data in a one-to-one correspondence with each instruction stream and a multi-cycle instruction by being informed by the plurality of instruction decoding circuits that a multi-cycle instruction is being decoded. An instruction issue control circuit that performs issue control, and a multi-cycle instruction decoder that knows the instruction stream for multi-cycle instruction decoding from the instruction issue control circuit, selects an instruction to decode from a plurality of instruction streams, and manages decoding of the multi-cycle instruction By providing a management circuit, multicycle instructions existing in multiple instruction streams can be decoded one-to-one with the instruction decoding circuit. It is characterized by performing the decryption control without providing a sense circuit.

In the data processor of the second invention of the present application, the register number used in the multi-cycle instruction is extracted by cutting out the register number referred to by the instruction to be decoded in the cycle in accordance with the instruction from the multi-cycle instruction decoding management circuit. The multi-cycle instruction decoding management circuit is characterized by executing a multi-cycle instruction without being provided in a micro-instruction.

[0007]

According to the present invention, with the above-described structure, the circuit structure which causes a significant increase in hardware due to the decoding mechanism of the multi-cycle instruction in the conventional structure is prevented.

Further, by using this configuration, it becomes possible to execute exclusive control of the instruction stream.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A data processor having a multi-cycle instruction decoding management circuit according to an embodiment of the present invention will be described below.
A description will be given with reference to the drawings.

FIG. 1 is a block diagram of a data processing apparatus having an instruction issue control circuit and a multi-cycle instruction decoding management circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a plurality of instruction decoding circuits,
2 is an instruction execution control circuit, 3 is a multi-cycle instruction decoding management circuit, 4 is a register group, 10 is a basic instruction execution circuit for performing basic operations, 11 is a load / store instruction execution circuit for writing or reading data from a memory, 14 An arbitration circuit that determines which instruction stream will use that execution circuit in the next cycle when multiple instruction streams request execution in the same execution circuit at the same time.

FIG. 2 shows an example of an instruction sequence for explaining the operation. R8a, R14a in the instruction sequence,
R16a, R24a, R8b, R14b, R16b, R
Reference numeral 24b indicates a register name. Of these, a and b at the end of the register name indicate the instruction stream to which they belong. Also SAVE, RESTORE, ST, LD, MO
V indicates an instruction. Of these, ST is a store-to-memory store instruction, LD is a memory-to-register load instruction, and MOV is a register-to-register move instruction.

SA in the instruction stream shown in (a)
The functions of VE and RESTORE are multi-cycle instructions having the same function as the instruction stream shown in (b). That is, when the instruction stream of (a) is executed, the same operation is performed functionally as when all the instruction streams of (b) are executed. The last digit in an instruction indicates the execution order of the same instruction stream. In the instruction operation, the first and second operands are sources and the third operand is a destination.

Here (in FIG. 1), the instruction decoding circuit 1 and the register group 4 are described in units of three in correspondence with the number of instruction streams. The number of each of these circuits is the same as the number of instruction streams, and the resources belonging to each instruction stream are not referred to by other instruction streams. Here, two instruction streams are shown for simplification of the description (FIG. 2).

FIG. 3 shows an example of pipeline operation for explaining the operation. In the figure, DEC is an operation in the instruction decoding circuit 1, EX is an operation in the basic instruction execution circuit 10 or the load / store instruction execution circuit 11, and MULTI-ADMIN.
Is the number of cycles of the multi-cycle instruction output from the multi-cycle instruction decoding management circuit 3. The instruction decoding circuit 1 and the register group 4 are prepared in the same number as the instruction stream, but the DEC in FIG. 3 is shown only for the instruction sequence for explanation.

A data processing apparatus having a multi-cycle instruction decoding management circuit according to an embodiment will be described below (FIG. 1) (FIG. 2).
The operation will be described with reference to FIG.

When the operation is started, the SAVE and RESTORE instructions are read into the instruction decoding circuit 1 for both the instruction streams a and b. Note that the number of instruction streams can be controlled even if it is not specified as 3 as described above. Further, it is assumed that these plural instruction streams are read by the fixed instruction decoding circuit 1 in a one-to-one correspondence with the existing instruction decoding circuits 1.

The instruction decoding circuit 1 decodes the instruction, determines whether the decoded instruction is a basic instruction or a multi-cycle instruction, and notifies the instruction issue control circuit 2 of it. This SAVE,
Although the RESTORE instruction is a multi-cycle instruction, first of all, the operation will be described regardless of whether the instruction is a multi-cycle instruction or not.

The instruction issue control circuit 2 is in the state of the basic instruction execution circuit 10 currently being executed, the state of the load / store instruction execution circuit 11 and the execution state of the multi-cycle instruction managed by the multi-cycle instruction decoding management circuit 3. The instruction flow for issuing an instruction is determined by the information of. There are multiple factors that hinder the issuance of instructions, but these are called pipeline hazards because they hinder the pipeline flow. Pipeline hazards include structural hazards caused by resource competition, data hazards caused by data dependency, and control hazards caused by control order.

Here, for the sake of simplicity of explanation, it is assumed that no data hazard occurs. The control hazard is
This is because the instruction to be issued is not supplied to the instruction decoding circuit 1 or the like, and therefore the instruction is not treated as already supplied to the instruction decoding circuit 1.

Therefore, the only problem is the structural hazard. Taking the structure of FIG. 1 as an example, since the instruction decoding circuit 1 and the register group 4 have resources corresponding to the number of instruction streams, no structural hazard occurs, but the basic instruction execution circuit 10 and the load / store instruction execution circuit 11 Is 1 each under the assumption of (Fig. 1)
Since there is only one, if you try to use the same circuit with multiple instruction streams, resource conflict will occur and it will be a structural hazard.

The instruction issue control circuit 2 has an arbitration circuit to arbitrate in order to solve the contention of resources when these structural hazards occur. For example, it is assumed that both the instruction streams a and b issue a use request to the basic instruction execution circuit 10 from the instruction decoding circuit 1 using the functional unit use request line 5 in the same cycle. In this case, the instruction issuance control circuit 2 knows whether the basic instruction execution circuit 10 can be used in the next cycle by using the basic instruction status line 13, and if it can be used, the arbitration circuit 14 in the instruction issuance control circuit 2 is activated. Command stream a, b
Which instruction to issue.

Originally, the arbitration circuit 14 is always present in a data processing device for executing a plurality of instruction streams if the number of execution circuits is not equal to or greater than the number of instruction streams.
It arbitrates usage requests from multiple instruction streams. Next, the operation in the case of a multi-cycle instruction will be described. When the instruction decoded by the instruction decoding circuit 1 is a multi-cycle instruction, the multi-cycle instruction decoding management circuit 3 manages whether the instruction can be issued, and the multi-cycle instruction is being decoded in that cycle. The instruction issue control circuit 2 is informed whether or not to continue decoding in the next cycle.

Based on this information and the information sent from the instruction decoding circuit 1, the instruction issue control circuit 2 determines whether the instruction can be issued. If only a single instruction stream decodes a multi-cycle instruction, the instruction issue control circuit 2 receives the information from the multi-cycle instruction decode management circuit 3 if the multi-cycle instruction is not decoded in the next cycle. Issuing a multi-cycle instruction is an instruction decoding circuit 1
Tell.

If the multi-cycle instruction decoding management circuit 3 is already decoding the multi-cycle instruction, the instruction issuing and decoding are stopped. When a plurality of instruction streams request the decoding of a multi-cycle instruction, the instruction issuance control circuit 2 issues an instruction when the instructions can be issued in the next cycle according to the information from the multi-cycle instruction decoding management circuit 3. The arbitration circuit 14 is used to determine the instruction flow to be executed.

When the arbitration circuit 14 determines the instruction stream for issuing the multi-cycle instruction, the arbitration circuit 14 only notifies the instruction decoding circuit 1 of the instruction stream for issuing the instruction. In the case of (FIG. 2) (FIG. 3), in the instruction streams a and b, a decoding request for a multi-cycle instruction is simultaneously issued to the instruction issue control circuit 2 in the first cycle. At this time, in the multi-cycle instruction decoding management circuit 3,
Since the multi-cycle instruction has not been decoded in the cycle before that, the instruction issue control circuit 2 uses the arbitration circuit 14 to perform arbitration.

In the case of this example, the SAVE instruction of the instruction stream a is selected by arbitration and the instruction is issued in the next cycle.
Also, this SAVE instruction is the first as shown in (Fig. 2b).
Since the cycle is an instruction having a store instruction and the second cycle is an instruction having the function of the MOV instruction, the store instruction is issued to the load / store instruction execution circuit 11 in the cycle 2 (FIG. 3).

On the other hand, the RESTORE instruction of the instruction stream b is stalled (issue is postponed) because the issue right could not be obtained due to arbitration. Here, the operations of the multi-cycle instruction decoding management circuit 3 and the instruction decoding circuit 1 at this time will be described.

The function of the multi-cycle instruction decoding management circuit 3 is to hold the state of whether the multi-cycle instruction is currently being decoded and which cycle of the multi-cycle is currently decoded, and the function of the specific multi-cycle instruction. There is a function of fetching from the memory device to the instruction execution circuit what kind of function the basic instruction operates in a certain cycle.

When the multi-cycle instruction decode management circuit 3 determines that the instruction stream a is issued in cycle 1 based on the information from the instruction issue control circuit 2, its internal state changes to a state in which the multi-cycle instruction is being executed. To do. As a result, even if the instruction stream b continues to issue a decode request for decoding the multi-cycle instruction in the second cycle, the instruction stream b is not issued and the stall continues, unless the multi-cycle instruction of the preceding instruction stream a is completed. become.

In addition, the state management unit controls the instruction issuance control circuit 2 so as to manage at what cycle the multi-cycle instruction is currently finished and permit the issuance of a new multi-cycle instruction when it is finished in the next cycle. Tell.

Further, which cycle of the present multi-cycle instruction is being decoded is transmitted to the instruction decoding circuit 1 through the information line 6, and the instruction decoding circuit 1 executes the instruction to the register group 4 according to this information. Read the necessary registers. In the case of (FIG. 2) (FIG. 3) example, SAV
Since the reading of R16 and R14 is required in the first cycle to execute the E instruction, the instruction decoding circuit 1 issues the instruction to the register group 4.

Further, in the multi-cycle instruction decoding management circuit 3, the fact that the first cycle of the SAVE instruction is a store (ST) instruction is read from the function memory unit and transmitted to the load / store instruction execution circuit 11 using the information line 8. The load / store instruction execution circuit 11 executes the store instruction in cycle 2 using these instructions and the register values. Further, since the second cycle of the SAVE instruction is the MOV instruction, the necessary register values are read out and the basic instruction execution circuit 10
Tell. In cycle 2, since this cycle is the final cycle of the multi-cycle instruction of the instruction stream a, in the next cycle, cycle 3, the state of the state management unit returns to the state in which the multi-cycle instruction is not decoded.

By these operations, the MOV instruction is executed by the basic instruction execution circuit 10 in cycle 3. Since the instruction decoding of the instruction stream a has already been completed in this cycle 3, the RESOTRE instruction in the instruction stream b is issued next.

[0035]

According to the data processor of the present invention, in decoding a multi-cycle instruction, the multi-cycle instruction can be decoded without providing a multi-cycle instruction decoding management device for each multi-instruction stream. It is possible to avoid access competition for resources shared between the users.

Further, since the instruction decoding circuit and the multi-cycle instruction decoding management circuit share the instruction decoding, the increase in hardware can be suppressed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention.

FIG. 2 is an instruction sequence diagram used to describe an embodiment of the present invention.

FIG. 3 is an explanatory diagram of a pipeline operation used to describe an embodiment of the present invention.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-281896 (JP, A) JP-A-7-182168 (JP, A) JP-A-4-360234 (JP, A) JP-A-4- 130537 (JP, A) JP 4-123230 (JP, A) JP 63-254530 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/30-9 / 38

Claims (2)

(57) [Claims] 1. A plurality of instruction decoding circuits for decoding a plurality of instruction streams, a register group for reading and writing data in a one-to-one correspondence with each instruction stream, and a multi-processor comprising a plurality of instruction decoding circuits. Knowing the instruction issue control circuit that performs issue control of the multi-cycle instruction by being notified that the cycle instruction is being decoded, and the instruction stream that performs the multi-cycle instruction decoding from the instruction issue control circuit, By including a multi-cycle instruction decoding management circuit that selects the instruction to be decoded and manages the decoding of the multi-cycle instruction, multi-cycle instructions existing in multiple instruction streams are decoded one-to-one with the instruction decoding circuit. A data processing device characterized by performing decryption control without providing a management circuit. 2. A data processing apparatus according to claim 1, further comprising an instruction decoding circuit capable of changing the information of the register number used by the instruction to be decoded by the information from the multi-cycle instruction decoding management circuit. .