JP2760273B2 - Arithmetic device and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor used in an information processing apparatus, and more particularly to a plurality of instruction streams (programs).
And a high-performance processor capable of processing in parallel.

[0002]

2. Description of the Related Art As a technique for increasing the speed of a processor, a method of preparing a plurality of function execution devices and simultaneously issuing instructions to the plurality of function execution devices using the parallelism of the instruction unit to improve the processing speed. Has been put to practical use. When this method is used, it is ideally possible to process instructions at a higher rate than the operation clock frequency. In order to perform such processing, a logic circuit for guaranteeing the validity of the result of instruction execution is required in addition to adding a function execution device. This method is generally called the super scalar method, and has been announced by Digital Equipement Corporation.
pha architecture, IBM IBM, Motorola, Apple Power
Architecture, used in Hewlett-Packard's PA-RISC architecture.

[0003] However, there is a limit to the use of the parallelism of the instruction unit, and the performance improvement in this method is actually suppressed to three to four times even when the number of function execution devices is increased infinitely. It is said. The factors that limit this parallelism are the dependencies between instructions and the disruption of instruction flow due to branching. Various schemes for overcoming these restrictions have been proposed, but the maximum performance improvement is limited to about 40 times against extreme complexity of hardware. These limitations are:
A paper published by Monica S. Lam et al. In 1992 (Monica SL
am and Robert P. Wilson, "Limits of Control Flow on
Parallelsim ", IThe 19th International Symposium on
Computer Architecture, IEEE ComputerSociety Press,
1992, pp. 46-57).

On the other hand, there has been proposed a method for improving the processing speed by increasing the efficiency of use of the function execution device by executing instructions in a plurality of instruction streams in parallel, instead of parallelism in instruction units. In this method, since there is no dependency between instruction streams, it is easier to improve the performance than the above-described instruction unit parallelism.

[0005] This method is based on a paper published by Hirata et al. In 1993 (Hiraki Hirata, Kozo Kimura, Satoshi Nagamine, Sadaji Nishizawa, Takayuki Sagishima, "Element Processor Using Multiple Threads and Multiple Instructions, Architecture," IPSJ paper. Magazine 1993 Vol34
No.4 pp.595-605). FIG.
Shows a schematic configuration of this embodiment. Hereinafter, this embodiment will be described as an embodiment of the related art.

In FIG. 2, reference numeral 11 denotes an instruction acquisition device;
Is an instruction decoding device, 13 is a function execution device, and 21 is a dependency analysis device between instructions. Reference numeral 22 denotes the function execution device 13
Is an instruction arbitration device that schedules The instruction decoding device 12 issues an instruction when the instruction arbitration device 22 is in a state where the instruction can be accepted, and when receiving an instruction from the instruction dependent device 21 that the instruction can be issued. The instructions issued from each of the instruction decoding devices 12 are assigned to the necessary function execution devices 13 by the instruction arbitration device 22, and the actual execution is performed. With the instruction arbitration device 22, the function execution device 13 can be shared among the instructions, and the use efficiency can be improved. Further, by distributing the instruction arbitration device 22 for each of the function execution devices 13, it is possible to simplify the instruction arbitration device.

[0007]

The above-mentioned conventional function execution device sharing mechanism has the following problems. First, the addition of instruction arbitration processing to the instruction execution pipeline increases the latency of instruction execution, resulting in a reduction in processing speed during instruction execution or exception processing that does not conform to the pipeline structure such as branch instructions. To bring. Second, the instruction arbitration device has a complicated structure because the number of instructions to be arbitrated increases and the arbitration logic becomes complicated when the instruction flow increases and the number of instruction decoding devices increases. Being a preventable factor. Third, if the instruction flow increases and the number of instruction decoding devices increases, the connection between the function execution device and the temporary storage device (register) required for executing the function or the connection between the buffer storage device (cache memory) is reduced. Since it is necessary to realize the operation by using a complicated switch, the delay increases, which is a factor that prevents the operating frequency from being improved. These problems limit the instruction stream and operating frequency that can be executed simultaneously by the above mechanisms.

SUMMARY OF THE INVENTION An object of the present invention is to increase the utilization rate of a function execution device within a practical range without increasing the latency of instruction execution at a high operating frequency, and to share the function execution device between instruction streams. To provide a control method.

[0009]

In order to solve the above problems, in the present invention, a processor in which a plurality of instruction streams operate in parallel, that is, a plurality of instruction acquisition devices, a plurality of instruction decoding devices, and a plurality of functions is provided. A resource allocation control device is added to a processor having an execution device, a plurality of temporary storage devices (registers), and a buffer device (cache).

This resource allocation control device is a mechanism for determining a function execution device that can be used for each clock of an instruction flow from the instruction execution information from each device and the internal setting information. The instruction decoding device can issue the instruction to the function execution device that can execute the instruction based on the function execution device use permission information determined by the resource allocation control device. That is, the resource allocation control device determines whether or not all the function execution devices in the processor can be used for each instruction stream.
The instruction decoding device determines a function execution device that executes an instruction according to a program counter of an instruction stream from among available function execution devices, and issues the instruction. Further, by notifying the instruction issuance information to the resource allocation control device, a temporary storage device and a buffer storage device for storing a result of executing the function by the function execution device are selected.

[0011] One resource allocation control device is provided in the system.
Alternatively, the number of function execution devices is prepared and distributed for each function execution device. In addition, each instruction decoding device issues one instruction at the same time, or sets the number of simultaneous instructions transmitted from the instruction acquisition device to the instruction decoding device to a plurality, and deactivates the instruction according to the available function execution device. A plurality of instructions are issued at the same time according to the available function execution device using the order issue and superscalar technology.

Further, the resource allocating device allocates resources equally to each instruction stream, or checks the use state of the function execution device for each instruction flow by software, for example, a compiler, and notifies the resource allocation control device. Thus, the assignment for each instruction stream of the function execution device in the resource assignment control device is determined. Alternatively, the resource allocation control device monitors the instruction issue information from the instruction decoding device to the function execution device for each instruction flow, thereby dynamically detecting the tendency of instruction issue in the instruction flow, and allocating the resource allocation according to the tendency. This is performed by the assignment control device.

A logic circuit is realized so that the instruction stream can use all the function execution devices, or the function execution devices that can use the individual instruction streams are limited, and the temporary storage device, the buffer storage device, and the function execution device are used. The method of simplifying the connection depends on the design of the processor, and the resource allocation control device may be distributed in accordance with the design, and a means for simplifying the logic of the resource allocation device may be selected.

[0014]

In the processor according to the first aspect of the present invention, the instruction decoding device issues an instruction to the function execution device according to the permission of the resource allocation control device. At the same time as entering the instruction decoding device, the use permission information of the function execution device is also obtained, and the function execution device to be used at the time of issuing the instruction is determined. Therefore, the number of pipeline stages for arbitrating the function execution device after the instruction is issued is increased. Without sharing the function execution devices between the instruction streams, the function execution devices can be used efficiently. Also, by making the number of function execution units that are rarely used one or less than the number of simultaneous operation instructions in the processor, resources in the chip can be effectively used. The resource allocation control device determines a usable function execution device for each clock of an instruction stream based on information from each device and internal information. Since resource allocation is determined from the information up to the previous instruction execution, the utilization efficiency of the function execution device cannot be expected as in the conventional method.However, the clock frequency can be reduced by simplifying the structure and shortening the instruction execution latency by shortening the pipeline. The processing speed can be improved. Further, according to the second aspect of the present invention, the resource allocation control devices are decentralized to simplify the structure of each resource allocation control device.

According to the third aspect of the present invention, the number of simultaneous instruction transmissions from the instruction acquisition device to the instruction decoding device is increased to increase the utilization rate of the function execution device and improve the efficiency. The instructions are issued out of order according to In the invention described in claim 4, the number of simultaneous commands transmitted from the command acquisition device to the command decoding device is set to be plural.
Furthermore, using superscalar technology, instructions are issued simultaneously according to available function execution devices. The use of these techniques makes it possible to efficiently use a plurality of function execution devices from a single instruction stream, and is particularly effective when the number of function execution devices is larger than the number of simultaneously operating instruction streams. .

In the present invention, the use status of the function execution device for each instruction stream is checked in advance by software, for example, a compiler. By transmitting this information to the resource allocation control device, the allocation of each function stream of the function execution device in the resource allocation control device is optimized, efficient execution is performed, and the processing is speeded up. Also,
In the invention according to claim 6, the resource allocation control device monitors the instruction issue information from the instruction decoding device to the function execution device for each instruction flow, thereby dynamically detecting the tendency of instruction issue in the instruction flow, The resource allocation control device performs resource allocation in accordance therewith, thereby performing efficient execution and speeding up the processing. By combining these, it becomes possible to preferentially assign a function execution device to a resource allocation suitable for the code or a code whose execution is delayed.

In the function execution device, when an event that must be interrupted occurs, for example, when necessary data cannot be obtained due to a cache miss or the like, the necessary processing is performed by hardware. Until the operation is performed, the function execution device cannot be used. According to the invention of claim 7, when such an event occurs, data necessary for resuming execution is saved in a storage device attached to the function execution device,
The function execution device can be used for executing other instructions, thereby improving the utilization rate of the function execution device.

Further, when a plurality of function execution devices are shared among a plurality of instructions, the number of instruction streams increases, and when the number of instruction decoding devices increases, the function execution devices and temporary storage required for function execution are provided. Since the connection between the devices (registers) and the buffer storage device (cache memory) needs to be realized by a complicated switch, there arises a problem that the number of necessary logic circuits increases . Instruction stream rather than implementing the logic circuit to be able to use all the functions executing apparatus, by limiting the function execution apparatus each instruction stream is available, temporary storage, buffer storage and function execution unit The connection to and from can also be simplified.

Further, by limiting the function execution devices that can use the instruction stream, the resource allocation control device can be distributed and the logic can be simplified.

Hereinafter, the present invention will be described in more detail with reference to the drawings. However, the following disclosure is merely an embodiment of the present invention and does not limit the technical scope of the present invention.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a block diagram showing an embodiment of a processor to which a control method according to the present invention is applied. The processor shown in FIG.
One and two instruction decoding devices 12 and three function execution devices 1
3. It is assumed that it is constituted by the resource allocation control device 14 and is simultaneously executed by three function execution devices 13 which share two instruction streams. The function execution device 13 having the same function or a different function does not affect the subject of the present invention, but here, for convenience, an integer operation unit, a floating point unit, and a load store unit. In this case, the aim is to use the computing unit more efficiently, rather than to speed up the processing. In addition, when an operation is performed by a processor, a temporary storage device (register), a buffer storage device (cache memory), and the like are present, but are not directly related to the first to seventh aspects of the present invention. Therefore, the description is omitted. The two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B.

From the command acquisition device 11 to the command decoding device 12
Is sent to the function execution device 13 from the command decoding device 12. Each of the function execution devices 1 is transmitted from the resource allocation control device 14 to the instruction decoding device 12.
3 is sent. Also, the execution status information is transmitted from the command acquisition device 11, the command decoding device 12, and the function execution device 13 to the resource allocation control device 14.

The instruction acquisition device 11 acquires an instruction from a main storage device (main memory) or a buffer device (cache memory) according to the values of the program counters of the instruction streams A and B. Next, the instruction decoding device 12 receives the instruction content from the instruction acquisition device 11, and, from the resource allocation control device 14, the availability information of each function execution device 13, for example, the instruction flow A is a floating instruction with the integer operation unit. The decimal point unit is available and instruction stream B receives information that the load store unit is available. If the instruction decoding result of the instruction stream A is an integer operation or a floating point operation, the instruction is unconditionally issued to the integer operation unit or the floating point operation unit. If it is a load store instruction,
An interlock occurs in the instruction decoding device 12, and the instruction is not issued until the next cycle. On the contrary, in the case of the instruction stream B,
If the instruction decoding result is an integer operation or a floating-point operation, an interlock is performed. If the instruction is a load store instruction, the instruction is issued. In the next cycle, if an instruction is issued in the previous cycle, the instruction decoding device 12
To receive a new order from. If no instruction has been issued in the previous cycle, no new instruction is received and only the availability information of the function execution device 13 is received. For example,
In this cycle, the instruction stream A can use the load store unit, and the instruction stream B can use the integer operation unit and the floating point unit. Thus, the instruction issuance is determined by comparing the instruction with the usable function execution device 13 as in the previous cycle. The resource allocation control device 14 has a mechanism for equally allocating resources between instruction streams. This is shown in Display 1. Further, it receives execution state information from each of the other devices, and determines whether the next function execution device 13 can be used based on the information.

[0024]

[Table 1]

As a result, a plurality of function execution devices 1
3 can be shared among a plurality of instruction streams, and the function execution device 13 can be effectively used.

Next, the second aspect of the present invention will be described with reference to the drawings. FIG. 3 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 3 includes two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, and three distributed resource allocation control devices 31, and shares two instruction streams. It is assumed that the functions are executed simultaneously by two function execution devices 13. The feature of this embodiment is that the resource allocation control device 14 in the processor according to the first aspect is distributed for each function execution device 13. As a result, the resource allocation control device can be simplified.

Next, a third aspect of the present invention will be described with reference to the drawings. FIG. 4 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 4 has two instruction fetch units / instruction queues 41, 2
One instruction decoding device 12, three function execution devices 13, and a resource allocation control device 14, which are executed simultaneously by three function execution devices 13 sharing two instruction streams. In this embodiment, the instruction acquisition device 11 of the processor according to claim 1 is extended by adding a queue so as to hold a plurality of instructions, and the instruction decoding device 12 receives the plurality of instructions from the instruction acquisition device, and And if there is no dependency between before and after the instruction, or if the dependency can be resolved, and the use permission status of the function execution device obtained from the resource allocation control device 14 indicates that the first instruction cannot be executed and The present invention is characterized in that the instruction is extended to perform out-of-order execution when the next and subsequent instructions are in an executable state.

As in the first aspect, the function execution units 13 are an integer operation unit, a floating point unit, and a load store unit, respectively. Also, two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B,
The command decoding device 12 simultaneously outputs two commands to the command acquisition device /
It is to be received from the instruction queue 41. The instruction acquisition device / instruction queue 41 acquires an instruction from a main storage device (main memory) or a buffer device (cache memory) according to the values of the program counters of the instruction streams A and B. Here, since there is an instruction queue, it is assumed that a plurality of instructions are acquired. Next, the command decoding device 12
The two instruction contents are received from the instruction acquisition device 11, and the individual function execution devices 1 are received from the resource allocation control device 14.
For example, the instruction stream A receives information that the integer operation unit and the floating point unit can be used, and the instruction stream B can use the load store unit. Instruction decoding can be performed on multiple received instructions,
Furthermore, the dependency between instructions is examined. If the first instruction is an instruction operation result of the instruction stream A and the result is an integer operation or a floating-point operation, the instruction is unconditionally issued to the integer operation unit or the floating-point operation unit. If the first instruction is a load / store instruction and the second instruction is an integer operation instruction or a floating-point operation instruction and there is no dependency between the first and second instructions, the second instruction is operated on by integer operation Issued to the unit or floating point unit. If this condition is not satisfied, an interlock occurs in the instruction decoding device 12, and the instruction is not issued until the next cycle. The same is true for the instruction stream B, and the operation in the next cycle is also
The same is repeated.

[0029] In a processor embodiment according to claim 1,
When the first instruction cannot be executed by the function execution device whose use is permitted, the interlock is unconditionally performed. In the processor embodiment in this section, the instruction is issued out of order. The probability of occurrence is reduced, and the throughput and the execution speed of the program are improved.

Next, the invention according to claim 4 will be described with reference to the drawings. FIG. 5 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 5 has two instruction acquisition devices / instruction queues 41, 2
One instruction decoding device 12, three function execution devices 13, and a resource allocation control device 14, which are executed simultaneously by three function execution devices 13 sharing two instruction streams. In this embodiment, the instruction acquisition device 11 of the processor according to claim 1 is extended by adding a queue so as to hold a plurality of instructions, and the instruction decoding device 12 receives the plurality of instructions from the instruction acquisition device 11, and Investigate the relationship, if there is no dependency between before and after the instruction, or if the dependency can be resolved, and if the use permission status obtained from the resource allocation control device 14 indicates that a plurality of function execution devices 13 can be used. The present invention is characterized in that an instruction is issued so as to simultaneously issue instructions to a plurality of function execution devices 13 using superscalar technology.

Similarly to the first aspect, the function execution units 13 are an integer operation unit, a floating point unit, and a load store unit, respectively. Also, two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B,
The command decoding device 12 simultaneously outputs two commands to the command acquisition device /
It is to be received from the instruction queue 41. The instruction acquisition device / instruction queue 41 acquires an instruction from a main storage device (main memory) or a buffer device (cache memory) according to the values of the program counters of the instruction streams A and B.
Here, since there is an instruction queue, it is assumed that a plurality of instructions are acquired. Next, the instruction decoding device 12 receives the two instruction contents from the instruction acquisition device 11, and also, from the resource allocation control device 14, the availability information of each function execution device 13, for example, the instruction flow A is an integer operation unit. The instruction stream B receives information that the load / store unit is available. Instruction decoding is performed on a plurality of received instructions, and the dependence between instructions is also examined. If the first instruction is an integer operation in the instruction decoding result of instruction stream A, the second instruction is a floating-point operation instruction, and 1
If there is no dependency between the second instruction and the second instruction, the first instruction is issued to the integer operation unit, and the second instruction is issued to the floating point operation unit. If the first instruction is a floating-point operation and the second is an integer operation, and there is no dependence between instructions, the first instruction is issued to the floating-point operation unit and the second instruction is issued to the integer operation unit. If this condition is not satisfied, only a single instruction is issued or an interlock state is established, as in the first aspect. This operation is the same for the instruction stream B, and the operation in the next cycle is similarly repeated.

In a processor embodiment according to claim 1,
Even when the resource allocation control device 14 gives permission to use a plurality of function execution devices 13, only one of them is used. However, in the processor embodiment in this section, instructions can be issued simultaneously using superscalar technology. Since the instruction decoding device 12 is expanded, the throughput and the processing speed of executing the program are improved. In particular, the number of frequently used function execution devices 13 is more than the number of instruction streams to be processed in parallel, and the number of rarely used function execution devices 13 is very small. It is possible to improve the utilization rate of the device and further improve the throughput. Further, it is possible to further improve the performance by simultaneously applying the inventions according to the third and fourth aspects.

Next, the invention according to claim 5 will be described with reference to the drawings. FIG. 6 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 6 includes two instruction acquisition units 11, two instruction decoding units 12, three function execution units 13, and a software priority indicating type resource allocation control unit 51, and shares two instruction streams. It is assumed that the functions are executed simultaneously by the three function execution devices 13. In this embodiment, a function is added to the resource allocation control device 14 of the processor according to the present invention so that the function execution device 13 suitable for the instruction flow is given by giving the nature and priority of the instruction flow by software. It is characterized by having done. This priority control is realized by incorporating a priority control instruction into the instruction stream.

As in the first aspect, the function execution units 13 are an integer operation unit, a floating point unit, and a load store unit, respectively. The two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B. Here, in the instruction stream A, if the code does not perform the floating-point operation, a resource allocation instruction instruction that the compiler does not use the floating-point unit is placed at the head of the instruction stream. When this instruction is decoded, information indicating that the use of the floating-point unit is unnecessary for the instruction stream A is transmitted to the resource allocation control device 51. Since then
As long as the setting is not changed, the resource allocation control unit 51 gives the floating point unit only to the instruction stream B. However, if the floating point arithmetic instruction is present in the instruction stream without being assigned, the instruction decoding device 12
It is also possible to select that the resource allocation control device 51 can make a resource allocation request. If the instruction stream B is a high-priority process, an instruction to preferentially allocate resources to the instruction stream B is issued to the resource allocation control device 51 by system software such as an OS. In this case, the resource allocation control device controls the instruction stream A and the instruction stream B so that the use permission of the function execution device 13 is increased in the instruction stream B.

By performing this extension, it becomes possible to allocate resources according to the nature of the instruction flow and the processing status, thereby improving the utilization rate of the function execution device, and improving the throughput and the processing speed of executing the program. Can be.

Next, the invention according to claim 6 will be described with reference to the drawings. FIG. 7 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 7 includes two instruction acquisition devices 11, two instruction decoding devices 12, three function execution devices 13, and a dynamic priority variable resource allocation control device 61, and shares two instruction streams. It is assumed that the functions are executed simultaneously by the three function execution devices 13. In the present embodiment, the assignment of the function execution device 13 is adapted to the instruction flow by monitoring the instruction execution status and the nature of the code in hardware with respect to the resource allocation control device 14 of the processor according to the first aspect. It is characterized by the following.

Similarly to the first aspect, the function execution units 13 are an integer operation unit, a floating point unit, and a load store unit, respectively. The two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B. At the beginning of the execution, the resource allocation management device 61 equally grants the use permission of the function execution device 13 to the instruction stream A and the instruction stream B, similarly to the processor shown in the specific example of claim 1. By monitoring the instruction issuance rate and the interlock occurrence rate of each of the instruction streams A and B to the respective function execution apparatuses 13, the function execution apparatus 13 suitable for each instruction stream is monitored.
Is assigned as much as possible. For example, instruction flow A
In the case of a code in which the floating-point unit is hardly used and the integer operation unit is mainly used, the floating-point unit transmits the resource allocation control from the instruction decoding unit 12 when the instruction is actually executed. By making an assignment request to device 61, a floating point unit will be assigned. On the other hand, if the instruction stream B is a code that mainly uses the load store unit and the floating point unit, the instruction stream B performs control for assigning mainly to this unit.

By performing this extension, it becomes possible to allocate resources according to the nature of the instruction stream and the processing status, thereby improving the utilization rate of the function execution device, and improving the throughput and the execution processing speed of the program. Becomes possible. Further, the efficiency can be further improved by using in combination with the assignment priority control by software according to the fifth aspect.

Next, the invention according to claim 7 will be described with reference to the drawings. FIG. 8 shows an embodiment of a processor to which the control method according to the present invention is applied. The processor shown in FIG. 8 includes two instruction acquisition units 11, two instruction decoding units 12, three function execution units 13, a resource allocation control unit 14, and an execution information save storage unit 71, and shares two instruction streams. Are executed simultaneously by the three function execution devices 13. In this embodiment, the execution information saving device 71 saves execution information to each function execution device 13 of the processor according to claim 1 so as to enable another instruction to be executed first. Is added.

Similarly to the first aspect, the function execution units 13 are an integer operation unit, a floating point unit, and a load store unit, respectively. The two instruction streams that are executed simultaneously are an instruction stream A and an instruction stream B. In the instruction stream A, the load instruction is
From the load store unit. However, when the desired data does not exist in the buffer device (cache memory), the data is transferred from the main storage device having a long delay. Therefore, the instruction interlocks in the load store unit. In this state,
In the case of the first aspect, the load store unit cannot be used until the interlock can be avoided. In the present invention, when such a lock state occurs, the execution information is saved in the execution information save storage device 71, so that the use of the load store unit can be permitted for the instruction stream B. Is what you do.

By performing this extension, even when an interlock occurs, it becomes possible to allocate a function execution device to another instruction stream, thereby improving the utilization rate of the function execution device, and improving the throughput and the program execution. Processing speed can be improved.

Next, a temporary storage device for a limit to the function executing unit 13 that may be used for each instruction stream, function execution prepared for each instruction stream (register) 81
Alternatively, it will be described that the coupling between the buffer storage device and the function execution device 13 can be simplified.

First, FIG. 9 shows an embodiment according to the first aspect. Compared with FIG. 1, a temporary storage device (register) 87 is provided.
Are different from those shown in FIG. 3 in that the number of instruction streams for simultaneous operation is increased to three and the number of function execution devices 13 is increased to six. Next, FIG.
0 is an embodiment of a processor to which the control method according to the present invention is applied. It is characterized in that the resource allocation is limited compared to FIG. In FIG. 10, when the three instruction streams are an instruction stream A, an instruction stream B, and an instruction stream C, respectively, the function execution devices 81 and 86 perform only the instruction streams A and C,
The function execution devices 82 and 83 execute only the instruction streams A and B, and the function execution devices 84 and 85 execute only the instruction streams B and C. Therefore, the connection between the instruction decoding device 12 and the function execution device 13 and the connection between the function execution device 13 and the temporary storage device 87 are simplified. In addition, by providing a restriction on the allocation, the internal structure of the resource allocation control device 14 is also simplified. In addition, by limiting the range of use of the function execution device 13 for each instruction flow between adjacent instructions, the number of intersections between the connections is reduced, which is advantageous in mounting.

This example is particularly effective in a processor having a plurality of function execution devices 13 having the same function. In the case where the degree of integration of the processor is improved and the number of simultaneously operating instruction streams and the number of function execution devices 13 in the processor are increased, the restricted allocation mechanism described in this section makes it possible to simplify the implementation and improve the operating frequency, It is possible to sufficiently compensate for the reduction in the utilization rate due to the restriction on the assignment of the function execution device. Claim 3
By combining the inventions described in claim 4, it is possible to further improve the efficiency.

[0045]

According to the present invention, in an arithmetic device that operates a plurality of instruction streams in parallel, the function execution device, which is the center of the operation, is shared between the instruction streams, so that the function execution device can be effectively used. . Further, in the conventional example, since the function execution device is scheduled after the instruction is decoded, there is a problem that the instruction execution delay is increased and the control is complicated. However, in the method of the present invention, the function is used in advance before the instruction is decoded. Since the possible function execution devices are provided for each instruction stream, the use efficiency of the function execution devices is slightly reduced. However, the advantage that the control frequency is improved and the operating frequency can be improved is more than compensated for by the reduced use efficiency. Becomes Also,
By performing software-based or hardware-based scheduling in accordance with the property of each instruction, it is possible to minimize a decrease in utilization efficiency. Further, when a plurality of instruction streams are executed simultaneously, the resource allocation control device can be simplified by limiting the usable function execution devices in advance. As described above, the method of the arithmetic device for operating a plurality of instruction streams in parallel according to the present invention is very effective for high-speed instruction operation and cost reduction.

[0046]

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a processor for illustrating a control method of the processor according to the present invention.

FIG. 2 is a configuration diagram of an embodiment of an instruction flow sharing method of a conventional function execution device.

FIG. 3 is a configuration diagram of an embodiment using a distributed resource allocation control device.

FIG. 4 is a configuration diagram of an embodiment using an instruction decoding device that issues out-of-order instructions.

FIG. 5 is a configuration diagram of an embodiment using an instruction decoding device that issues instructions at the same time.

FIG. 6 is a configuration diagram of an embodiment using a software priority indicating type resource allocation control device.

FIG. 7 is a configuration diagram of an embodiment using a dynamic priority variable type resource allocation control device.

FIG. 8 is a configuration diagram of an embodiment in which an execution information saving device is added to a function execution device.

FIG. 9 is a configuration diagram of an embodiment equivalent to that of FIG. 1, and newly represents a temporary storage device (register).

FIG. 10 is a configuration diagram of an embodiment in which usable function execution devices are restricted for each instruction flow.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 instruction acquisition device 12 instruction decoding device 13 function execution device 14 resource allocation control device 21 instruction dependency analysis device 22 instruction arbitration device 31 distributed resource allocation control device 41 instruction acquisition device / instruction queue 51 software priority indicating type resource allocation control device 61 Dynamic priority variable type resource allocation control device 71 Execution information save storage device 81-86 Function execution device 87 Temporary storage device (register)

Claims (7)

(57) [Claims] 1. A method for simultaneously executing information processing for a plurality of instruction streams.
A plurality of instruction acquisition devices for extracting instructions from a storage device or the like in an arithmetic device to execute
And instructions fetched from the instruction acquisition device , wherein
Decrypt commands for processing with the function execution device to which permission has been given
And decodes multiple instructions that issue the instruction to the function execution device.
Device and the necessary devices in accordance with the commands issued from the command decoding device.
A plurality of function execution devices for executing functions, a current instruction execution status, the instruction acquisition device, and the instruction decryption.
From the device, the function execution device, and the instruction decoding device
Control the use permission of the function execution device before decoding the instruction
And a resource allocation control device that performs
An arithmetic device. Wherein the resource allocation control device, operation according to claim 1, characterized in that decentralized for each function executing unit
Equipment . 3. The function execution device according to claim 1, wherein the instruction decoding device has no dependency on the available function execution device before and after the instruction, or the dependency can be eliminated, and the function execution obtained from the resource allocation control device. when the use permission status of the device after the second and the first instruction is not executable instruction is ready to run, according to claim 1 or 2, characterized in the row of TURMERIC unordered execution of instructions The arithmetic unit according to item 1 . 4. The apparatus according to claim 1, wherein the instruction decoding device has a function execution device which has no dependency between before and after the instruction or the dependency can be eliminated. when the use permission of the device is obtained, the arithmetic apparatus according to claim 1 or 2, wherein the simultaneous issuance of command line of TURMERIC. 5. The resource allocation control device according to claim 1, wherein
Set more priority grant function executing unit of the instruction stream for each
3. The arithmetic device according to claim 1 , wherein execution of each instruction stream is optimized. Wherein said resource allocation control device checks the information of the instruction issue from the instruction decoding unit to the function executing unit, a resource allocation to a subsequent instruction streams each, characterized in that the optimization based on the information The arithmetic device according to claim 1 or 2 , wherein 7. A storage device for saving one or more pieces of execution information
It was added and the function executing device, when suspends execution event occurs, saves the processed information in the storage device, by transferring saving information to the resource allocation control unit suspends execution event The arithmetic device according to claim 1 or 2 , wherein the function execution device in which the error has occurred is used for information processing according to instructions of another instruction flow .