JPH10207720A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the application efficiency of a hardware resource while attaining the high speed of information processing by optionally switching a scalar mode and a vector mode. SOLUTION: A control unit 30 is provided with an instruction fetch unit 40 for fetching an instruction from a memory unit 20, a sequencer 50 for controlling the operation of the whole information processor and 1st to 3rd multiplexers 60 to 62. The sequencer 50 decodes an instruction INST supplied from the 3rd multiplexer 62. The sequencer 50 switches the scalar mode for executing a scalar instruction by using the 1st and 2nd register sets 11, 12 respectively as scalar register sets and the vector mode for executing a vector instruction by using the 1st and 2nd register sets 11, 12 as two-dimensional vector register sets. The mode switching is dynamically executed in accordance with an event generated during the operation of the information processor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-thread type information processing apparatus.

[0002]

2. Description of the Related Art Conventionally, a multi-threaded pipeline type information processing apparatus having a plurality of threads (instruction streams) has been known. This achieves high-speed information processing using task-level parallelism in an application program. Specifically, each thread has one program counter and one register set composed of a plurality of registers. Moreover, these threads share at least one arithmetic unit. Then, a task is assigned to each of the plurality of threads, and the plurality of tasks are executed in parallel in a time-division manner.

Further, an information processing apparatus of a vector processing system is known. This achieves high-speed information processing by utilizing the parallelism of data in a matrix calculation or the like.

[0004]

Generally, in an information processing apparatus, it is necessary to consider both the parallelism of task level and the parallelism of data.

[0005] Tzi-cker Chiueh, "Multi-Threaded Vecto
rization ", Proceedings of 18th International Sympo
sium on Computer Architecture, pp.352-361, 1991, proposes an information processing apparatus that combines a multithreaded pipeline system and a vector processing system. However, this information processing device has a scalar register set,
And a vector register set independent of this. Therefore, there is a problem that the utilization efficiency of hardware resources is poor.

An object of the present invention is to improve the utilization efficiency of hardware resources in a multi-thread type information processing apparatus into which a vector processing method is introduced.

[0007]

In order to achieve the above object, a multi-thread information processing apparatus according to the present invention comprises:
A scalar mode for executing a scalar instruction using an individual register set of the plurality of register sets as a scalar register set, and N (N is an integer of 2 or more) registers of the plurality of register sets Set N
The mode is switched to a vector mode in which a vector instruction is executed using the source vector register set.

According to the information processing apparatus of the present invention, one register set is assigned to a task that executes only a scalar instruction as a scalar register set. All register sets can be used as scalar register sets. In addition, N register sets are assigned to a task that executes an N-ary vector instruction as an N-ary vector register set.

[0009] Switching between the scalar mode and the vector mode is dynamically performed according to an event that occurs during the operation of the information processing apparatus. For example, switching to vector mode is performed in response to an internal interrupt that occurs when a vector instruction is fetched in scalar mode, and responding to an internal interrupt that occurs when a dedicated interrupt instruction is fetched or decoded in vector mode. Then, switching to the scalar mode is executed.

[0010] The processing of the external interrupt needs to stop and save the thread resources. This includes saving the contents of the register set. Also, there is a situation in which saving thread resources in scalar mode is easier than saving thread resources in vector mode. Therefore, when a thread in the scalar mode and a thread in the vector mode coexist, it is preferable to cause the thread in the scalar mode to execute the external interrupt process preferentially.

[0011]

FIG. 1 shows an example of the configuration of a multithreaded pipeline type information processing apparatus according to the present invention. The information processing apparatus of FIG. 1 is roughly composed of a data path unit 10, a memory unit 20, and a control unit 30. The memory unit 20 stores an instruction sequence configuring each of a plurality of tasks, and data related to each task.

The data path unit 10 includes first and second register sets 11 and 12 each having a plurality of registers (R0, R1, R2,...) And one operation for executing an arithmetic and logic operation. (ALU) 15 and an M register (REG M) 16 for temporarily storing the operation result. The first register set 11 includes one write port WT1 and first and second read ports RD1.
1 and RD12. Second register set 1
2 has one write port WT2 and first and second read ports RD21 and RD22. The arithmetic unit 15 receives a first input from the first read port RD11 of the first register set 11 or the first read port RD21 of the second register set 12, and receives the second input of the first register set 11. Read port RD12 or the second read port RD2 of the second register set 12
2 to receive a second input. The calculation result of the calculator 15 is
The data is temporarily stored in the M register 16 and is supplied from the M register 16 to the memory unit 20 and the control unit 30 as an address ADRS for data access (or branch destination designation), or the write port WT1 of the first register set 11 And to the write port WT2 of the second register set 12. The write port WT1 of the first register set 11 and the write port WT2 of the second register set 12 are:
Data can also be supplied from the memory unit 20. However, both write ports WT1, WT2 are connected to a common data bus.

The control unit 30 includes a memory unit 20
Instruction fetch unit 4 for fetching instructions from
0, a sequencer 50 for controlling the operation of the entire information processing apparatus, and first, second and third multiplexers 6.
0, 61, and 62. The instruction fetch unit 40 includes first and second program counters (PC1, PC1).
PC2) 41, 42 and first and second instruction buffers (IB1, IB2) 45, 46. The first and second program counters 41 and 42 hold the addresses of instructions to be fetched next for the tasks associated with them, and are incremented in accordance with instructions from the sequencer 50, respectively. The first multiplexer 60 selects one of the address supplied from the first program counter 41 and the address supplied from the second program counter 42 in accordance with an instruction from the sequencer 50, and The selected address is supplied to the second multiplexer 61. The second multiplexer 61 receives the address supplied from the first multiplexer 60 and the arithmetic unit 1 in response to an instruction from the sequencer 50.
5 through the M register 16
RS, and supplies the selected address to the memory unit 20. First instruction buffer 4
5 is a first program counter 41 related to the corresponding task
The instruction fetched from the memory unit 20 is temporarily stored in accordance with the holding address of the instruction. Second instruction buffer 46
Temporarily stores the instruction fetched from the memory unit 20 according to the holding address of the second program counter 42 relating to the corresponding task. The first and second instruction buffers 45 and 46 respectively supply the temporarily stored instructions to the third multiplexer 62. Third multiplexer 6
2 selects one of the instruction supplied from the first instruction buffer 45 and the instruction supplied from the second instruction buffer 46 in response to an instruction from the sequencer 50,
The selected instruction is supplied to the sequencer 50. INST in FIG. 1 represents the instruction supplied to the sequencer 50 in this manner. When a plurality of instructions are fetched at a time as employed in many information processing apparatuses, an instruction sequence including the plurality of instructions is stored in an instruction buffer, and the instruction buffer stores the FIFO (first-in・
A first-out operation may be performed to supply the instructions to the third multiplexer 62 one instruction at a time. As a result, the number of instruction fetches can be reduced.

The sequencer 50 decodes the instruction INST supplied from the third multiplexer 62. The sequencer 50 also includes a scalar mode for executing a scalar instruction using each of the first and second register sets 11 and 12 as a scalar register set, and a first and second scalar mode.
Is switched to a vector mode in which a vector instruction is executed by using the register sets 11 and 12 as a binary vector register set. This mode switching is dynamically executed in response to an event that occurs during the operation of the information processing apparatus in FIG. Specifically, switching from the scalar mode to the vector mode is performed in response to an internal interrupt generated when a vector instruction is fetched and decoded in the scalar mode. Switching from the vector mode to the scalar mode is performed in response to an internal interrupt generated when a dedicated interrupt instruction for return in the vector mode is fetched and decoded. In the vector mode, it is possible to execute not only a vector instruction but also a scalar instruction. Further, the sequencer 50 stores information indicating which task is being executed in the current cycle, that is, “task information”. Here, in the scalar mode, the first program counter 41 sets the instruction address related to the specific task 1 to:
It is assumed that the second program counter 42 holds an instruction address related to another specific task 2.
Further, it is assumed that the instruction of task 1 is executed using the first register set 11, and the instruction of task 2 is executed using the second register set 12. In this case, the first program counter 41 and the first register set 11 constitute one thread, and the second program counter 42 and the second register set 12 constitute another thread. Is configured. Alternatively, the task 1 instruction may be executed using the second register set 12 and the task 2 instruction may be executed using the first register set 11. In this case, the first program counter 41 and the second register set 12 constitute one thread, and the second program counter 42
And the first register set 11 constitute another thread. The sequencer 50 also stores information related to such a thread configuration, that is, “thread information”.

The sequencer 50 includes a mode register 51 for storing "mode information" indicating a current operation mode for each thread, an internal interrupt process, and an external interrupt INT.
And an interrupt processing handler 52 for executing the above processing. First and second register sets 11 and 12
Is used as a scalar register set, each of the two threads is in scalar mode. First
When the second register set 11 and the second register set 12 are used as a binary vector register set, one thread is in the main vector mode and the other thread is in the slave vector mode. The mode register 51 is also used for storing the task information and the thread information. According to the task information, thread information, and mode information stored in the mode register 51, the sequencer 50 includes first and second register sets 11 and 12,
It controls the operation of each of the M register 16, the instruction fetch unit 40, and the first, second, and third multiplexers 60, 61, and 62.

FIG. 2 shows a specific example of the pipeline operation in the scalar mode of the information processing apparatus of FIG. Here, the first program counter 41 and the first register set 11 store the instruction sequence (A0, A1, A1
2, A3, A4,...), And the second program counter 42 and the second register set 12 execute the instruction sequence (B0,. It is assumed that a thread 2 is configured. These two threads share the arithmetic unit 15. Instruction A0,
A1, A2, A3, A4 and B0 are all scalar instructions. The two instructions A0 and B0 are load instructions for register indirect addressing. The other four
Each of the instructions A1, A2, A3, and A4 is a register arithmetic operation instruction. Note that the lines other than the instruction INST in FIG. 2 indicate which instruction is the data or address related to the execution of the instruction.

Referring to FIG. 2, in cycle 1, the instruction A0 fetched from the memory unit 20 in accordance with the address supplied from the first program counter 41 is decoded by the sequencer 50. From the result of this decoding, it is recognized that the instruction A0 is a scalar load instruction specifying the register indirect address. Then, the storage addresses of the two designated registers in the first register set 11 are read to the read ports RD11 and RD12.

In cycle 2, the first read port RD
The arithmetic unit 15 performs addition of the address on the address 11 and the address on the second read port RD12, that is, the address calculation according to the instruction A0. The instruction B0 fetched from the memory unit 20 according to the address supplied from the second program counter 42 is decoded by the sequencer 50. From the result of this decoding, it is recognized that the instruction B0 is a scalar load instruction specifying the register indirect address. Then, the storage addresses of the two designated registers in the second register set 12 are read to the read ports RD21 and RD22.

In cycle 3, the result of the address calculation by the arithmetic unit 15 is supplied to the memory unit 20 as an address ADRS for data access according to the load instruction A0. The addition of the address on the first read port RD21 and the address on the second read port RD22, that is, the address calculation related to the instruction B0 is performed by the arithmetic unit 1
5 is performed. Further, according to the address supplied from the first program counter 41, the memory unit 2
The instruction A1 fetched from 0 is decoded by the sequencer 50. From the result of this decoding, the instruction A1
Is a scalar register arithmetic operation instruction. Then, the storage data of the two specified registers in the first register set 11 is stored in the read port RD1.
1, RD12.

In cycle 4, data read from memory unit 20 in response to instruction A0 is supplied to write port WT1 of first register set 11, and the data is designated in first register set 11. Written to a register. Thus, the execution of the instruction A0 is completed.
The result of the address calculation by the arithmetic unit 15 is the address ADR for data access related to the load instruction B0.
S is supplied to the memory unit 20 as S. Furthermore, the first
Arithmetic operation of the data on the read port RD11 of the first instruction and the data on the second read port RD12, that is, the instruction A1
Is executed by the arithmetic unit 15.
Further, the instruction A2 fetched from the memory unit 20 according to the address supplied from the first program counter 41 is decoded by the sequencer 50. From the decoding result, it is recognized that the instruction A2 is a scalar register arithmetic operation instruction. And the first
The stored data of the two designated registers in the register set 11 is read out to the read ports RD11 and RD12.

In cycle 5, the data read from the memory unit 20 in response to the instruction B0 is supplied to the write port WT2 of the second register set 12, and the data is designated in the second register set 12. Written to a register. At this time, a data bus is used for data transfer from the memory unit 20 to the second register set 12. Therefore, the result of the operation by the operation unit 15, that is, the result of the scalar arithmetic operation according to the instruction A1 is temporarily stored in the M register 16. Also, the first
Arithmetic operation on the data on the read port RD11 and the data on the second read port RD12, that is, the instruction A2
Is executed by the arithmetic unit 15.
Further, the instruction A3 fetched from the memory unit 20 according to the address supplied from the first program counter 41 is decoded by the sequencer 50. From the result of this decoding, it is recognized that the instruction A3 is a scalar register arithmetic operation instruction. Then, the storage data of the two designated registers in the first register set 11 is read to the read ports RD11 and RD12.

In cycle 6, the operation result temporarily stored in the M register 16, that is, the result of the scalar arithmetic operation related to the instruction A1, is supplied to the write port WT1 of the first register set 11, and the result is stored in the first register set WT1. The data is written to the designated register in the register set 11. The result of the scalar arithmetic operation related to the instruction A2 is stored in the M register 16
Is temporarily stored. Further, the first read port RD11
The arithmetic operation of the above data and the data on the second read port RD12, that is, the scalar arithmetic operation related to the instruction A3 is executed by the arithmetic unit 15. Furthermore, the instruction A4 fetched from the memory unit 20 according to the address supplied from the first program counter 41 is decoded by the sequencer 50. From the decoding result, it is recognized that the instruction A4 is a scalar register arithmetic operation instruction. Then, the storage data of the two designated registers in the first register set 11 is read to the read ports RD11 and RD12.

As described above, in the scalar mode, each of the first and second register sets 11 and 12 is used as a scalar register set. Then, the scalar instruction sequence of task 1 and the scalar instruction sequence of task 2 are executed in parallel by a multi-thread pipeline method.

FIG. 3 shows an example of processing for shifting from the scalar mode to the vector mode in the information processing apparatus of FIG. It is assumed that the thread 1 executes the instruction sequence of the task 1 and the thread 2 executes the instruction sequence of the task 2 in the scalar mode. At this time, when a vector instruction is fetched from the memory unit 20 according to the address supplied from the first program counter 41 constituting a part of the thread 1, and the fetched vector instruction is decoded by the sequencer 50, , An internal interrupt occurs in the sequencer 50. The interrupt handler 52 checks the cause of the interrupt and confirms in step S1 that a vector instruction interrupt has occurred in the thread 1, and then proceeds to step S3.
Then, the process proceeds to S4. In step S3, the execution of the task 2 assigned to the thread 2 is stopped, and the resources of the thread 2 (the contents stored in the second register set 12)
Is evacuated. In step S4, the interrupt processing handler 52 sets the thread 1 to the main vector mode,
To the slave vector mode. After the contents stored in the mode register 51 are updated in response to this, the process returns to the execution of the task 1. When a vector instruction interrupt occurs in the thread 2, in step S2,
The thread 1 stops and saves resources, the thread 2 shifts to the main vector mode, and the thread 1 shifts to the slave vector mode.

FIG. 4 shows an example of a pipeline operation in the vector mode of the information processing apparatus of FIG. Here, the thread 1 composed of the first program counter 41 and the first register set 11 is in the main vector mode, and the thread 2 composed of the second program counter 42 and the second register set 12 Is a slave vector mode. Then, it is assumed that the threads 1 and 2 execute the vector instruction sequence (V0, V1, V2,...) Of the task 1. The instruction V0 is a load instruction specifying a register indirect address, and the instructions V1 and V2 are register addition instructions.

Referring to FIG. 4, the execution procedure of the load instruction V0 is as follows. That is, in cycle 1, the first
Instruction V0 fetched from memory unit 20 according to the address supplied from program counter 41 of
Are decoded by the sequencer 50. From the result of this decoding, it is recognized that the instruction V0 is a vector load instruction specifying a register indirect address. And
The storage addresses of the two specified registers Ri and Rj in the first register set 11 are stored in the read port RD1.
1, RD12. In cycle 2, addition of the address on the first read port RD11 and the address on the second read port RD12, that is, the address calculation of the first vector element D0 according to the instruction V0 (Ri + Rj)
Is executed by the arithmetic unit 15. In cycle 3, the result of the address calculation (Ri + Rj) by the arithmetic unit 15 is supplied to the memory unit 20 as the address ADRS for the first data access according to the load instruction V0.
In the cycle 3, the address calculation (Ri + Rj + a) of the second vector element D1 related to the instruction V0 is performed by the arithmetic unit 15
Is executed by In cycle 4, memory unit 2
0 is supplied to the write port WT1 of the first register set 11, and the first vector element D0 read from
The vector element D0 is written to the designated register Rk in the first register set 11. Cycle 4
Then, the address calculation (Ri + Rj +
The result of a) is the memory unit 2 as the address ADRS for the second data access according to the load instruction V0.
0. Then, in cycle 5, the second vector element D1 read from the memory unit 20 is supplied to the write port WT2 of the second register set 12, and
The second vector element D1 is written to a designated register Rk in the second register set 12. With the above operation, the execution of the vector load instruction V0 is completed. As a result, a binary vector composed of the first vector element D0 and the second vector element D1 is stored in the first register set 1
It is stored in a specified binary vector register Rk in a binary vector register set composed of the first and second register sets 12.

The execution procedure of the addition instruction V1 is as follows. That is, in cycle 3, the instruction V1 fetched from the memory unit 20 according to the address supplied from the first program counter 41 is transmitted to the sequencer 50.
Is decoded by From the result of this decoding, it is recognized that the instruction V1 is a vector register addition instruction. Then, the storage data of the two designated registers R0 and R1 in the first register set 11 is read to the read ports RD11 and RD12. In cycle 4, the arithmetic unit 15 performs addition of the data on the first read port RD11 and the data on the second read port RD12, that is, the addition (R0 + R1) of the first vector element according to the instruction V1. In the cycle 4, the data stored in the two specified registers R0 and R1 in the second register set 12 are stored in the read ports RD21 and RD21.
Read to RD22. In cycle 5, the result of the addition by the arithmetic unit 15, that is, the result of the addition (R0 + R1) of the first vector element according to the instruction V1, is temporarily stored in the M register 16. In the cycle 5, the data on the first read port RD21 and the second read port RD2
The arithmetic unit 15 performs the addition with the data on the second 2, that is, the addition (R0 + R1) of the second vector element according to the instruction V1. In cycle 6, the addition result temporarily stored in the M register 16, that is, the result of the addition (R0 + R1) of the first vector element according to the instruction V1, is supplied to the write port WT1 of the first register set 11, and the result is Specified register R in the first register set 11
Written to 0. In the cycle 6, the result of the addition by the computing unit 15, that is, the result of the addition (R0 + R1) of the second vector element according to the instruction V1 is temporarily stored in the M register 16. Then, in cycle 7, the addition result temporarily stored in M register 16, that is, instruction V1
Is supplied to the write port WT2 of the second register set 12, and the result is written to the designated register R0 in the second register set 12. With the above operation, the execution of the vector register addition instruction V1 is completed. As a result, the sum of the storage contents of the specified two vector registers R0 and R1 in the binary vector register set composed of the first register set 11 and the second register set 12 is specified. It is stored in the vector register R0. FIG. 4 shows the next vector register addition instruction V
2 shows that the storage data of the two designated registers Rx and Ry in the first register set 11 are read out to the read ports RD11 and RD12 in the execution process of No. 2.

As described above, in the scalar mode, each of the first and second register sets 11 and 12 is used as a scalar register set, whereas in the vector mode, the first and second register sets 11 and 12 are used. Used as a binary vector register set. In other words, the first and second register sets 11 and 12 are automatically allocated to the task of executing the binary vector instruction as a binary vector register set, so that efficient use of hardware resources is achieved.

Now, while the threads 1 and 2 are executing the instruction sequence of the task 1 in the vector mode, a dedicated interrupt instruction for returning to the scalar mode from the memory unit 20 is fetched, and the fetched dedicated instruction is issued. When the interrupt instruction is decoded by the sequencer 50, an internal interrupt occurs in the sequencer 50. Upon confirming that the dedicated interrupt instruction for returning to the scalar mode has been fetched, the interrupt processing handler 52 checks the threads 1 and 2
To the scalar mode. In response,
The content stored in the mode register 51 is updated. In the thread 2 that was in the slave vector mode, the second
After the storage contents of the register set 12 are restored, the execution is resumed from the return address of the task 2. In the thread 1 in the main vector mode, the task 1 is continuously executed.

As described above, according to the information processing apparatus of FIG. 1, the mode is dynamically switched in accordance with the type of the instruction fetched during the operation. Adaptive hardware resource utilization is achieved.

FIG. 5 shows another example of the configuration of a multithread pipeline type information processing apparatus according to the present invention. In the information processing apparatus of FIG. 5, the number of threads is expanded to three. In FIG. 5, the data path unit 10 includes:
First and second register sets 11 and 12 and a computing unit 1
5, a third register set 13 having a plurality of registers (R0, R1, R2,...) In addition to the M register 16 and the M register 16. The third register set 13 includes 1
It has two write ports WT3 and first and second read ports RD31 and RD32. The instruction fetch unit 40 shown in FIG. 5 includes first and second program counters 41 and 42 and first and second instruction buffers 4 and 4.
5 and 46, and a third program counter (PC
3) 43, and a third instruction buffer (IB3) 47. Other configurations in FIG. 5 are the same as those in FIG.

In the information processing apparatus shown in FIG. 5, a scalar mode for executing a scalar instruction using each of the first, second and third register sets 11, 12, and 13 as a scalar register set is provided. 2nd and 3rd register set 1
A vector mode in which two vector sets among 1, 12, and 13 are used as a binary vector register set to execute a vector instruction is switched. That is, it is possible to simultaneously process one task that executes a vector instruction and another task that executes only a scalar instruction.

FIGS. 6 to 8 show an example of the process of shifting from the scalar mode to the vector mode in the information processing apparatus of FIG. Here, it is assumed that the thread 1 executes the instruction sequence of the task 1, the thread 2 executes the instruction sequence of the task 2, and the thread 3 executes the instruction sequence of the task 3 in the scalar mode. At this time, when a vector instruction is fetched from the memory unit 20 according to the address supplied from the first program counter 41 constituting a part of the thread 1, and the fetched vector instruction is decoded by the sequencer 50, , An internal interrupt occurs in the sequencer 50. The interrupt handler 52 is configured as shown in FIG.
As shown in (2), when the cause of the interrupt is checked to confirm that the vector instruction interrupt has occurred in the thread 1 in step S11, and that the thread 2 is in the scalar mode is confirmed in step S13 from the storage contents of the mode register 51, The process proceeds to steps S14 and S15. In step S14, the execution of the task 2 assigned to the thread 2 is stopped, and the resources of the thread 2 (the contents stored in the second register set 12) are saved. Step S15
Then, the interrupt handler 52 shifts the thread 1 to the main vector mode and the thread 2 to the slave vector mode. After the contents stored in the mode register 51 are updated in response to this, the process returns to the execution of the task 1. At this time, the thread 3 maintains the scalar mode. Therefore, the processing of task 3 is continued. When a vector instruction interrupt occurs in the thread 2 or 3, an interrupt accepting process corresponding to each case is executed in step S12.

When a vector instruction interrupt has occurred in the thread 1 and the threads 2 and 3 have already shifted to the vector mode, the interrupt processing handler 52 proceeds from step S13 in FIG. 6 to step S13 in FIG. The process proceeds to step S21. Here, even if the threads 2 and 3 are in the vector mode, if it is confirmed in steps S21 to S23 that the thread 1 has a higher priority than the thread in the main vector mode among the threads 2 and 3, The interrupt handler 52 proceeds to steps S24 to S29. As a result, the thread 2 and the thread 3 are released from the vector mode, and the thread 1 shifts to the master vector mode and the thread 2 shifts to the slave vector mode. At this time, if there is a waiting task in the scalar mode, the waiting task is assigned to the thread 3. Threads 2 and 3
Thread 1 than thread in main vector mode
Do not have a high priority in steps S21 and S2.
When confirmed in step 3, the interrupt processing handler 52 advances the processing to steps S31 to S34 in FIG. 8 so as to wait for the transition of the thread 1 to the main vector mode. At this time, if there is a waiting task in the scalar mode, the waiting task is assigned to the thread 1.

Returning from the vector mode to the scalar mode in the information processing apparatus shown in FIG. 5 is the same as that in the case shown in FIG.

FIG. 9 shows an example of a process of accepting an external interrupt INT in the information processing apparatus of FIG. The processing of the external interrupt INT requires stopping and saving the thread resources. There is a situation in which saving thread resources in scalar mode is easier than saving thread resources in vector mode. Therefore, the interrupt handler 52
Causes the thread in the scalar mode to execute the external interrupt process preferentially in accordance with steps S41 to S45 in FIG. As a result, it is possible to reduce opportunities to interrupt the task in the vector mode.

The extension to the information processing apparatus having four or more threads will be apparent from FIG. In general, a scalar mode in which a scalar instruction is executed by using an individual register set among a plurality of register sets as a scalar register set, and a scalar mode of N (where N is 2 or more) among the plurality of register sets Is switched to a vector mode in which a vector instruction is executed by using the register set of (i.

When a call instruction (CALL instruction) for a function including a vector instruction is executed in the scalar mode, the mode is switched to the vector mode, and in the vector mode, a return instruction to a function not including the vector instruction (RETUEN) is issued.
(Instruction), the mode may be switched to the scalar mode. In addition, the operating system has information indicating whether or not the task assigned to each of the plurality of threads is a task for executing a vector instruction. If the execution task is a task that executes a vector instruction, the mode is switched to the vector mode, and if the next execution task is a task that does not execute the vector instruction, the mode is switched to the scalar mode.

[0039]

As described above, according to the multi-thread information processing apparatus according to the present invention, a mode in which a plurality of register sets are individually used as scalar register sets, and N modes (N is (2 or more integers) register set can be freely switched to a mode in which the register set is used as a vector register set, so that the speed of information processing can be increased by adapting to program characteristics such as the presence or absence of matrix operation. In addition, the utilization efficiency of hardware resources can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to the present invention.

FIG. 2 is a timing chart illustrating an operation example of the information processing apparatus in FIG. 1 in a scalar mode.

FIG. 3 is a flowchart illustrating an example of a transition process from a scalar mode to a vector mode in the information processing apparatus in FIG. 1;

FIG. 4 is a timing chart illustrating an operation example of the information processing apparatus of FIG. 1 in a vector mode.

FIG. 5 is a block diagram illustrating another configuration example of the information processing apparatus according to the present invention.

FIG. 6 is a flowchart illustrating an example of a transition process from a scalar mode to a vector mode in the information processing apparatus of FIG. 5;

FIG. 7 is a flowchart illustrating an example of processing subsequent to FIG. 6;

FIG. 8 is a flowchart illustrating an example of processing subsequent to FIG. 7;

9 is a flowchart illustrating an example of an external interrupt acceptance process in the information processing apparatus of FIG. 5;

[Explanation of symbols]

 Reference Signs List 10 data path unit 11, 12, 13 register set 15 arithmetic unit (operation unit) 16 M register 20 memory unit 30 control unit (control unit) 40 instruction fetch unit 41, 42, 43 program counter 45, 46, 47 instruction buffer 50 Sequencer 51 Mode register 52 Interrupt handler 60, 61, 62 Multiplexer

Claims (6)

[Claims] 1. A multi-thread type information processing apparatus, comprising: a plurality of register sets each having a plurality of registers, each of which belongs to one thread, and shared by the plurality of threads. Computing means for performing an operation based on data supplied from the plurality of register sets; and a scalar instruction using each of the plurality of register sets as a scalar register set. A scalar mode to be executed and a vector mode to execute a vector instruction by using N (N is an integer of 2 or more) register sets of the plurality of register sets as an N-ary vector register set. Information processing apparatus, comprising: a control unit for controlling the plurality of register sets and the arithmetic unit. Place. 2. The information processing apparatus according to claim 1, wherein the control unit dynamically switches to one of the scalar mode and the vector mode in response to an event occurring during operation of the information processing apparatus. An information processing apparatus having a function of switching to an information processing device. 3. The information processing apparatus according to claim 1, wherein said control means switches to said vector mode in response to an internal interrupt generated when a vector instruction is fetched in said scalar mode, and said vector mode. An information processing apparatus having a function of switching to the scalar mode in response to an internal interrupt generated when a dedicated interrupt instruction is fetched or decoded. 4. The information processing apparatus according to claim 1, wherein said control means switches to said vector mode when a call instruction of a function including a vector instruction is executed in said scalar mode, and said vector means in said vector mode. An information processing apparatus having a function of switching to the scalar mode when a return instruction to a function not including an instruction is executed. 5. The information processing apparatus according to claim 1, wherein the control unit responds to information indicating whether a task assigned to each of the plurality of threads is a task for executing a vector instruction. When the task is switched, if the next execution task is a task that executes a vector instruction, the task is switched to the vector mode, and if the next execution task is a task that does not execute a vector instruction, the function is switched to the scalar mode. An information processing apparatus characterized by the above-mentioned. 6. The information processing apparatus according to claim 1, wherein the control unit has a function of causing a thread in a scalar mode among the plurality of threads to execute an external interrupt process with priority. Information processing device.