WO1998013759A1 - Data processor and data processing system - Google Patents

Data processor and data processing system

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Publication number
WO1998013759A1
WO1998013759A1 PCT/JP1996/002819 JP9602819W WO9813759A1 WO 1998013759 A1 WO1998013759 A1 WO 1998013759A1 JP 9602819 W JP9602819 W JP 9602819W WO 9813759 A1 WO9813759 A1 WO 9813759A1
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WO
Grant status
Application
Patent type
Prior art keywords
instruction
evening
execution
instructions
task
Prior art date
Application number
PCT/JP1996/002819
Other languages
French (fr)
Japanese (ja)
Inventor
Shigezumi Matsui
Susumu Kaneko
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/461Saving or restoring of program or task context
    • G06F9/462Saving or restoring of program or task context with multiple register sets

Abstract

A data processor (1) in which an instruction fetching unit (10) fetches an instruction, an instruction decoder (12) interprets the instruction latched in an instruction register (11), and an instruction executing unit (13) executes the instruction based on the results of interpretation by the decoder (12). One of task buffers (16 and 17) each provided with a program storing area (160 and 170) and a pointer (161 and 171) for successively reading out instructions stored in the areas (160 and 170) or the unit (10) is selected through a selector (18). The selection by the selector (18) is controlled by a switching control means (19) in accordance with an internally or externally generated event. Register means (S1 and S2) used exclusively for the task buffers (16 and 17) are provided in the instruction executing unit (13) so as to make the saving of the internal state of the unit (13) unnecessary when the task is switched by selecting a program stored in one task buffer from the outside. Therefore, the speed of switching the task is improved and the burden of the data processor (1) at the time of switching the task is reduced.

Description

Bright thin sheet data processor and data processing system

Technical field

The present invention relates to a data processor, further applies relates Mar Chitasukingu or task switching technology in a data processor, such as a plurality of tasks pipeline processed data Bro processor, and a data processing system employing the Detapurose Tsu Sa Te is also the technique effective. BACKGROUND

There are pipeline processing as a technique to speed up data processing by de Isseki processor. Pipelining, by dividing one large processing to a plurality of processing elements, performing a one after another new processed in time or pipeline pitch required for each processing element, which improves the throughput of the data processing it is. For example, the control process for executing one instruction, and instruction fetch, instruction decode, operation, if divided into the processes of memory access and register evening scan Ta, the processing of the respective one of the pipeline stages, one one of the performing instruction Fuetsuchi every Pidzuchi (pipeline bits h) of Pas Eve Rain stage, apparently, and then execute one instruction in one pipeline Npitchi.

In the course of such pipeline processing, when performing task switching is later to allow return to the currently executing task, the program counter, stack space values ​​such as status register evening and de Isseki Regis evening not have to perform the process of regression avoid to. However, since it takes no small time for such evacuation process, thus causing disturbance to the pipeline. In particular, when performing a complicated process, evening be viewed locally disk switching is Rukoto frequently may arise from the program execution state. As a result, even if adopted much trouble Paiburain processing, it is not possible to improve the throughput of de Isseki processed as I think. In Japanese 閧昭 6 2 2 3 7 5 3 1 JP, when running in a time division multiple programs, because the process becomes complicated in the interrupt, providing a program R 0 M and program counter evening 2 pairs , ROM accesses evening shifted Lee timing in each set, alternating selector selects the output of the ROM to as providing instructions to the instruction register scan evening, this Yotsute, executed by simply time division multiple programs it way art is shown.

This is a technique for performing a time completely divide the program is switched alternately program quasi based on the clock signal, the apparent multiple programs, and simply assume that you want to run in parallel , no consideration is given to switch the evening disk in response to a specific I vent occurs in and out of de Isseki processor. Considering it also reduced the de Isseki processor for generic use in such device control, to reduce the disturbance or the like of the pipeline on the occasion to task switching, it is required to improve the throughput.

Also, de Isseki processor scan one pass color architecture can run concurrently a plurality of instructions by a plurality of pipelines. In such a de Isseki processor, an instruction has to manage a dependency instruction mutual interrogation represented by the data conflicting Bok conditions such as that as to take advantage of the result of executing other instructions. If that cheat de one Takonfuriku preparative the instruction to be executed in parallel ^ revealed, become a part of the plurality of pipeline to stop instruction execution completion of the other instruction execution and willing to wait. With this taken into consideration to use a pipeline vacated by de Isseki Konfuriku bets for the execution of another task, again, such minimal disturbance of the pipeline by shortening the processing time associated with the e task switching it has been revealed by the present inventors should Re.

Further, Isseki de processor may be mounted a key Yasshumemori to speed up operand access. When the Kiyadzushi Yurain of cache memory can be replaced-out harm, also must write conversion Erare the contents of the memory that is associated with it. For example if only the data processor has occupied a main memory, only the pre-Symbol rewritten content it is only necessary to reflect the main memory when the replacement of the cache line is performed. Such an operation is referred to as a line Bokuno Seok.

However, de externally connected DMA (Direct Memory Access) Con Bok rollers Isseki processor, a Isseki erroneous de rewriting of the cache memory is not reflected in the main memory is read from the main memory de Isseki there is a possibility that perform transfer the. Referred to such a possibility and cache-Kohi one Renshi problems, in order to solve this problem, even Kiyasshuhi' bets during Memorirai Bok operation, to employ a write-through system in which in each case Memorirai preparative operation wire carrier Sshumemori together it can be a non-flop locking configure Kiyadzushume memory using rye concert Ffa. However, because of Kiyadzushi Interview-Kohi one Renshi, when Memorirai Bok operation occurs frequently, Detapu port processor has run out of bus de Isseki transfer capability for connecting DMA con Bok roller and the main memory for Kiyadzushu 'coherency put away, when performing high-speed data transfer by the DMA controller one la, resulting in a problem that the data transfer rate is limited.

Accordingly, without adopting a write-through cache in write-back mode - for maintaining coherency to detect an action that does not keep a cache coherency, it is possible to adopt a technique of writeback at that time. For example, the data processor, the DMA controller detects an operation of read access to data stored in the cache memory (bus snoop), by interrupting the operation of write-back the de Isseki, the later, DMA transfers to enable the. However, the data processor will increase the burden for detecting an operation does not keep a cache coherency.

An object of the present invention can reduce the processing associated with task switching, Ru near to provide a de-Isseki processor capable of improving the data throughput.

Another subject of the present invention is to provide a de-Isseki processor capable of suppressing the disturbance of the pipeline to a minimum during task switching. Still another object of the present invention is to so in de Isseki processor superscalar architecture can be effectively used by switching the pipeline vacated by de Isseki Konfuriku Bok the execution of another task. Other objects of the present invention, when a built-in Kiyadzushumemori Lai Tobadzuku method in bets that provides a data processor capable of minimizing the burden for keep the caches' Kohi one Renshi during DMA transfers .

The above and other Π manner and novel features of the present invention will be apparent from the following description of this specification. Disclosure of the Invention

In the present invention, as illustrated in FIG. 1, instruction fetches Fuetsuchuni' bets (1 0) instruction, the instruction register evening (1 1) that was latched instruction to the instruction decoder (1 2) decodes , a data processor instruction execution unit (1 3) executes an instruction based on the decoded results (1), the program storage area (1 6 0, 1 7 0) and the instruction sequence stored in the area evening Boyne for reading and (1 6 1 1 7 1) and a plurality of task Kubadzufa (1 6, 1 7) which are respectively provided with, is dedicated the respective evening every disk buffer, said instruction run Yuni' me arranged register means (S 1, S 2) and said plurality of Tasukubadzufa from among the instruction Fuetsuchunidzu Bok - selector for connecting one to the selectively the instruction register evening (1 8) When the instruction to the selector in an initial state Co When to select Etsuchuni' bets, internal or an elective Gosuru switching control means said selector evening according Iben bets that are generated externally (1 9), wherein the plurality and based on the control of the instruction execution Yuni' Bok interface means for external and fin evening face to de Isseki write "J ability of all or part of the task buffers (2 1, BUS) and a.

The task buffers each have a unique Poin evening, follow from the instruction execution Yuni' metropolitan 冇 specific registers evening means assigned to the task buffer each to be executed task instruction Fuwetsuchuni' bets Program ivy when the normal switched between the swap evening risk processing in accordance with the program instruction processing and task buffer, saving or restoring the normal instruction processing execution state to be interrupted (for example, a program counter and general-purpose registers evening values) It does not require a process to access the stack area of ​​the external memory in order to or. Thus, a high-speed task switching, and the reduction in wake intends processing task switching is achieved, which contributes to the data processing capacity improvement of a data processor.

It said instruction register evening, instruction decoder and the instruction execution Yuni' Doo is, when performing a pipeline processing instructions proceeds with Paibura Insuteji units, the above, the disturbance of the pipeline can be minimized. The instruction execution Yuni' DOO said instructions and output registers finger 示信 No. for latching instructions to evening the (LIR), the selector subjected the instruction signal to the instruction Fuwetsuchuni' Bok or tasks buffer the switching example control means selects feeding to the instruction Fuedzuchu Knitting DOO updates based to be supplied instruction into the instruction register evening on the finger 示信 No., the task buffer can be updated on the basis of the Boyne evening on the finger 示信 No.. This control facilitates the Boyne evening control of the Tasukuba' file.

Examples Method return from Suwapputasuku processing to the normal instruction processing, pre-Symbol switching control means the switching control means based on the decoded result of the instruction is supplied to the instruction decoder from the selected task buffer before said selector ^ instruction Fetsuchuni' it back to the selected state of the divination. That is, when considering that to complete than connexion completion of Suwapputasuku processing Barre selected, the Suwapputasuku process of returning to normal instruction processing priority, as illustrated in FIG. 1, the switching control means, wherein in response to selection of the task buffers, may output an interrupt disable signal to disable the interrupt signal to be input to the instruction execution Yuni' Bok (INH). Thus, the interrupt request is not accepted during the scan Wa Pputasuku process.

If allowing the interrupt acceptance, such as the data processor illustrated in the first 2 Fig (1 A), said switching control means (1 9) selects the task Roh couch (1 6, 1 7) when is the conjunction return before Symbol selector by a control signal ICNT to by the instruction execution Yunidzu Doo (1 3) is corresponding to the received interrupt (1 8) in the selected state of the instruction Fuetsuchuni' Bok, selection of the previous task buffer state it is sufficient to retreat.

Data processor (1) is de in question and the instruction execution Yuni' Doo and external - evening can comprise the cache memory (1 5). The de Isseki processor, as illustrated in the second 0 Figure, that make up a plurality of connected data processing system to the peripheral circuit (2, 5) such as a memory through a bus (4). In this case, the Ku to task buffer Wakashi DMA transfer control program if you set the DMA transfer and de Isseki conversion control program, it is possible to mitigate the burden on the data processor for solve the problem of Kiyasshi Yukohirenshi. That is, in a state in which processing tasks de Isseki Purosedzusa is switched to the DMA transfer control process via the selector or the like, functions as a DMA controller will be run Yunidzu I realized. Accordance connexion, between the data processor external memory or when controlling the DMA de Isseki transferred between external memory and an external input and output circuit, always the data cache memory address signals or the access control information for the DMA transfer control It will be passing through. In other words, when the cache memory is employed Reye concert click method, even if the DMA transfer is started in a state where the de Isseki rewriting of the cache memory is not reflected in the external memory, such external memory not reflected data is read from the de Isseki key Yasshu memory instruction execution Yuni' me, it will be transferred. Thus, de Isseki Purosedzusa is key Yasshu when it detects detects the DMA transfer operation is not maintained the coherency without requiring making rope rows pre Ji fit writeback operation, DMA fc that does not keep a cache coherency it is possible to reduce the processing load of the data processor of detecting feeding operation. In course de Isseki DMA transfer control function realized by the processor, the transfer data will be temporarily loaded into a data processor.

It said task switching means is also applicable to super scalar format of a data processor (1 B, 1 C) illustrated in the first 4 view and the first 6 FIG. Chi words, the instruction register evening (1 1 A, 1 1 B) the instruction that latched in the instruction decoder (1 2 A, 1 2 B) is decoded by the instruction execution Yuni' Doo (1 3 A, 1 3 B) is the instruction execution control sequence for executing the instruction with multiple series comprises, includes instructions Fetsuchuni' you want to Fetsuchi instructions (1 0), the multiple instruction multiple instruction execution control sequence in parallel executable de Isseki processor ( 1 B, 1 C), the storage area of ​​the program and the plurality of tasks buffer and a pointer for to sequentially read out the instruction stored in the area each with (1 6, 1 7), wherein each of the tasks dedicated to the respective buffer, certain of said instruction execution Gyoyu two, first and Regis evening means disposed on Seo Bok (S 1, S 2), from among the plurality of tasks buffer and instruction fetch unit corresponding to the previous Symbol particular instruction execution Yuni' Bok select the One A selector for SeMMitsuru the instruction register evening (1 8) which, together with to select the instruction Fuwetsuchu Stevenage Bok to said selector in an initial state, the selection control the Te 従Tsu to Iben Bok generated internally or externally selector and a switching control means (1 9) to. Also in the data processor of this, since it is switched to the normal instruction processing and swap task processing by using one of the instruction execution control system, the same, and a ^ 担軽 decrease the data processor due to speed and switching tasks in the task switching achievement can also therefore c disturbance of the pipeline can be minimized, it is possible to ensure a high de Ichitasho physical ability superscalar architecture contemplates naturally.

A plurality of instructions Te parallel executable scan one path forces Rade evening processor odor, place to thus arbitration hardware instructions mutual dependencies, such as data conflicting Bok ^, contained in the respective instruction execution control sequence instructions based on the instruction decoding results from Deco over da, whether capable of parallel execution of instructions by mutually different instruction execution control sequence examined dependencies between these instructions each other, depending on the result of execution of other instructions delaying 突行 instructions will be provided with a contention ¾ physical Yunidzu preparative (2 5) to.

At this time, the switching control means, as an example in the first 6 FIG, when said contention management Yuni' taken by such de Isseki Konfuriku preparative delay the execution of a particular instruction, the control signal 2 5 for notifying it by selecting the task buffer to said response cell Rectifiers evening (1 8) to 0, it is possible to switch processing the normal instruction processing by one of the instruction execution control system or Paibu interrupted to scan Wappu evening disk process , it is possible to effectively utilize the instruction execution control sequence. Especially when the task switching as described above, the middle do not require the saving of the execution state of the normal command processing is interrupted, the Suwappu evening disk process also performed efficiently task switching if a short idle time of the instruction execution control sequence it is possible to move to.

Competitive state of the data conflicting Bok such contention management Yuni' Bok (2 5) is determined on the basis of the instruction Decorating one de result, then, is base Ki instruction processing is delayed already finished decoding. Thereafter, although switched to swap task processing, and normal instruction processing process is interrupted, if the the Suwapputasuku processing treatment begins Alternatively using the same instruction register evening and decrees decoder to each other, the as illustrated in 1 7 Fig pipe

The same instruction as the instruction Fuetchi pipeline stage m (I n) in 1 was Fuetchi again stage m + 2 of the pipe 1, the same instruction as the pipeline stage m + 1 instruction Decorating one de in pipe 1 (D n) the must be decoded again in stage m + 3 of the pipe 1, so that the pipeline is disturbed in this sense. Thus, after the swap task processing, it must be re-opened from the instruction Fuetsuchi when the operation returns to the normal instruction process is interrupted.

In switching from the normal instruction processing by de one Takonfuriku preparative above to Suwapputasuku processing document, to prevent occur at all disturbed pipeline, as exemplified in the first 8 Figure, de Isseki processor (1 D) is the one of the instruction execution control system, swap task processing dedicated instruction register (1

1 C) and an instruction may be added to the decoder (1 2 C). That is, the instruction Les Soo evening (1 1 A, 1 1 B) instruction instruction decoder (1 2 A, 1 2 B) latched to and decoded by the instruction execution Yuni' Doo (1 3 A, 1 3 B) instruction with a comprising a plurality of sequences of instruction execution control sequence to be executed, include instruction Fetchuni' preparative (1 0) to Fuetsuchi instructions, and assume that are executable in parallel a plurality of instructions in said plurality of instruction execution control sequence to. Then, the data evening processor (1 D), the storage area of ​​the program and a plurality of taskbar Ffa of the Boyne evening for out sequentially read the instructions stored in that region each comprising (1 6, 1 7) , the plurality of dedicated the particular task for instruction register evening in task buffer (1 1 C) and the specific tasks river instruction register certain tasks for the instruction decoder for decoding the instruction latched in the evening (1 2 C) When the husband is dedicated 's for each task buffer, a particular instruction execution Yuni' me arranged Regis evening means (S 1, S 2), prior g among his own plurality of taskbar Ffa and instructions Fuwetsuchuni' bets select a first selector which connects to instruction register evening that one selectively to be corresponding to the particular instruction execution Yuni' Bok (1 8), one from among the plurality of tasks buffer the the specific tasks Te A second selector (2 6) connected to click for instruction register evening, selectively said particular instruction outputs of the instruction decoder for the particular task of the instruction decoders corresponding to a particular instruction execution Yuni' DOO a third selector which connects to the execution Interview two Tsu Bok (2 7), on the basis of the instruction decoding result from the instruction decoder included in each of the instruction execution control system column, by the instruction execution control sequence that differs in phase Wataru whether capable of parallel execution of instructions checks for dependencies between it al instructions mutual delays the execution of a particular instruction depends on the result of execution of other instructions, the time to delay the execution of the particular instruction ^! 3 of contention management Interview two Tsu preparative said to select a specific task for the instruction decoder to the selector (2 5), the second selector with to select the instruction fetch unit to the first selector in an initial state The controls in a non-selected state, and the selection control the first selector in accordance Ibento generated internally or externally, and the second in response to the selection of the third of the instruction decoders for specific tasks by the selector of including selector and switching control means (1 9) to select a task buffer corresponding to Iben Bok generated internally or externally. BRIEF DESCRIPTION OF THE DRAWINGS

Proc view of de Isseki processor according to the first embodiment of Figure 1 the present invention,

Figure 2 is an example proc diagram of instruction Fuetsuchuni' bets,

Figure 3 is a block diagram showing a first example of a swap tasks buffer, Figure 4 is proc diagram showing a second example of Suwappu evening disk buffer, block Fig. 5 showing a third example of the swap tasks buffer FIG, FIG. 6 is a block diagram showing a fourth example of the swap tasks buffer, FIG. 7 is an illustration of an example of registry evening set included in the instruction execution Yuni' Bok, FIG. 8 is according to the first embodiment an illustration of an example of a task switching example operation in a data processor,

An illustration of an example of switching operation of FIG. 9 is normal instruction processing and interrupt processing, first 0 Figure an example timing chart showing the relationship between the task switching recombinant and Paiburain in de Isseki processor according to the first embodiment ,

The first 1 Figure exemplary operation timing chart of the de Isseki processor according to the first embodiment does not accept interrupts during Suwapputasuku,

Purodzu click diagram of a data processor according to the second embodiment of the first 2 figures present invention,

The first 3 figures an example operations evening I timing chart of a data processor according to the second 灾施 example of accepting an interrupt in the swap task, first 4 figures plot click data processor according to the third embodiment of the present invention Figure,

The first 5 figure control and task switching control example tie Mi Nguchiya Bok showing the contents of the case any de Isseki co Nfuriku preparative In de Isseki processor according to the third embodiment,

Plot click diagram of a data processor according to the fourth embodiment of the first 6 figures present invention,

The first 7 FIG Thailand Minguchiya one Bok showing the contents of the task switching control in case of any data con pretending click preparative to de Isseki processor according to the fourth embodiment,

Plot click diagram of a data processor according to a fifth embodiment of the first 8 figures present invention,

The first 9 FIG De according to the fifth embodiment when the resulting data conflicting bets - evening Thailand Minguchiya one Bok showing the task switching control performed by the processor,

The second 0 Figure of a data processing system to which the data processor of the present invention - example block diagram,

The second 1 Figure is an explanatory view showing an example of evening disk by DMA transfer control and de Isseki conversion control program,

The second 2 Figure is an explanatory view showing an example of a minimum unit of program descriptions of the DMA transfer control and de Isseki conversion control program,

The second FIG. 3 is a block diagram showing an example of a de Isseki processing system including a DMA controller which is arranged outside the cache memory and the de-Isseki processor employing a write-back scheme. To the best mode first diagram for carrying out the invention plot click view of Detapurosedzusa according to a first embodiment of the present invention is shown. De Isseki processor 1 shown in the drawing is not particularly limited, and is formed on a single semiconductor substrate like monocrystalline silicon by the known semiconductor integrated circuit manufacturing technique.

1 0 Instruction Fetchuni' bets in FIG. 1, 1 1 instruction register evening,

1 2 instruction decoder, 1 3 the instruction execution unit, 1 4 instruction cache memory, 1 5 data cache memory, 1 6, 1 7 swap task buffers representatively shown, 1 8 selector 1 9 switching control circuit, 2 0 are circuit proc which collectively chip peripheral module.

The instruction execution Yuni' sheet 1 3, the program counter evening PC, general register evening GR, each scan Wa Uz flop Task Buffer 1 6, 1 7 evening Regis assigned for an individual set S 1, S 2, interrupt control circuit 1 3 1, the sequence control circuit 1 3 2, including the arithmetic circuit such as 1 3 3.

In the data processor 1 of this embodiment, the instruction register evening 1, the instruction decoders 1 2 and the instruction execution Yuni' Bok 1 3 proceeds with the pipe Rain stage unit, pipelining instructions. Instruction register evening 1 1, operation cycle in the instruction decoder 1 2 and the instruction execution Yuni' sheet 1 3, synchronously illustration of de one evening processor 1 operating reference clock signal are omitted, the ¾ Symbol sequence control circuit 1 3 2 Control.

The instruction execution Yuni' Bok 1 3 is not particularly limited, in the outside via the data key Yasshu memory 1 5 connected to the internal bus BUS evening Hue - the scan. Target data key Yasshu memory cache is an external memory 2 and the like. De Isseki cache memory 1 5 Kiyasshi Interview de Isseki unit not shown, is illustrated as a circuit block including a cache tag unit and the cache controller. Cache data unit holds a part of data such as external memory 2's. Cache Yugu unit cache de - held part of the Adoresu in correspondence with data evening unit's (the Adoresu evening grayed) as a cache tag. When the cache controller of cache-hit Bok in external access, Kiyasshude output to the internal bus BUS to Isseki de according to hit from Kiyadzushude Isseki portion, or engagement Lud Isseki to hit as a new entry write to Isseki part. Canon in the case of Mesh miss gives the data read from the external memory 2 or the like to the internal bus BUS, to access writing a walk external memory 2 and the like. In Kiya' misses, Ru can do the replacement of the cache line. Is not particularly limited, the cache controller, the process for writing back the contents of the cache de Isseki portion rewritten by the cache hit me external memory 2 or the like is performed only when the replacement of Kiyasshiyurain is performed, so-called carried out by a write-back.

It said program counter evening PC is carrying instructions Adoresu to be executed next. Instruction Fedzuchu two Uz sheet 1 0 is not particularly limited, based on the value of the program counter evening PC, the plurality of instructions ahead specified by the expected instruction (for example program counter evening PC to be executed in the future fetching instructions). Instructions to be fetched is not particularly limited, and is stored in the external memory 3. Instruction key Yasshu memory 1 4 is disposed between the external memory 3 and the instruction Fetsuchunidzu sheet 1 0 In this example.

The instruction key Yasshu memory 1 4 Kiyasshude Isseki unit not shown, is illustrated as a circuit block including a cache Yugu portion and Kiyasshukon controller. Kiyasshude Isseki unit holds a part of the instruction such as the external memory 3 you Ho冇. Cache tag unit held part of the Adoresu the (Adoresutagu) as Kiya' Gerhard evening grayed in correspondence with the instruction cache data unit has coercive. Key Yasshu controller opening one La instruction Fuetchuni Tsu Bok 1 0 instructions held by the cache de Isseki part in the case of a cache 'hit in the memory access instructions Fetchuni' door 1 0 by - For example, in the case of a cache miss It reads instructions from the external memory 3 and the like gives the instruction Fuetsuchuni' sheet 1 0.

Instruction Fetchunidzu door 1 0 is not particularly limited, first-in-first-out

Has the function of the (First-in · First-out) buffer, Ru can be used to pre-fetch the instruction of multiple Wado worth to the program counter evening PC value. For example, a latch 1 0 0 A~ 1 0 0 D in four stages as shown in Figure 2 are arranged in series, directly outside without through the selector 1 0 1 A~ 1 0 1 C via a pre-stage of the latch or it is to be able to take instructions from the instruction key Yasshu memory 1 4. 1 0 2 is a control circuit of Me other instruction fetch outputs a Adoresu of Fuetchi should do instruction based on the value of the program counter evening PC, the instruction that it is by connexion input first-in first-out form the latch is held by the 1 0 0 A~ 1 0 0 D. be output from ft one Radzuchi 1 0 0 A~ 1 0 0 D. It is not particularly limited, La Tutsi 1 0 0 A~: I 0 0 D is latched instructions in two words ^ position, the instruction Deco one Da 1 2 decodes an instruction in units of one word. In response to this, the output of Detara Tutsi 1 0 0 D is output Ke minute Bok position word and the upper Wado selector 1 0 3.

Each of the scan Wa-up task buffer 1 6, 1 7, the program storage area 1 6 0, 1 7 0 and its storage area 1 6 0, 1 7 0 Poin for reading out the order next to the instructions stored in the evening and a 1 6 1 1 7 1. Particularly limited, such Iga, swap tasks buffer 1 6 is to be written for the program storage area 1 6 0 by executing Interview two Tsu sheet 1 3 via the internal bus BUS. Further, the swap tasks buffer 1 7, Shiriaruin evening face which is controlled by the instruction execution Yuni' sheet 1 3 (its control line is not shown) 2 1 write lump can for the program storage area 1 70 via the I have been in.

An example of a swap task bar Uz file 1 6, 1 7 is shown in Figure 3 - Figure 6. The example of Figure 3 is intended to a shift Torejisu evening and selector and the storage area 1 60 (1 70), a shift Torejisu evening the latch L AT plurality of parallel's output type comprising in cascade, each latch a selector SEL for parallel output from the parallel output select 1 bi Tsu Todzu' of L AT, busty and through the selector SEL, to select the output of Dear latch LAT from the upper side or de position side in order to selector evening SEL evening it is a configuration child by 1 60 (1 70). For example, a latch LAT each m bits and comprises n stages, sequential instructions in n-bi Uz Units can output m times. Data writing to the shift Torejisu evening is carried out in serial-in evening face 2 1 or instruction execution Yuni' Bok 1 3 control. Stages of the latch L AT is determined in accordance with the bits Bok number of instructions, in Figure 4 the number of stages of the latch L AT is shown different configurations is the third FIG. Figure 5 example the storage area 1 60 a RAM (Random Access Memory) consisting of dynamic memory cells or scan evening memory cell array MCA 1 was te I brute side memory cells arranged Ma Bok Rikusu and add-Les decoder ADEC 1 It is intended to, Poin evening 1 6 1 to generate an access § dress for the RAM. Write to RAM is controlled by the instruction execution Yuni' Bok 1 3. The example of FIG. 6 are all SANYO to a ROM (Read Only Memory) storing area 1 60 comprising a Fu揮 ¾-volatile storage elements from Matrix scan arranged memory cell array MCA 2 and the address decoder AD EC 2, pointer 1 6 1 to generate an access address for the R 0 M. The swap task buffer 1 6, 1 7, by connexion configured program instruction series to realize one of coherent processing is stored. If the unit of one conjoint ivy process realized by a specific instruction sequence is defined as Yusuke click, the processing program according to a specific task is stored (e.g., a processing program for the DMA transfer, data compression 'such as a processing program for the extension is set. scan Wa Uz loading processing program to flop task buffer 1 6, 1 7 is not particularly limited, serial-in due to power-on set at system I Nisha rise evening can be performed via the Hue one scan 2 1 and the instruction execution Yunidzu sheet 1 3.

It said selector 1 8 to connect to the selected one instruction register evening 1 1 from the swap tasks buffer 1 6, 1 7 and instruction Fetsu Chiyuni' sheet 1 0. The connection control is performed by the switching control circuit 1 9. The switching control circuit 1 9, at initialization reset the data processor 1 to the selector evening 1 8 to select the instruction Fuetsuchuni' sheet 1 0, then given that will be generated inside and outside Ipen Bok, for example, on-chip peripheral circuit module 2 0 to the selector 1 8 Te 従Tsu the notification signal 2 3 given Iben preparative generation of an interrupt signal 2 2 and the external from causing selects the output of the swap tasks buffer 1 6 or 1 7. The choice of swap tasks buffer, Iben Bok originates and swap tasks buffer and the look and determining correspondence table switching control circuit 1 9 comprises, or Iben preparative generation of a notification signal Suwa' flop P4 Yes per it can be controlled by assigning a task buffer.

It is not particularly limited, the instruction execution Yuni' sheet 1 3 outputs an instruction signal LIR for latching instructions to said instruction register evening 1 1. Instruction register evening 1 1 latches the instruction in synchronism with the instruction signal LIR. At this time, before Symbol selector 1 8 supplies the instruction signal LIR to the switching control circuit 1 9 selects instructions Fetchu Stevenage sheet 1 0 or swap task buffer 1 6, 1 7. When the instruction Fetchuni' Bok 1 0 Ru receives the instruction signal LIR, to update on the basis of the to be supplied instruction into the instruction register evening 1 1 to the instruction signal. Further, the task buffer 1 6, 1 7 receives the instruction signal LIR, updated based the Boyne evening 1 6 1 1 7 1 on the instruction signal LIR. Thus, the selector 1 8 Boyne evening 1 6 1 or 1 7 1 swap task bar Ffa 1 6 or 1 7 to be selected sequentially by updating, instruction storage area 1 60 in accordance with the Boyne evening value 1 70 It is supplied to the instruction register evening 1 1 from.

Swap Task Buffer 1 6, 1 7 program is run exit stored in the last switching by end signal 1 2 0 instruction is output is the instruction decoder 1 2 Dede co one de executed of the program control circuit 1 9 recognizes. Switching control circuit 1 9, when the Deco one de result receive (termination signal 1 2 0), returning the selector evening 1 8 to select the state of the instruction Fuetsuchuni' sheet 1 0.

The FIG. 7 Regis evening configuration example of an instruction execution unit 1 3 is shown. General register evening GR is Regis evening SR, including R 0 to R 1 5. SR is assigned to the evening stearyl Isseki Surejisu, R 0 ~ R 7 is assigned to the Isseki de Regis evening and address Les Soo evening, R 8 ~ R 1 5 De Isseki Regis evening, address register scan evening, stack Poin assigned to the evening, and the like. The Regis evening set Bok S 1 is Regis evening S 1 SR, includes S 1 R 0~S 1 R 7, wherein Regis evening set Bok S 2 is Regis evening S 2 SR, the S 2 R 0 ~ S 2 R 7 wherein, they Regis evening set S l, S 2 is evening Regis general register evening GR SR, is intended to be used in place of R 0 to R 7, having 夬 s unique register evening Adoresu. Regis evening set S 1 is exclusively assigned to the execution of the program stored in the swap task buffer 1 6, Regis evening set S 2 is dedicated to the execution of the program stored in the swap task buffer 1 7 the assigned, general register evening GR register SR, R 0 to R 7 is assigned to execution of the instruction output from the instruction fetch unit 1 0.

Is not particularly limited, general register evening GR Regis evening SR, R 0 ~ R 7, either by use of the registers evening set Bok S 1 or the register set S 2 throat Regis evening is Regis evening number and task types is determined by, for example it is specified in the operand field of the instruction. Said register SR instruction execution Yuni' Bok 1 3 The instruction execution when an instruction outputted from the instruction Fuetchuni' sheet 1 8 is selected, using the R 0 to R 1 5 instruction is output from the swap task buffer 1 6 instruction when the instruction execution Yuni' sheet 1 3 instruction execution register evening S 1 SR, using the S 1 R 0~S 1 R 7 instruction is output from the swap task buffer 1 7 is selected when it is selected run Interview Stevenage sheet 1 3 wherein the register Xi S 2 SR instruction execution, using S 2 R 0~S 2 R 7.

As described above, Suwadzupu evening disk buffer 1 6, 1 7 each have a unique Poi down evening 1 6 1 1 7 1, unique assigned to swap tasks buffer 1 6, 1 7 of the respective registers evening since having a set S 1, S 2, when the execution should do evening disk is switched between the instruction Fetchuni' sheet 1 0 and Suwappu evening Sukuno Ffa 1 6, 1 7, program counter evening PC and register scan evening GR scan evening accessing the click region processing, such as an external memory 2 to the value or return or retracted does not require.

The Figure 8 operation example of task switching is shown. The instruction Fuetsuchuni Tsu executes instructions from Bok 1 0 (normal instruction processing) state developing, for example, by a signal 2 3, execution request program stored in the swap task buffer 1 6 (swap task 1) When the switching control circuit 1 9, in synchronism with the switching of the pipeline stages, switches the selection state that by the selector 1 8 Suwappu evening to disk buffer 1 6. Thus, the scan Wa-up task buffer 1 6 and outputs the instruction to the first instruction swap tasks 1 Poin evening 1 6 1 in synchronism with the instruction ί3 No. LIR, the instruction register evening 1 1 latches this to. Further, instruction execution Yuni' sheet 1 3 when performing Suwapputasu click utilizes registry evening set S 1 are designated by the instruction description of the task. Thus, saving of the program counter evening PC, register SR, without requiring evacuation of R 0 to R 7, you can proceed to the execution of the swap tasks 1. When the last instruction in the switched swap task 1 is decoded by instruction decoder 12, the switching control circuit 1 9 to select the instruction Fetchunidzu bets 10 to the selector 18. At this time, the program counter evening PC ;, status register evening SR, data and Adoresurejisu evening R0 to R 7 are the values ​​of the switching immediately prior to the Wapputasuku 1 that has unchanged maintained. Regis evening R8 ~ R 15 in the execution of the swap has been stored in the task buffer 16 instructions is not utilized. Therefore, even when switching example of the normal instruction, it does not require a memory access for the return. In the case of switching between normal instruction processing and interrupt processing shown in FIG. 9 is retracted at every switching, memory access for return is required. Saving, memory accesses Me other return will O Ichibae' de task switching or pipeline switching.

An example of a pipeline state that put at the time of switching between the normal instruction processing and Suwapputasuku 1 in Figure 10 is shown. Is not particularly limited, the pipeline stages in de Isseki processor 1 of this embodiment is a five-stage, the pipeline stages in the normal instruction processing, the instruction Fuetchi (I n), instruction decode (Dn), calculation (En) , are the stages of memory access (an) and Le Jisutasu Ta (Sn). Pipeline stages in the swap task instruction transfer (C s), instruction decode (D s), calculation (E s), is a memory access (As) and Regis Yusuke store (S s) each stage of the.

For example, when the execution of Suwapputasuku 1 is required in the pipeline stage m, the switching control circuit 19 switches the selection state by Oite selector 1 8 in pipeline stage m + 1 to swap tasks buffer 1 6, the pipeline stages instructions for first instruction swap task 1 is transferred (C s 1) to the instruction register evening 1 1 in m + 1. At the time task switching as described above the program counter PC and register evening SR, without requiring evacuation of R 0 to R 7, you can proceed to the execution of the swap tasks 1. Processing for each pipeline stage following is advanced one at a time. Instruction execution Yuni' sheet 1 3, although the normal execution of the instruction processing utilizing general register evening GR, you use the registry evening set Bok S 1 in the execution of the swap tasks 1. How register to use the evening or is determined by each of the instruction description. When the last instruction in the switched swap task 1 is decoded by the instruction decoder 1 2 in a pipeline stage n (D s 1), end signal 1 2 0 is supplied to the switching control circuits 1-9. Switching control circuit 1 9 Paibura-in stage n + 1 instruction Fetchunidzu door 1 0 is selected to the selector 1 8, this is in the instruction register evening 1 1 in Yotsute pipeline stage n + 1 instructions after Fuetchiyuni' door 1 0 instruction is supplied from. Even when switching to the passing ^ instruction processing, as described above, it does not require a memory access for the return. As described above, Ipurain does not cause any disturbance during normal task switching between the instruction processing and Suwapputasuku 1. The said interrupt control 问路 1 3 1 In FIG. 1, as representatively illustrated interrupt request signal IRQ is supplied. Interrupt controller 1 3 1 receives an interrupt request in response to the interrupt priority set thereto. In this embodiment, the switching control circuit 1 9, swapping in a state in which the task buffer 1 6 or 1 7 and is selected by the selector 1 8, interrupt acceptance is inhibition signal INH rice one Bull to the interrupt control circuit 1 3 is supplied to the 1. Interrupt controller 1 3 1 does not accept any interrupt request when the interrupt inhibition signal INH is rice one table. Thus, de Isseki processor 1, when running the task in accordance with the program of the swap tasks buffer 1 6 or 1 7, until the completion of execution of the task, task switching is not performed. In other words, will be the highest execution priority level is given to the task by the scan Wa-up task buffer 1 6 or 1 7 in the stored program. Interrupt controller 1 3 1 accepts the interrupt request, it interrupts the current instruction execution, the program counter evening PC, the status register SR, the data and Adoresurejisu evening R 0 to R 1 5 inner like the external memory 2, etc. It is saved on the stack of subsequently branches to the interrupt request processing program accepted.

Example of Operation When not accept interrupts during swap task as described above is shown in the first 1 FIG. When there is normally an interrupt request in the course of processing, after saving the like return address, is branched to the interrupt processing, the interrupt process is terminated, after the restoration process is returned to the normal processing I¾. If there is an execution request for Suwapputasuku 1 in the normal process, the switching control circuit 1 9 by selecting the swap task buffer 1 6 is immediately moved to the execution of Suwapputasuku 1. Since during the swap task 1 executes the interrupt disable signal I New Eta is rice one table, even if there is an interrupt request, during which interrupt request is not accepted. Acknowledgment disabled once was interrupt request, Eta New interrupt disable signal I after completion of swap task 1 execution is accepted after being Disue one table. When branching to interrupt processing First, it retracts the normal return address and registers evening value of the instruction process being interrupted, is branched to the interrupt processing after it. After the interrupt processing ends, after returning the the saved information is returned to the normal instruction processing.

The first 2 Fig second embodiment of the data processor according to the present invention is shown. Data processor 1 Alpha shown in the figures, that even during the execution of the task by the swap tasks buffer 1 6 or 1 7 in the stored program to allow accepting interrupt is a data processor 1 of FIG. 1 Ru is the difference. In other respects is the same as FIG. 1, the same will not be further described by the same reference numerals are given to the circuit proc the same function.

In de Isseki processor 1 A, an interrupt control circuit 1 3 1 accepts the interrupt request, and supplies before Symbol switching control circuit 1 9 an interrupt control signal ICNT in the rice one table. Switching control circuit 1 9, when the selector 1 8 selects the swap task buffer 1 6 or 1 7, when the interrupt control signal ICNT is rice one table, the instruction selection state by the selector 1 8 Fuwetsuchuni' the switching control to me 1 0. Further, to save the information (swap task selection information) for identifying the scan Wa-up task buffer 1 6, 1 7 which has been selected immediately before switching. Save destination, it is desirable to retract latch omitted switching control circuits 1 9 internal illustrated. May be saved in the stack area, such as an external memory 2, but if so, Razz Do unless starts an external bus access cycle for returning the Suwapputasuku selection information when returning from the interrupt processing Suwapputasuku, This is because the return to Suwapputasuku treatment is delayed.

If an interrupt is received during the execution of the swap tasks, branch to Suwapputasuku it is being made then the previously normal instruction processing. Therefore, after completing the interrupt processing, Unishi must'm that can return to the normal processing of the current suspended. Therefore, after the retraction of the switching and scan Wa Pputasuku selection information of the selector 1 8, return address and registers evening information of the normal instruction processing which is currently suspended is evacuated and is then branch to the interrupt processing program.

The first 3 FIG example of operation when an interrupt is received during the swap task is shown. When there is an interrupt request during the normal instruction processing, after saving the like return address, is branched to the interrupt processing, the interrupt processing Ru is terminated, after the return process, and returned to the normal instruction processing. If there is an execution request for the swap task 1 in the normal instruction processing, the switching control circuit 1 9 by selecting the swap task buffer 1 6 to the selector 1 8, it is immediately transferred to the execution of the scan Wa Pputasuku 1. Interrupt controller 1 3 1 can accept an interrupt even during the swap task 1 executes an interrupt to give accepted, supplied to the switching control circuit 1 9 an interrupt control signal ICNT in the rice one table. That this shall switching control circuit 1 9 controls switches the selection state by the selector evening 1 8 instruction Fetchuni' sheet 1 0, swap task selection information order to identify the swap tasks buffer that was selected at that time evacuate. Then, the interrupt instruction execution Yuni' sheet 1 3 that has received the, after the previously processed it is retracted (S 1) a return address and registers evening information of the normal instruction processing interrupted in the stack area, branch to the interrupt processing program to. When the interrupt processing is terminated (T 1), said interrupt control signal ICNT is disabled, the switching control circuit 1 9 by Re This, according Suwapputasuku selection information saved, swap task 1 that has been suspended resume the execution of the. When the last instruction in this swap task 1 is decoded by the instruction decoder 1 2, end signal 1 2 0 is given to the switching control circuit 1 9, Yotsute thereto, switching example control circuit 1 9 selector 1 8 causing selects the output of the instruction Fuetsuchi circuit 1 0. Then, the interrupt processing return process after the (S 2) is started, return address and registers evening information of the normal instruction process being retracted is restored, normal instruction processing resumes. When the return processing (S 2), the interrupt processing ends (T 1) being pulled stretched to the end swap task processing 1 to be resumed later, but this, the interrupt process is terminated (T 1), switching the control circuit 1 9, based on the this said Suwaputasuku selection information has been saved, because obtain switching the selector 1 8 first, scan Wa-up task buffer 1 6.

The first 4 FIG third embodiment of de Isseki processor according to the present invention is shown. Data processor 1 B shown in the figure has a scan one Pasukaraa one Kiteku Chiya, multiple instructions may want to consider performing some parallel by two pipelines. That is, the first instruction execution control sequence for executing the instruction instruction execution Yuni' Bok 1 3 A is decodes the instruction that latched in the instruction register evening 1 1 A at instruction decoder 1 2 A, the instruction register evening 1 latched instruction to the instruction decoder 1 2 decoded by the instruction execution Yuni' Bok 1 3 B in B to 1 B is a second instruction execution control sequence for executing the instruction. Pipeline processing performed in the first instruction execution control sequence called pipe 0, the pipeline processing performed by the second instruction execution control sequence is referred to as pipe 1. LIRA the instruction signal of the instruction latch for instruction register evening 1 1 A, LIRB is instruction signal of the instruction latch for the instruction register scan evening 1 1 B, is corresponding to the instruction signal LIR.

The instruction execution Yuni' preparative 1 3 A, 1 3 B is 冇 a dedicated been sequence control circuit 1 3 2 A, 1 3 2 B an arithmetic circuit 1 3 3 A, 1 3 3 B respectively. Dependencies between instructions mutual like Detako Nfuriku Bok occurring between pipe 0 and pipe 1 is contention management Yuni' Doo 2 5 is detected based on the instruction decoder 1 2 A, 1 2 B Deco one de results. That is, conflict management Yuni' DOO 2 5, based on the instruction decoder 1 2 A, 1 2 instruction decode results from B, and whether it is possible to parallel execution of instructions by Roh Eve 0 and pipe 1 between them instruction mutual checks for dependencies, to delay execution of Ru instruction name depend on the result of execution of other instructions, the control ί No. ARBA, controls the sequence control circuit 1 3 2 a, 1 3 2 B by ArBB.

Interrupt controller 1 3 1, program counter evening PC, general register evening G

R is co ¾ both instruction execution Yuni' Bok 1 3 A, 1 3 B. Regis evening set S 1, S 2 is dedicated to the instruction execution Yuni' Bok 1 3 B. Their For these details are the same as de Isseki processor of FIG. 1.

De Isseki processor 1 B smell of the scan one pass color architecture Te, the selector 1 8, switching control circuit 1 9 and swap tasks buffer 1 6, 17 to the instruction execution control sequence of instructions Regis evening 1 1 B-side It is located. Then, similarly to the data processor of FIG. 1, the instruction Fetchuni Uz sheet 1 0, the instruction key Yasshu memory 1 4, chip peripheral module 20, such as de one evening cache memory 1 5 is provided. The one having a first 1 [¾1 same function is omitted the detailed description thereof are denoted by the same marks ^ in Figure 14. In the case of FIG. 14, the both swap tasks buffer 1 6, 1 7 so that the initial loading of the program via the internal bus BU S is performed.

The first 5 FIG contents of the control and task switching control case any data conflicting preparative In the data processor 1 B are example ^.

For example, each pipeline stage m s instruction register evening 1 1 A, 1 1 conflict management in B to latch instruction of Deco one de stage (Π1 + 1) Yuni' bets 2 5 detects the data conflicting bets are run later execution of Rubeki instruction until the execution result of the instruction to be executed first is obtained NO P - are (Bruno down operation). That is, I can use the results of Regis Yusuke store pipe 0 (S n) in the pipeline stages (m +4) in the operation stage pipe 1 (E n) of the stearyl one di (m + 4) Uninaru until pipeline stages Paibu 1 is a NO P. Furthermore, the execution of the swap task 1 is required in the pipeline stage m + 3, the switching control circuit 1 9 switches the selection state by the selector 1 8 in Suwadzupu evening disk buffer 1 6 in a pipeline stage m + 4, instructions for the first instruction of the pipe 1, the scan Wa Pputasuku 1 is transferred to the instruction register evening 1 1 B in the pipeline stage m + 4 (C s 1). At the time task switching described above program counter evening PC and register evening SR, without requiring evacuation of R 0 to R 7, you can proceed to the execution of the swap tasks 1. The following process for each pipeline stage of the pipe 1 is sequentially advanced. At this time, the instruction execution Yuni' preparative 1 3 B, the execution of Suwa' Putasuku 1 utilizing Regis evening cell Uz Bok S 1. Which register whether to use the evening is determined by similarly respective instruction description and the examples. When the last instruction in Suwadzubutasuku 1 was replaced switching is decoded by the instruction decoder 1 2 B in pipeline stage n + 1 in the pipe 1, the end signal 1 2 0 to the switch changeover control circuit 1 9 is supplied. Switching control circuit 1 9 to select the instruction Fetchuni Uz sheet 1 0 to the selector 1 8 in pipeline stage n + 1, the instruction in the instruction register 1 1 B in this pipeline stage n + 1 and later Yotsute pipe 1 instruction is supplied from the Fetsuchunidzu door 1 0. This normal instruction processing in Yotsute pipe 1 is resumed in. Even when switched to the normal instruction processing, as described above, it does not require a memory access for the return. As described above, when the normal task switching in question with the instruction processing and Suwappu Yusuke click 1, the pipeline does not cause any disturbance.

The first 6 FIG fourth embodiment of de Isseki processor according to the present invention is shown. Data Bro processor 1 C shown in the drawing is the data processor 1 has a scan one pass color architecture similar and B, a plurality of instructions can be executed in parallel by two paths Ipurain. Differs from the de Isseki processor 1 B is that it has a de one Takonfuriku bets occur as single-switching example factors to Suwapputasuku when that one row normal instruction processing by a pipe 0 and pipe 1. Conflict management Yuni' Bok 2 5 gives to the control circuit 1 9 switches the control signal 2 5 0 in synchronism with the generation of the de Isseki co Nfuriku Bok. This by the connexion switching control circuit 1 9 performs processing of the swap task 1 by using an empty pipe 1 in the normal instruction processing by the data conflicting Bok. However, since the pipe 1 side instruction register evening 1 1 B and the instruction decoders 1 2 B is only one set, upon de one Takonfuriku preparative run execution is interrupted instruction by restarting would start from the instruction Fuetsuchi . Its control sequence control circuit 1 3 2 B is performed. Since other configurations are the same as the data processor 1 B in FIG 1 4 Detailed description of the configuration will be omitted.

The contents of the task switching control in case of any de one Takonfuriku bets are illustrated in the first 7 FIG. For example, pipeline stages m in each instruction les Soo evening 1 1 A, 1 1 B conflicts latched instruction decode stage (m + 1) to the management Yuni' Bok 2 5 detects the data conflicting Bok, or we run after execution of instructions to be is a NOP (non 'operating one Chillon) until available execution result of the instruction to be executed first. That is, the results of the pipe 0 Rejisutasu Ta (S n) in the pipeline stages (m + 4) to become available in the pipe 1 in operation stage (E n) in the stage (m + 4), the pipe 1 execution of the normal instruction processing in the pipeline stage of is stopped. The instruction is notified to the instruction execution Yuni' preparative 1 3 B by the control signal ArBB. In this case, conflict management Yuni' DOO 2 5 gives the switching control circuit 1 9 activates the control signal 2 5 0. Switching control circuit 1 9, to select a Suwa' flop Task Buffer 1 6 to the selector 1 8 in response thereto. As a result, the pipeline stage m + 1~! Pipe 1 at 11 + 5 can perform processing of swap tasks 1. Period allowed for processing ¾ swap task 1 is a phase question normal instruction processing Paibu 1 by Detako Nfuriku Bok is Habadan, that period is controlled by contention management Yuni' DOO 2 5, the control signal 2 5 0 is reflected in by the control signal 2 5 0 is inactive, the selected state of the selector 1 8 back into the selected state of the original normal instruction processing (selection state of the instruction Fetchuni Uz Bok 1 0) It is. At the time task switching described above pro Guramukaun evening PC and register evening SR, without requiring evacuation of R 0 to R 7, you can proceed to the execution of the scan Wapputasuku 1. At this time, the instruction execution Interview two Uz Bok 1 3 B, the execution of the swap task 1 you use the registry evening set S 1. Which register utilizing evening or is by connexion determined in the same manner as each of the instruction description and the examples.

In the example of FIG. 1 7, each pipeline stage m + 3 s instruction register evening 1 1 A, 1 1 B to the latched instruction decode stage (m + 4) smell even conflict management Yuni' preparative 2 5 is de one detects the Takonfuriku Bok, in the same manner as described above, computation scan tape one pipe 1 results Regis Yusuke bets § pipe 0 in the pipeline stages (m + 7) (S n) in the stage (m + 7) until available in di (E n), execution of the normal instruction processing in the pipeline stages of the pipe 1 is stopped, alternatively, pipes 1 are subjected to processing of the swap tasks 1. Limited by this example, the hash processing of the swap tasks 1, but the processing evening I timing is also limited to the data con flip click preparative incurred, the de Isseki Konfuriku bets on specific processing Ya processing in evening one Bal it is effective when applied to a no treatment. Further, the control signals 2 5 0 may be used as a control signal for defining timing for processing the signals 2 2, 2 3 swap tasks selected in practice.

The first 8 FIG fifth embodiment of the de Isseki processor according to the present invention is shown. De Isseki processor 1 D shown in the figure has the de Isseki scan one pass color architecture similar to the processor 1 B, a plurality of instructions can be executed in parallel by two paths Ipurain. De Isseki processor 1 D, as well as the de Isseki processor 1 C, switching factors of occurrence of de one Takonfuriku Bok to scan Wa Pputasuku when performing the normal instruction processing Te Paibu 0 and pipe 1 Niyotsu Although one of, that it includes a dedicated manner assigned instruction registers evening 1 1 c in Suwa' Putasuku executed at that time the instruction decoders 1 2 C is different from the de-Isseki processor 1 C. Instruction selection Les Soo evening 1 1 C inputs performs selector 2 6, the output of the instruction decoder 1 2 B or 1 2 C is selected by the selector 2 7.

Conflict management Yuni' DOO 2 5 gives the selectors 2 7 and the control circuit 1 9 switches the control signal 2 5 0 which is in synchronism with the generation of de one Takonfuriku Bok rice one table. With the Yotsute selector 2 7 to select the output of the instruction decoder 1 2 C, the control signal LIRB also supplied to the instruction register evening 1 1 C side, the instruction register 1 1 B intact instructions currently held maintaining, in place of Re its instruction register 1 1 C is enabled latch the new instruction in accordance with the control signal LIRB. Further, the switching control circuit 1 9 connects the control signal 2 5 0 Rice one Bull state swap task bar Ffa 1 6 or 1 7 by the selector 2 6 to the instruction register evening 1 1 C. Which is either by connection it may be fixed also be selectable. For example, when Detapurose Tsu service initialization reset, so as to determine whether to select what Re according to the operation mode to be Botsujo.

If utilizing conventional free pipe 1 instruction processing by the data conflicting preparative example performs processing swap tasks 1, because the pipe 1 side comprising instructions Regis evening 1 1 C and the instruction decoder 1 2 C for which dedicated , the data upon Konfuriku Bok execution execution is interrupted instruction by resuming need not start from the instruction Fuetsuchi as de Isseki processor 1 C. Immediate Chi pipeline is not disturbed at all. The other configuration is the same as de Isseki processor 1 C detailed description of the structure will be omitted.

The contents of the task switching control performed by the data processor 1 D in case of any de one Takonfuriku bets are illustrated in the first 9 FIG. Each instruction register evening 1 1 A, 1 1 B conflicts latched instruction decode stage (m + 1) to the management Yuni' DOO 25 is executed later when detecting the data con Furiku bets, for example pipeline stages m instruction execution to is up to execution of the instruction to be executed first is obtained NO P (non 'Operations). That is, the results of Regis Yusuke store the path Eve 0 in the pipeline stages (m + 4) (Sn) to become available in the stage (m + 4) to your Keru pipe 1 of the arithmetic stage (En) , execution of the normal instruction processing in the pipeline stages Roh I flop 1 is stopped. Compare with FIG. 17 is that it does not require to repeat anew instruction Fetsuchi and Decorating one de For Figure 19 stage m + 4 of definitive pipe 1 operation stage (En). Normal execution stop instruction processing instructions in pipeline stages of the pipe 1 is notified to the instruction execution Yuni' preparative 13 B by the control signal AR BB. In this case, conflict management Interview Stevenage DOO 25 Ru applied to the switching control circuit 19 activates the control signal 250. Switching control circuit 19 to select the swap evening disk buffer 1 6 to the selector 18 in response thereto. Thus, the pipe 1 in a pipeline stage m + 1 to m + 5 can perform processing of Suwapputasuku 1. Period allowed for processing the swap task 1 is a phase question normal instruction processing of the pipe 1 by de one Takonfu Riku Bok is interrupted, that period is controlled by contention management Yuni' sheet 1 5, the control signal 250 is reflected, the signal 250 by being inactive, the selected state of the selector 18 is returned to the selection state of the original of the normal instruction processing (selection state of the instruction Fetchuni' bets 10). At the time task switching described above program force © down evening PC and register evening SR, without requiring evacuation of R0~R 7, swap evening can proceed to the execution of disk 1. At this time, the instruction execution Yuni' Bok 13 B, the execution of the swap tasks 1 utilizing Regis evening cell Uz Bok S 1. Which register utilizing evening or is determined by the same manner each of the instruction description and the examples.

In the example of FIG. 1 9, respectively instruction register evening 1 1 A, 1 1 B to the latched instruction decode stage (m + 4) smell even conflict management Yuni' Bok 25 is de one Takonfuriku preparative pipeline stage .pi.1 + 3 detecting and, in the same manner as described above, the registry Yusuke bets § pipe 0 in the pipeline stages (m + 7) of the (S n) the result of the pipe 1 in the stage (m + 7) Starring! ? Scan Te temporarily until they can be used in (E n), execution of the normal instruction processing in the pipeline stages of the pipe 1 is stopped, alternatively, pipes 1 are subjected to processing of the swap tasks 1.

The Figure 20 an example of a data processing system applying the de Isseki processor 1 is shown. The scan de Isseki external bus 4 of the processor 1 the external memory 2 and the input-output circuit 5 is typically ^. External bus 4 comprises § de Resubasu ABU S, de Isseki bus DBU S and a control bus CBU S. In this system, the swap task buffer 1 6 Data Bro processor 1 DMA transfer control and data conversion control program is store. The start of the DMA transfer control and data conversion control program is an interrupt signal 2 3 0 assigned to one of the control signals 23. The interrupt signal 230 is supplied from the input and output circuit 5. The second 1 Figure an example of a task by the DMA transfer control and data conversion control program is shown. That is, the interrupt signal 230 from the input and output circuit 5 is supplied to the switching control circuit 1 9, processing program of a data processor 1 is switched to the DMA transfer control and data conversion control program stored in the swap task buffer 1 6 It is. Tasks to be processed by this program is input-output circuit reads data from the 5, the read data to the instruction execution Yuni' sheet 1 3 Dede Isseki converted (e.g. compression or coordinate transformation), the memory 2 the converted data of you write control in a predetermined area. Read address and write address, for each data transfer and de Isseki conversion, it is sequentially updated by the program. An example of a minimum unit of program description of such DMA transfer control and de Isseki conversion control program shown in the second 2 FIG. As described above in task switching using the swap tasks buffer, since there is no disturbance of the pipeline without the need for saving process, such as normal interrupt processing, it is a child fast response to Iben Bok generated .

In the above embodiment represented by the data processor 1, Suwa' flop Task Buffer 1 6, 1 7 If you set the DMA transfer control program, as compared with the system configuration as illustrated in the second FIG. 3, the burden of the data processor 1 of fried to solve the problem of Kiyasshuko Hirenshi it is possible to mitigate. That is, in the system configuration of the second 3 diagram, when Kiya' Shumemori 1 5 adopts the write-back method, starting the DMA configuration Bok roller 6 DMA transfer in a state where the rewriting of the cache memory 1 5 is not reflected in the external memory then, because the Kunar such keep the cache Kohi one Renshi, de Isseki processor 1 E is constantly monitors the startup of the DMA transfer operation has a kept a cache coherency, 予Jimera I-back operation when it detects it the it is necessary to carry out, the data processor 1 E must burden processing for detecting an action that does not keep the key Yasshu coherency. In contrast, when the de Isseki processor 1 of FIG. 1 as an example, in a state in which the processing task of the data processor 1 is switched to the DMA transfer control process via the selector 1 8 etc., function as a DMA controller executes Yuni' sheet 1 3 so that is realized. Thus, between the external memory of de one evening processor 1, or when controlling the DAM de Isseki transferred between external memory and an external output circuit, Adore scan signal or access control information for the DMA transfer control is always Detakiya It will be passed through the Dzushumemori 1 5. Thus, when the cache memory 1 5 adopts a line concert Seok method, even if the DMA transfer is started in a state in which rewriting of the cache memory 1 5 is not reflected in the external memory, is reflected in such external memory not de Isseki is loaded into the instruction execution Yuni' sheet 1 3 Kiyadzushumemori 1 5, because to be transferred, Detapu port Sedzusa 1, the process for detecting an action that does not keep a Kiyadzushukohi one Renshi there is no need to bear. Incidentally, in the DMA transfer control function realized by the de Isseki processor 1, the transfer de Isseki is - Danderyd Isseki will be read into the processor 1.

Although the present invention made by the inventor has been concretely describes with reference to Examples, the present invention is not limited thereto, in horse it can be variously modified within a scope not departing from the gist thereof Absent.

For example, the number of swap tasks buffer can be suitably changed without being limited to the above embodiments. The cache memory is not limited to the configuration in which separate de Isseki Kiyasshume memory and an instruction key Yasshu memory, unified is also used in the instruction and data evening 'may be a cache memory. Further, the number of stages of pipeline stages is not limited to five stages of the above embodiment. Further, the number of parallel operations possible pipe in scan one path forces Rade evening processor is not limited to two, but may be more. Furthermore, the contents of the swap tasks can be applied of any type as needed, not limited. Industrial Applicability

As described above, the data processor according to the present invention can be widely applied various de Isseki processing system, in particular frequent system task switching is performed, in systems requiring increased data throughput, for example, it is possible to apply a transfer and data compression of the shooting de Isseki in daisy evening cameras so etc. Computing evening system for embedded device control having as Suwa' Putasuku.

Claims

The scope of the claims
1. Fetches instructions Fetchuni' Bok instruction, instruction an instruction decoder which is latched in the instruction register evening is decrypted, the data processor instruction execution Yuni' Bok executes an instruction based on the decoding result,
A plurality of tasks buffer storage area and the Boyne evening for out sequentially read the instructions stored in the area each with a program,
Dedicated to the each of the respective tasks buffer, and registers evening means disposed in front Jd instruction execution Yuni' Bok,
A selector for connecting one to selectively said instruction register evening, - from the instruction Fuetchunidzu Bok said plurality of evening Sukuno Ffa
Together to select the instruction Fuetsuchuni' Bok said selector evening in the initial state, the switching control means for selecting controlling the selector evening according Iben preparative generated internally or externally,
Those made provided, and Intafu I- scan means part the data writable outside fin evening off We Ichisu - all or of the plurality of Tasukubaffu § under the control of the instruction execution Yuni' Bok de one evening processor, characterized in that.
2. Before ci instruction register evening, instruction decoder and the instruction execution Yuni' TMG, Isseki de of Claims paragraph 1, wherein a is for Paiburain processing instructions proceeds at pipeline stage units processor.
3. The instruction execution Yuni' DOO said instructions Regis outputs an instruction issue for latching instructions to evening, the selector is supplied to the instruction fetch unit or task buffer the instruction issue ί previous switching control hand stage selecting and, instructions Fetsuchunidzu DOO is updated based instructions to be supplied to the instruction register evening on the instruction signal, the claims the task buffer is characterized in that for updating based on the pointer to the instruction signal the first Ko乂 de Isseki processor according the second term.
4. The switching control means is characterized that it is intended to the selector based on the result of decoding is supplied to the instruction decoders from the selected task buffer instruction back to the selected state of the instruction Fetchuni' Bok billed range data processor of the third term describes.
5. The switching control means, the scope of the claims in response to selection of the task buffers, and characterized in that outputs an interrupt disable signal to disable the interrupt signal to be input to the instruction execution Yuni' DOO de Isseki processor of the third term describes.
6. The switching control means may return to the selected state before the SL instruction execution Yuni' preparative by said in response to acceptance of the interrupt selector evening instructions Fuetsuchuni' Bok when selecting the task buffer, the task buffers of the immediately preceding data processor range 两第 3 claim of claim, characterized in that in which retracting the selected state.
7. Range first Ko乂 De Isseki processor of the mounting second preceding claims, characterized in that those comprising data key Yasshu memory Bei Ete between said instruction execution Yuni' Doo and external.
8. A data processor in the range 7 claim of claim, the data processing blocks connected external to De Sa Isseki bus, those comprising the external data bus connected to the memory and human output circuit Day evening processing system, characterized in that there.
9. Both the instruction register evening instruction execution Yuni' preparative decodes the instruction decoder instructions latched comprises a plurality of sequences of instruction execution control sequence for executing the instruction includes instructions Fuwetsuchuni' Bok to off I Tutsi instructions, multiple and have your instructions in parallel executable data processor by the plurality of instruction execution control sequence,
A plurality of tasks buffer Poin the evening and are each equipped for out sequentially read the instruction storage area and stored in the area of ​​the program,
Dedicated to the each of the respective tasks buffer, and registers evening means disposed particular the instruction execution Interview two Tsu DOO,
A selector for connecting one to the instruction registers evening which is corresponding to the particular instruction execution Yuni' preparative Select, - from the instruction Fuwetsuchuni' Bok said plurality of evening disk buffer one
JP together to select the instruction Fuetsuchuni 'Seo preparative said selector evening in the initial state, the switching control means for selecting controlling the selector evening according Iben Bok generated internally or externally, to be those formed by providing a de Isseki processor to butterflies.
1 0. Instruction register evening included in the respective instruction execution control sequence, instructions Deco
- da and the instruction execution Yuni' TMG, de Isseki processor according range 囲第 9 days claims, characterized in that the instructions proceeds at pipeline stage unit is for processing pipeline.
1 1. Based on the instruction decoding result from the instruction decoder contained in the respective instruction execution control sequence, the dependency between them instructions mutual whether capable of parallel execution of instructions by mutually different instruction execution control sequence examined, de one evening processor ranging first 0 claim of claim, characterized in that those formed by your contention management Yuni' bets to delay the execution of instructions that depend on the result of execution of another instruction.
1 2. The switching control means, said conflict when the management Yuni' bets delays the execution of a particular instruction, claims, wherein the first item 1, wherein said selecting means is intended to select a task buffer data processor.
1 3. Instruction execution Yuni' preparative contained in the respective instruction execution control sequence, and outputs an instruction signal for pre-Symbol instruction register evening to latch the instruction, the selector is output from the instruction execution Yuni' Bok which is corresponding wherein an instruction signal is supplied to the instruction Fetchuni' preparative or Tasukuba' file the switching control means selects the instruction Fuwetsuchuni' DOO is updated based instructions to be supplied to the instruction register evening on the instruction signal, the task buffer the pointer that data processor ranging first one of claims claims, characterized in that the is to update on the basis of the instruction signal.
1 4. Co the instruction register instruction which is latched in the evening is decoded by the instruction decoder instruction execution Yuni' Bok comprises a plurality of sequences of instruction execution control sequence for executing instructions includes instructions Fetsuchuni' you want to Fuetsuchi instructions, multiple Te capable of parallel execution data processor odor before Symbol plurality of instruction execution control sequence instructions,
Storage areas of the program and the a plurality of tasks buffer the respective provided with a pointer for issuing sequentially read the instructions stored in that area,
An instruction register scan evening for specific tasks, which are dedicated to the plurality of tasks buffer,
An instruction decoder for a specific task that decodes the instruction latched in the instruction register evening for the particular task,
Dedicated to the said respective tasks buffer per-a Regis evening means disposed to a particular instruction execution Yuni' DOO,
A first selector connected to the instruction register evening which is corresponding to the particular instruction execution Yuni' preparative selectively the single one out of the instruction Fuwetsuchuni' bets and the plurality of task buffer,
A second selector for connecting to said specific tasks for the instruction register evening by selecting one of the plurality of tasks buffer,
A third selector for selectively connected to the front ¾ particular instruction execution Interview Stevenage Bok the outputs of the previous SL specific tasks for the instruction decoder of the instruction decoders corresponding to the particular instruction execution Yuni' DOO,
Based on the instruction deciphering result from the instruction decoder contained in the respective instruction execution control sequence, whether Parallelable execution of instructions by mutually different instruction execution control sequence checks for dependencies between those instructions mutual , delay the execution of a particular instruction depends on the result of execution of other instructions, and conflict management Yuni' bets to select the for a specific task instruction decoders to the third selector when delaying the execution of the particular instruction,
In the initial state with to select the instruction Fetsuchuni' preparative said first selector and controls the second selector to a non-selected state, and the selection control the first selector according to the event to be generated internally or externally, or and, provided, and switching control means for selecting a task buffer corresponding to Ibento generated internally or externally to the second selector in response to the selection of the instruction decoder for Japanese ¾ task by said third selector de Isseki processor characterized in that made.
PCT/JP1996/002819 1996-09-27 1996-09-27 Data processor and data processing system WO1998013759A1 (en)

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US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
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US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
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US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
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US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
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US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
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US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US6928073B2 (en) 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US7000078B1 (en) 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US7228389B2 (en) 1999-10-01 2007-06-05 Stmicroelectronics, Ltd. System and method for maintaining cache coherency in a shared memory system
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WO2004023291A1 (en) * 2002-08-30 2004-03-18 Renesas Technology Corp. Information processing apparatus
CN102135867B (en) 2010-01-21 2014-04-02 联阳半导体股份有限公司 Data processing module and method thereof
JP2014501969A (en) * 2010-11-18 2014-01-23 日本テキサス・インスツルメンツ株式会社 Context switching method and apparatus

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