JPH03163627A - Instruction processor - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of a pipeline at the time of executing an instruction by adding a branching address generating means to a computer system provided with a pipeline instruction processing mechanism, and executing simultaneously the branching address generation in a machine cycle for reading out an operand. CONSTITUTION:In the case an instruction 1 is a branching instruction, a branching address generating means 19 generates a branching destination address by the transfer instruction of an instruction fetching means 11 in the OF/BA stage of a machine cycle t1, and sends it to a multiplexer 18 with the start of t2. Subsequently, an operand fetching means 12 sends the success/failure information of the branch to the multiplexer. In the IF stage of t2 of a succeeding instruction 2, from two instruction addresses transferred from the means 11 and 19, the multiplexer 18 selects an appropriate address by information sent from the means 12, reads out an instruction from a memory 15 and fetches it to the means 11. Even between the branching instruction and the succeeding instruction, there is no room in an execution pipeline, and the parallel execution can be performed. Also, the OW cycle of the instruction 1 and the OF/BA cycle of an instruction 3 are activated by an exclusive timing, therefore, a register file 16, a fetching means 12 and a writing means 14 can share a bus.

Description

Detailed Description of the Invention [Industrial Application Field] The first and second inventions relate to an instruction processing device for an information processing device, and in particular, the first invention relates to a single machine equipped with a vibe line instruction processing mechanism. RISC executes instructions in cycles
The second invention relates to a parallel instruction processing device that executes a plurality of instructions in parallel, and a pile line instruction processing device that utilizes a vibe line mechanism to achieve high-speed processing.

[Conventional technology]

(1) In the conventional technology related to the first invention, computers with various pipeline configurations have been developed as the performance of computer systems increases. A pipeline method is often used in which each write is placed in one pileline stage. In this type of pipeline system, as shown in the pipeline timing chart of a conventional instruction processing device in Figure 3(a), there are two steps: ◆Instruction fetch from memory (abbreviated as IF stage), ●General-purpose register● From file The pipeline consists of four stages: ● operand fetch (abbreviated as OF stage), ● instruction execution (abbreviated as EX stage), ● operand ● write to general-purpose register ● file (abbreviated as OW stage).

Since processing at each stage of the pipeline can be executed in an emmachine cycle, an instruction can be executed every machine cycle. Furthermore, since each process is subdivided, the machine cycle itself can be made faster. Therefore, a high-performance instruction processing device can be provided.

(2) Further, as the conventional technology related to the second invention, there is the following technology.

(a) VLIW type parallel computer
ction Word) method, as shown in Figure 8,
Parallel processing is achieved by distributing relatively long instructions into a large number of fields and independently controlling a large number of arithmetic units, registers, interconnection networks, memories, etc. in each field.

In the VLIW method, the parallelism of operations is extracted at the time of compilation, and the compiler synthesizes those that can be operated in parallel into one instruction. High-speed processing can be achieved when the degree of parallelism is close to the number of parallel computing units.

However, when the degree of parallelism is low, empty space is created in the instruction field, reducing the bit usage efficiency of instructions.

The extent to which the instruction field can be filled depends on the capabilities of the compiler and the source program.

In the VLIW method, since the parallelism of a program is extracted at the time of compilation, there is no need to perform complicated processing such as detecting data dependencies. Therefore, the hardware configuration can be easily configured.

The VLIM method is based on a concept derived from the horizontal microinstruction method, and is suitable for fine-grained parallel processing (low-level parallel processing) using arithmetic units with a low functional level.

(b) Instruction pipeline processing The execution process of machine instructions in a computer system is instruction fetch (abbreviated as read 20F), instruction decode (decode: abbreviated as ID), operand address generation (abbreviated as OA), operand ● This is done by sequentially proceeding with fetching (abbreviated as OD), operation execution (abbreviated as EX), and writing back of results (abbreviated as WB). In the instruction pipeline method, each stage of instruction execution is executed in an overlapping manner. The instruction pipeline system achieves maximum performance when the execution time of each execution stage is the same and equal to a machine cycle, and an operation result is obtained every machine cycle.

Factors that disturb the flow of the instruction pipeline include: ● When the subsequent instruction requires the operation result of the preceding instruction ● When the preceding instruction determines the operand of the subsequent instruction ● When a branch occurs ● When a branch occurs ● Memory ● Access conflict ●When the preceding instruction rewrites the contents of the following instruction ●When an interrupt/exception occurs ●When the instruction is complex and requires multiple machine cycles to execute the operation.

Various efforts have been made to minimize these factors that disturb the instruction pipeline. For example, as a way to suppress pipeline disturbances due to conditional branching, there are programs that use a loop buffer method that uses a large instruction buffer that can store the loop, and multiple instruction streams that process instruction sequences in both cases where the condition is met and when the condition is not met. A branch prediction method that predicts a branch from history information of branch instructions is known.

Recently, in the field of high-performance microprocessors, there has been an effort to simplify the machine instruction set and achieve high-speed processing.
S C (Reduced Instruction 1 on
The approach of ``Set Computer'' is attracting attention.

The RISC approach was born from the analysis of trace results of high-level language programs and the success of the hardwired logic of the Cray-1 supercomputer. The instruction set, which is based on register-register operations, is characterized by emphasis on ● 1 machine cycle execution ● application of the latest compiler technology, and eliminates the need for operand ● address generation (OA). Also,
The simple instruction set simplifies instruction decoding and allows instruction decode (ID) to be included in the operand fetch (OF) stage. Furthermore, the balance of processing at each stage is considered, and as shown in Figure 10, ●Instruction fetcher & operand ●Fetch (IF/
An instruction pipeline has been developed that consists of three stages: ●Instruction Execution (EX) ●Operand ●Write (OW).

In this instruction pipeline, if instruction 1 is a branch instruction,
Instruction 2 can be fetched only after the execution stage (EX) is completed. Therefore, the instruction fetched during the execution of instruction 1 must be invalidated, which leaves one machine cycle vacant in the instruction pipeline, reducing performance.

To minimize this performance degradation, a delayed branching mechanism is utilized. This assumes that a branch instruction is a delayed instruction that is executed one machine cycle after its issuance, as shown in Figure 11, and uses instruction scheduling by the compiler to fill the instruction slot immediately after the branch instruction with a valid instruction. This is intended to eliminate pipeline disturbances and maintain performance. If a valid instruction cannot be embedded in an instruction slot immediately after a branch instruction, a NoP instruction must be embedded in that instruction slot. In this case, of course, there is a reduction in performance.

How many delayed instruction slots can be filled with valid instructions depends on the performance of the compiler. Currently, with modern compiler technology, it is possible to effectively utilize approximately 80 to 90 percent of the delayed instruction slots.

[Problem to be solved by the invention]

(1) In the conventional instruction processing device that employs the above-mentioned vibe line configuration for the first invention, as shown in FIG. 3(b), when instruction 1 is a branch instruction, the following instruction The first stage (IF stage) of No. 2 is made to wait until machine cycle t4 when the EX stage of the branch instruction ends. This is because taking/not taking a branch in a branch instruction and calculating a branch destination address are executed in the EX stage.

Therefore, in the conventional instruction processing device, an empty space is created in the instruction execution pipeline every time a branch instruction is executed. That is, the branch instruction and the subsequent instruction are not executed in parallel, so the maximum execution speed cannot be obtained.

(2) Consider a case where a parallel pipeline instruction processing device is constructed by combining the above-mentioned VLIW method and instruction pipeline method according to the second invention. For example, consider a parallel pipeline instruction processing device that has four instruction pipeline instruction processing devices arranged in parallel and executes a VLIW instruction having four fields.

It is assumed that the instruction pipeline of this parallel pipeline instruction processing device has the same branch delay of one machine cycle as the instruction pipeline of the RISC microprocessor described above. Then, this parallel pipeline instruction processing device has l slots of delayed instruction slots, but since one instruction consists of four instruction fields, there are effectively four instructions' worth of delayed instruction slots. become. Furthermore, the three instruction fields of the instruction itself, including the branch instruction, need to be treated in the same way as the delayed instruction slots in consideration of instruction dependencies. therefore,
This four-parallel pipeline instruction processing device can be considered equivalent to a serial pipeline instruction processing device having seven delay instruction slots.

An instruction schedule that embeds and utilizes valid instructions into such a large number of empty instruction slots. IJ programming is extremely difficult and requires NOP instructions to be embedded in most parts. As mentioned earlier, even the utilization rate of one free instruction slot is 80-90%, and 7
It is extremely difficult to make effective use of empty instruction slots. Therefore, a conventional parallel pipeline and instruction processing device having a branch line configuration in which the branch delay is one machine cycle has the disadvantage that its processing performance is significantly degraded by the execution of a branch instruction.

[Means to solve the problem]

The configuration of the instruction processing device of the first invention has an instruction set that can be executed in a single machine cycle, and includes a first storage means for storing the instructions, a second storage means for storing the operands, and a second storage means for storing the operands. an instruction reading means for reading the instruction from the first storage means; an operand reading means for reading the operands necessary for executing the read instruction from the second storage means; comprising an instruction execution means for executing an instruction using an operand, and an operand writing means for writing the operand obtained as a result of the instruction execution into the second storage means, reading the instruction, reading the operand, execution of said instructions;
The computer system includes a pipeline instruction processing mechanism consisting of writing the operand, further comprising branch address generation means for generating a branch destination address, and the computer system further comprises branch address generation means for generating a branch destination address, and the instruction read from the first storage means by the instruction reading means. is a branch instruction, by simultaneously generating a branch address in the branch address generation means in the machine cycle for reading the operand, the pipeline is prevented from being disturbed when the branch instruction is executed. It is characterized by faster operation.

Further, the configuration of the second invention has an instruction string consisting of a parallel arrangement of n instructions (n is a natural number of n≧2), and includes a first storage means for storing the instruction string, and a first storage means for storing the instruction string; an instruction sequence reading means for reading out the instruction sequence from one storage means; n instruction processing means corresponding to the n instructions in the read instruction sequence and processing instructions specified by the instructions; ,n
n operands used by the instruction processing means are stored; n
n-1 of the instruction processing means;
The instruction processing means includes operand reading means for reading operands necessary for executing the instruction specified by the instruction from the second storage means, and instruction execution means for executing the instruction using the read operands. operand writing means for writing back the operand obtained as a result of instruction execution to the second storage means; a first stage for reading out the instruction string and reading out the operand; and executing processing for the instruction. A pipeline instruction processing mechanism consisting of a second stage to write the operand and a third stage to write the operand executes instructions other than the branch instruction, while processing the remaining one instruction in the instruction processing means. The means includes operand reading means for reading out operands necessary for execution of a conditional branch instruction specified by the instruction from the second storage means, and address generation means for generating an address of an instruction sequence to be executed next, The branch instruction is executed by a branch control mechanism that reads the operand and generates the address in parallel, reads the instruction string, reads the operand, and generates the address in a single machine cycle, and delays the branch. It is characterized by suppressing the increase in the number of empty instruction slots due to

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention, and FIG. 2 is an execution timing chart of FIG. 1.

In FIG. 1, 11 is an instruction fetch means, 12 is an operand fetch means, 13 is an instruction execution means, 14 is an operand write means, 15 is an instruction memory, and 18 is equipped with two read ports and one write port. General-purpose register ● file, 17 is an incrementer that increments the address from which an instruction is fetched by 1, 18 is a manoretic multiplexer, and 19 is a branch address generator that calculates a branch destination address when the instruction fetched by the instruction fetch means 11 is a branch instruction. Means, 101, 102,
105, 109, 110 are instruction buses for transferring fetched instructions; 103, 104, 113 are source operand buses for transferring fetched operands; 108 are destination operand buses for transferring instruction execution results; 107 , 108, 111, and 112 are instruction address paths, 114 and 116 are register address buses, 115 is a register read bus used for operand fetch, and 117 is used in time-sharing for fetching and writing operands. It is a register ● read/write ● bus.

In Figure 2, F is the instruction fetch ● cycle, OF
/BA is an operand fetch/branch address generation cycle, EX is an instruction execution cycle, and OW is an operand write cycle.

The flow of command processing in this embodiment will be explained using FIG. 1 and FIG. 2. Here, the flow of command 1 in FIG. 2 will be explained.

In the first half cycle of the machine cycle t1, the instruction fetch means l1 fetches the instruction address from the instruction address bus 1.
08 to the multiplexer, and the instruction read from the instruction memory 15 is fetched via the instruction bus 109 according to the instruction address sent by the multiplexer via the instruction address bus 107. Here, the instruction address sent by the multiplexer 18 is one of the two instruction addresses obtained from the instruction buses 108 and 111, which is selected depending on the contents of the source Oberand bus 113.

The fetched instruction is transferred to the operand fetch means 12 via the instruction bus 101 at the start of the next machine cycle t2, and if the instruction is a branch instruction, it is transferred to the operand fetch means 12 at the start of the next machine cycle t2. At the timing when a half cycle starts, it is transferred to the branch address generation means 19 via the instruction bus 110. Further, the incrementer 17 adds the value obtained by adding the instruction address of the instruction address bus 107 by one to the instruction address bus 112.
It is sent to the instruction fetch means l1 via the instruction fetch means l1.

The operand fetch means 12 is a machine cycle t
In the second half cycle of 1, based on the instruction transferred via the instruction path 101, the address of the register that fetches the operand is sent to the register●address●buses 114 and 116, and the register is sent from the general register●file l6. Operands are fetched via two buses: ◆Read Bus 115 and Register Read/Write Bus 117.

Once the operand fetch is complete, the instruction passes through instruction path 1.
02, the two fetched operands are transferred to the instruction execution means 13 via source operand buses 103 and 104 at the start of the next machine cycle t2. Further, if the instruction is a branch instruction, operand information that determines whether the branch is taken or not is transferred to the multiplexer 18 via the source Oberand bus 113.

The branch address generation unit l9 generates a machine cycle t
In the second half cycle of 1, a branch destination address generated based on the instruction transferred via the instruction bus 110 is sent to the multiplexer 18.

The instruction execution means 13 includes a source operand bus 103
and using the operands transferred via 104,
The instructions transferred via the instruction bus 102 are executed in one machine cycle (t2). The executed instruction is transferred to the instruction bus 105, and the data obtained as a result of the instruction execution is transferred to the destination operand bus 106 at the start of the next machine cycle t3. ●Transferred to the write means 14.

Operand Write means 14 is machine cycle t3
In the first half cycle of , based on the instruction transferred via the instruction bus 105, the address of the register in which the operand is to be written is sent to the register address bus 6.
Also, the operand transferred via the destination operand bus 106 is sent out via the register read/write bus 117 and written into the general-purpose register file 16. Note that the register write mentioned above is
This is performed during the first half cycle of the machine cycle t3, and the operand write means 14 is performed during the first half cycle of the machine cycle t3.
The latter half cycle is in an idle state.

Each instruction is executed as described above. These operations are superimposed on each machine cycle to form an instruction pipeline.

Now, in FIG. 3(b), when the instruction 1 is a branch instruction, the branch address generation means I9 sends the instruction to the instruction fetch means via the instruction bus 110 in the latter half cycle (OF/BA stage) of t1. A branch destination address is generated based on the instruction transferred from the instruction address bus 111 and sent to the multiplexer 18 via the instruction address bus 111 at the timing when t2 starts. In addition, the operand fetish means l2
source the operand information that determines whether it holds true or not.
It is transferred to the multiplexer 18 via the Oberando bus 113.

In the first half cycle (■F stage) of the first machine cycle (t2) of instruction 2, which is the instruction following the branch instruction, the multiplexer 18 receives the instruction address transferred from the instruction fetch means 11 via the bus 108. instruction address and the instruction address from the branch address generation means 19.
From the two instruction addresses transferred via the bus 111, an appropriate address is selected based on the operand information transferred from the operand fetch means 12 and sent to the instruction address bus 107.

The instruction fetch means 11 receives the instruction read from the instruction memory 15 according to the instruction address sent by the multiplexer via the instruction address bus 107.
Fetch via 9.

In other words, the instruction fetch ● cycle for instruction 2 is
It can be executed in cycle t2.

Therefore, since there is no empty space in the instruction execution pipeline between a branch instruction and a subsequent instruction, the instructions can be executed in parallel.

By the way, in the instruction pipeline of this embodiment, as shown in FIG. 2, the OW cycle of instruction 1 and the OW cycle of instruction 3 are
Since the F/BA cycle operates at mutually exclusive timing, the bus connecting the general-purpose register file 16, the operand fetch means 12, and the operand write means 14 can be shared.

It goes without saying that the present invention is not limited to the above-described embodiments, but can be realized with other suitable configurations.

Next, the second invention will be explained with reference to the drawings.

FIG. 4 is a block diagram of an embodiment of the present invention in the case of n=4, and is a parallel pipeline instruction that executes four instructions in parallel using a VLIW type parallel instruction sequence consisting of four instructions. This figure shows the configuration of the processing device.

In FIG. 4, 411 is an instruction string memory, 412 is an instruction string fetch means, 413 is a data register with 8 read ports and 4 write ports, 414 to
417 is operand fetch means, 418 is address generation means for generating the address of the instruction string to be fetched next, 419 to 421 are instruction execution means, 422 to 425 are operand write means, and 4101 is for fetching the instruction string. Instruction string path, 4102 is address bus, 41
03 to 4106 are instruction buses that transfer fetched instructions, 4107 to 4110 are two register read buses used to fetch operands necessary for executing instructions,
4111 to 4114 are two source Oberand buses that transfer fetched operands, 4115 to 411
8 is a destination *operand* bus for transferring the instruction execution results, and 4119 to 4122 are register *write* buses used for writing operands.

FIG. 5 shows the instruction format of the parallel pipeline instruction processing device having the configuration shown in FIG.

FIG. 7 is a diagram showing the structure of the vibration line of the second invention. The meanings of the abbreviations in the figure are as follows.

IF...Instruction string fetch OF...Operand Fetch AG...Address generation EX...Instruction execution OW...Write Back Figure 8 is an example of a program sequence that includes a conditional branch instruction. FIG. 9 is a diagram showing the operation of the instruction pipeline in the second invention, and shows the pipeline operation when the program ● sequence shown in FIG. 8 is executed.

In FIG. 9, IF represents instruction string fetch, OF represents operand fetch, AG represents branch address generation, operations 1 to 6 and operations 10 to 12 execute respective instructions, and WB represents operand write back.

First, the operation when a sequence of instructions is executed will be explained using FIGS. 4 and 5.

The instruction string fetch means 412 uses the address bus 4102
The instruction string specified by is fetched from the instruction string memory 411 via the instruction string bus 4101. The instruction string fetching means 412 fetches instruction 1, instruction 2, . . . shown in FIG. Each instruction of instruction 3 and branch instruction is 4103 and 4104, respectively.
, 4105 and 4106 to operand fetch means 414 to 417 and address generation means 418, respectively.

Next, the operand fetch means 414 to 417 are
Decode each transferred instruction and write the operands used in each instruction to each register ● Read ● Buses 4107 to 411
Fetch data from register 413 via 0.

The operand fetch means 414 to 416 respectively transfer the fetched operands to the source Oberand bus 4.
112 to 4114 respectively to instruction execution means 419.
Transfer to ~421. On the other hand, the operand fetch means 417 transfers the fetched operand to the address generation means 418 via the source operand bus 4111. The operations up to this point are the same for all instruction processing.

The instruction execution means 419 to 421 execute the source●operand●
Each instruction is executed using the operands transferred via buses 4112 to 4114, and each execution result is sent to the destination ● Operand ● Bus 4116 to
Operand write means 423 to 42 via 4118
Transfer to 5.

Operand write means 423 to 425 write each result operand back to the register specified by each instruction via register write buses 4119 to 4121, respectively.

On the other hand, the address generating means 418 increments the internally held instruction string address and generates the next address. At the same time, it decodes the branch instruction given via the instruction bus 4106 and generates a branch destination address. Then, by referring to the operand given via the source Oberando bus 4l11, the branch condition is satisfied/
It is determined whether the branch is not taken, and if a branch occurs, the branch destination address is output to the address bus 4102, and if the branch does not occur, the next address is output to the address bus 4102. In addition, in the case of a branch instruction that simultaneously stores the next address in a register, that is, a branch ●and●link instruction, the branch destination address is output to the address bus 4102, and the next address is output to the destination bus 4102. ●Operand●Transferred to the write means 22 via the bus 4115. Then, the operand write means 422 writes the next address to the register write bus 412.
The data is written back to the register 13 via 2.

The timing of the processing described above will be explained using FIG. FIG. 6 is a diagram showing the flow of processing when one instruction sequence is executed. The processing on the 1st to 3rd lines corresponds to the processing of commands - command (2). Processing over the bottom two lines corresponds to branch instruction processing. In FIG. 4, the timing at which the instruction string fetch means 412 fetches the instruction string corresponds to IF. Similarly, the operands are fetched from registers by the fetch means 414 to 417, the next address and branch address are generated by the address generation means 418, the instructions are executed by the instruction execution means 419 to 421, and the operands are written by the write means 422 to 42.
The timing of operand write to the register by No. 5 corresponds to OF, AG, EX, and WB, respectively.

Now, the parallel pipeline instruction processing device of this embodiment is the seventh
Let us consider the case of processing the program●sequence shown in the figure. In this sequence, instruction string 2 includes a conditional branch instruction, and when the condition is met, the sequence changes to instruction string 2.
Branches to instruction sequence A from .

FIG. 8 shows the operation of the pipeline when the sequence of FIG. 7 is executed. In the processing of instruction sequence 2, the pipeline that processes the branch field executes generation of the next address and branch destination address in parallel while fetching the operand, and using the contents of the fetched operand. At the end of the t2 cycle, it is possible to determine whether to use the next address or the branch destination address and output it to the address bus 4l02.

Therefore, processing of instruction A can be started from cycle t3.

Therefore, even when executing a sequence of instructions that includes a branch, there is no empty space in the pipeline, and the number of empty instruction slots that the compiler must fill can be reduced compared to conventional systems, resulting in highly efficient parallel Vibration instruction processing. The device can be realized.

For example, on a conventional device with a branch delay of one machine cycle, the compiler may
It is necessary to embed valid instructions in the three instruction slots of instruction 6 and the three instruction slots in the subsequent delayed instruction sequence, for a total of six instruction slots. In contrast, in the parallel pipeline instruction processing device of this embodiment, it is sufficient to fill three instruction slots, instructions 4 to 6, with valid instructions.

It goes without saying that the present invention is not limited to the above-described embodiments and can be realized with other suitable configurations.

〔Effect of the invention〕

As explained above, in the first invention, even when a branch instruction is executed in a pipelined computer, instructions are executed in parallel without disrupting the pipeline operation, so that instruction execution can be speeded up. Furthermore, since the bus used for reading/writing general-purpose registers can be used in a time-sharing manner and shared, the amount of hardware can be reduced.

Furthermore, as explained above, the parallel pipeline instruction processing device of the second invention does not create empty slots for instructions due to instruction sequences with branch instructions, so it is possible to use simple hardware and parallel instruction scheduling during compilation. The effect is that it is possible to realize a highly efficient parallel pipeline instruction processing device that combines VLIW type parallel processing that realizes parallel processing and high-speed processing using the instruction pipeline method. This has the effect of facilitating parallel instruction scheduling because the number of empty instruction slots that would otherwise be required can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention, FIG. 2 is a timing diagram of the pipeline in FIG. 1, and FIG.
FIG. 3(a) is a timing diagram of a pipeline of a conventional instruction processing device, FIG. 3(b) is a timing diagram of a branch instruction pipeline in a conventional instruction processing device, and FIG. 4 is a timing diagram of a branch instruction pipeline in a conventional instruction processing device.
FIG. 5 is a block diagram showing the configuration of an embodiment of the second invention in the case of FIG. Figure 7 is a diagram of a program sequence including a conditional branch instruction, Figure 8 is a diagram showing the operation of the instruction pipeline when the instruction shown in Figure 7 is executed, Figure 9 is a diagram showing the operation of the instruction pipeline when the instruction shown in Figure 7 is executed. A diagram showing the principle of a VLIW parallel computer,
Fig. 10 is a diagram showing an instruction pipeline of a conventional serial instruction processing device, Fig. 11 is a diagram showing the operation when a branch occurs in the conventional pipeline, and Fig. 12 is a diagram showing the operation of a delayed branch instruction in the conventional pipeline. It is a diagram showing the operation. AG... address generation, EX... instruction execution cycle, IF... instruction fetch ● cycle, OF... register ● fetch ● cycle, OW... register ● write ● cycle, 11... instruction fetch Means, 12...
・Operand ● Fetching means, 13... Instruction execution means, 14... Operand ● Writing means, 15... Instruction memory, 16... General purpose register ● File, 17...
・Incrementer, 18... Manorreciplexer, 19
...branch address generation means, 101-102...instruction bus, 103-104 source●operand●bus,
105...Instruction bus, 106...Destination●operand●bus, 107-108...instruction address●bus, 109-110...instruction bus, 111-
112...Instruction address●bus, 113...Source●operand●bus, 114...register●address●bus, 115...register●read●bus, 116
...Register●Address●Bus, 117...Register●Read/Write●Bus, 411...Instruction string memory, 412...Instruction string fetch means, 413...Data●Register, 414-417. ...Operand●Fetch means, 418...Address generation means, 419-4
21... Instruction execution means, 422-425... Operand●Write means, 4101... Instruction string bus, 410
2...Address●Bus, 4103-4106...Instruction bus, 4107-4110...Register●Read●
Bus, 4111 to 4114... Source ● Operand ●
Bus, 4115-4118...Destination Chiron●
Operand●Noce, 4119-4122...Register●Write●Noise.

Claims (1)

[Claims] 1. A first storage means having a set of instructions that can be executed in a single machine cycle and storing the instructions, a second storage means storing operands, and the first storage means; an instruction reading means for reading the instruction from the second storage means; an operand reading means for reading an operand necessary for executing the read instruction from the second storage means;
comprising an instruction execution means for executing an instruction using the read operand, and an operand writing means for writing the operand obtained as a result of the instruction execution into the second storage means, reading the instruction; The computer system includes a pipeline instruction processing mechanism that reads the operand, executes the instruction, and writes the operand. If the instruction read by the instruction reading means is a branch instruction, the branch address generation means generates a branch address at the same time in the machine cycle of reading the operand, so that the pipe at the time of execution of the branch instruction is An instruction processing device characterized by eliminating line disturbances and speeding up pipeline operation. 2. A first storage means that has an instruction sequence consisting of a parallel arrangement of n instructions (n is a natural number of n≧2), and stores the instruction sequence; and a first storage means that stores the instruction sequence from the first storage means; n instruction processing means for processing instructions specified by the instructions corresponding to the n instructions in the read instruction string; and n instruction processing means for processing the instructions specified by the instructions. an instruction processing device for processing n instructions in parallel, comprising a second storage means for storing operands used by the n instruction processing means and readable/writable independently from the n instruction processing means; The n-1 instruction processing means in the means are
operand reading means for reading operands necessary for execution of the instruction specified by the instruction from the second storage means; instruction execution means for executing the instruction using the read operands; operand writing means for writing back the operand to the second storage means; a first stage for reading out the instruction sequence and reading out the operand; a second stage for executing processing of the instruction; A pipeline instruction processing mechanism consisting of a third stage for writing operands executes instructions other than branch instructions, while the remaining one of the instruction processing means executes instructions specified by the instruction. operand reading means for reading out operands necessary for execution of a conditional branch instruction to be executed from the second storage means; and address generation means for generating an address of an instruction sequence to be executed next; A branch control mechanism executes generation in parallel, reads the instruction string, reads the operand, and generates the address in a single machine cycle. An instruction processing device characterized by being suppressed.