JP2861234B2 - Instruction processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The first and second inventions relate to an instruction processing device of an information processing device, and in particular, the first invention relates to a single machine having a pipeline instruction processing mechanism. The second invention relates to a parallel instruction processing device for executing a plurality of instructions in parallel and a pile line instruction processing device for realizing high-speed processing using a pipeline mechanism.

[Conventional technology]

(1) In the prior art of the first invention, computers with various pipeline configurations have been developed with the advancement of computer systems. However, in order to speed up machine cycles, operand reading and operand In many cases, a pipeline method is used, in which each write is positioned in one pipeline stage. In this type of pipeline system, as shown in the timing chart of the pipeline of the conventional instruction processing device in FIG. 3A, instruction fetch from memory (abbreviated as IF stage); Operand fetch (abbreviated as OF stage), instruction execution (abbreviated as EX stage), operand write to general-purpose register file (OW
A pipeline is composed of four stages. Since the processing of each stage of the pipeline can be executed in one machine cycle, an instruction can be executed every machine cycle. Further, since each process is subdivided, the machine cycle itself can be sped up. Therefore, a high-performance instruction processing device can be provided.

(2) Further, in the conventional technique according to the second invention, there is the following technique.

(A) VLIW type parallel computer The VLIW (Very Long Instruction Word) method distributes a relatively long instruction into many fields as shown in FIG. 9 and a large number of arithmetic units, registers, and interconnections in each field. The parallel processing is realized by independently controlling the network, the memory, and the like.

In the VLIW method, the parallelism of the operation is extracted at the time of compiling, and the compiler synthesizes an instruction that can be operated in parallel into one instruction. When a degree of parallelism close to the number of parallel computing units is obtained, high-speed processing can be achieved. However, when the degree of parallelism is low, the instruction field becomes empty, and the bit usage efficiency of the instruction decreases. The extent to which the instruction field can be filled depends on the capabilities of the compiler and the source program.

In the VLIW method, since the parallelism of a program is extracted at the time of compilation, there is no need to perform complicated processing such as detection of data dependency. Therefore, the hardware configuration can be simplified.

The VLIW method is based on a concept derived from the horizontal microinstruction method, and is suitable for fine-grained parallel processing (low-level parallel processing) using an arithmetic unit with a low function level.

(B) Instruction pipeline processing The machine instruction execution process in the computer system includes instruction fetch (read: abbreviated as IF), instruction decode (decoding:
ID), operand address generation (abbreviated as OA),
This is performed by sequentially performing operand fetch (abbreviated as OF), execution of an operation (abbreviated as EX), and writing back of the result (abbreviated as WB). In the instruction pipeline system, each stage of the instruction execution is executed in an overlapping manner. When the execution time of each execution stage is the same and is equal to a machine cycle, the instruction pipeline method performs the best, and the operation result is obtained every machine cycle.

Factors that disrupt the flow of the instruction pipeline include:-When the operation result of the preceding instruction is required by the subsequent instruction-When the preceding instruction determines the operand address of the subsequent instruction-When a branch occurs-Memory access conflict • When the preceding instruction rewrites the contents of the following instruction. • When an interrupt / exception occurs. • There are cases where the instruction is complicated and requires more than one machine cycle to execute the operation.

Various schemes have been devised to minimize the factors that disrupt these instruction pipelines. For example, as a device for suppressing pipeline disruption due to conditional branching, a loop buffer system using a large instruction buffer capable of storing a program loop, a multi-instruction flow for processing an instruction sequence when both conditions are satisfied and conditions are not satisfied, and so on. method,
A branch prediction method for predicting a branch from history information of a branch instruction is known.

In recent high-performance microprocessors, RISC seeks to simplify machine instruction sets and achieve high-speed processing.
(Reduced Instruction Set Computer) approach is attracting attention.

RISC's approach stems from the analysis of trace results in high-level language programs and the success of the hardwired logic of the supercomputer Cray-1. ・ Simple instruction set based on register-register operation ・ Pipeline Emphasis ・ One machine cycle execution ・ The latest compiler technology is applied.
Operand address generation (OA) is no longer required, and access to main memory in operand fetch (OF) is no longer required. The simple instruction set also simplifies instruction decoding, speeds up by applying hardwired logic, and allows instruction decoding (ID) to be included in the operand fetch (OF) stage. Furthermore, considering the balance of processing in each stage, as shown in Fig. 10, it consists of three stages:-instruction fetch & operand fetch (IF / OF)-instruction execution (EX)-operand write (OW) An instruction pipeline has been developed.

In this instruction pipeline, if the instruction 1 is a branch instruction, the instruction 2
Can be fetched. Therefore, the instruction fetched during the execution of instruction 1 needs to be invalidated, resulting in a vacancy of one machine cycle in the instruction pipeline, which degrades the performance.

To minimize this performance degradation, a delay branching mechanism is used. This is because, as shown in FIG. 11, a branch instruction is regarded as a delayed instruction executed one machine cycle after its issuance, and the instruction slot immediately after the branch instruction is filled with valid instructions by instruction scheduling by the compiler. In this way, it is intended to eliminate the disturbance of the pipeline and maintain the performance. If a valid instruction cannot be embedded in the instruction slot immediately after the branch instruction, it is necessary to embed a NOP instruction in that instruction slot. In this case, of course, there is a decrease in performance.

How many delayed instruction slots can be filled with valid instructions depends on the performance of the compiler. Current,
With the latest compiler technology, about 80-90% of the delay instruction slot can be used effectively.

[Problems to be solved by the invention]

(1) In the conventional instruction processing apparatus employing the above-described pipeline configuration for the first invention, as shown in FIG. 3 (b), when instruction 1 is a branch instruction, the instruction is a continuation instruction. The first stage (IF stage) of the second instruction is
It is waited until the machine cycle t4 when the EX stage ends. This is because the branch taken / not taken in the branch instruction and the calculation of the branch destination address are executed in the EX stage.

Therefore, in the conventional instruction processing device, every time a branch instruction is executed, an empty space is created in the instruction execution pipeline. That is, there is a disadvantage that the maximum execution speed cannot be obtained because the branch instruction and the following instruction are not executed in parallel.

(2) Consider a case in which the VLIW method and the instruction pipeline method described above for the second invention are combined to form a parallel pipeline instruction processing device. For example, consider a parallel pipeline instruction processing device that arranges four instruction pipeline type instruction processing devices in parallel and executes a VLIW type instruction having four fields.

It is assumed that the instruction pipeline of this parallel pipeline instruction processing device has the same branch delay of one machine cycle as the instruction pipeline of the RISC microprocessor described above. Then, this parallel pipeline instruction processing device has one delay instruction slot, but one delay instruction slot.
Since the instruction consists of four instruction fields,
Effectively, a delay instruction slot for four instructions is generated. Furthermore, the three instruction fields of the instruction itself including the branch instruction also need to be treated in the same manner as the delay instruction slot in consideration of the instruction dependency. Therefore, this four-parallel pipeline instruction processor can be considered to be equivalent to a serial pipeline instruction processor having seven delay instruction slots.

Instruction scheduling that embeds and uses valid instructions in such a large number of empty instruction slots is extremely difficult, and almost all parts must be filled with NOP instructions. As described above, even the utilization rate of one empty instruction slot is 80 to 90%, and it is extremely difficult to effectively use seven empty instruction slots. Therefore, the parallel pipeline instruction processing device having the conventional pipeline configuration in which the branch delay is one machine cycle has a disadvantage that the processing performance is significantly reduced by the execution of the branch instruction.

[Means for solving the problem]

The configuration of the instruction processing apparatus of the first invention has an instruction set that can be executed in a single machine cycle, and stores a first storage unit for storing the instruction, a second storage unit for storing operands, Instruction reading means for reading the instruction from the first storage means, operand reading means for reading from the second storage means an operand required to execute the read instruction, An instruction execution unit for executing an instruction using an operand; and an operand writing unit for writing the operand obtained as a result of the instruction execution to the second storage unit, wherein reading of the instruction and reading of the operand are performed. A pie comprising a first stage to execute, a second stage to execute the processing of the instruction, and a third stage to execute the writing of the operand A computer system having a line instruction processing mechanism, further comprising a branch address generating means for generating a branch destination address, wherein the instruction read by the instruction reading means from the first storage means is a branch instruction In the first stage, the reading of the operand and the generation of the branch address by the address generation means are performed simultaneously to eliminate disturbance of the pipeline operation at the time of execution of the branch instruction and to speed up the pipeline operation. Features.

Further, the configuration of the second invention has an instruction sequence composed of a parallel arrangement of n instructions (n is a natural number of n ≧ 2), and a first storage means for storing the instruction sequence; An instruction sequence reading unit for reading the instruction sequence from one storage unit; and n instruction processing units corresponding to the n instructions in the read instruction sequence and processing an instruction specified by the instruction. ,
storing n operands used by the instruction processing means;
a second storage means readable / writable independently of the n instruction processing means, wherein the instruction processing apparatus processes n instructions in parallel;
One instruction processing means includes an operand reading means for reading, from the second storage means, an operand necessary for executing the instruction specified by the instruction, and an instruction execution means for executing the instruction using the read operand. And an operand writing means for writing back the operand obtained as a result of the instruction execution to the second storage means, a first stage for executing the reading of the instruction sequence and the reading of the operand, and the processing of the instruction. The second stage to perform,
An instruction other than a branch instruction is executed by a pipeline instruction processing mechanism comprising a third stage for executing the writing of the operand, while the remaining one in the instruction processing means is executed.
The instruction processing means includes: operand reading means for reading, from the second storage means, operands necessary for executing a conditional branch instruction specified by the instruction; generation of an address of a next instruction sequence and generation of a branch destination address And an address generating means for executing the instruction in parallel, and when the instruction read by the instruction reading means from the first storage means is a branch instruction, reading the operand in the first stage and By simultaneously executing the generation of the address of the branch destination, disturbance of a pipeline operation at the time of execution of a branch instruction due to a branch delay is eliminated, and an increase in empty instruction slots due to the branch delay is suppressed.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of the first invention, and FIG. 2 is an execution timing chart of FIG.

In FIG. 1, 11 is instruction fetch means, 12 is operand fetch means, 13 is instruction execution means, 14 is operand write means, 15 is instruction memory, 16 is provided with two read ports and one write port. General register file, 17 is an incrementer that increments the address to fetch an instruction by 1, 18 is a multiplexer,
19 is a branch address generating means for calculating a branch destination address when the instruction fetched by the instruction fetch means 11 is a branch instruction, 101, 102, 105, 109 and 110 are instruction buses for transferring fetched instructions, and 103, 104 and 113 are source operands for transferring fetched operands. A bus, 106 is a destination operand bus for transferring an instruction execution result, 107, 108, 111, 112 are an instruction address bus, 11
4,116 is the register address bus, 115 is the operand
A register read bus 117 used for fetching is a register read / write bus 117 used in time division for fetching and writing operands.

In FIG. 2, IF is an instruction fetch cycle, OF / B
A is an operand fetch / branch address generation cycle, EX is an instruction execution cycle, and OW is an operand write
It is a cycle.

The flow of instruction processing in this embodiment will be described with reference to FIGS. Here, the instruction 1 in FIG.
Will be described.

The instruction fetch means 11 transmits the instruction address to the instruction address bus 108 in the first half cycle of the machine cycle t1.
And outputs the instruction read from the instruction memory 15 by the instruction address transmitted by the multiplexer via the instruction address bus 107.
Fetch via 109. Where multiplexer 1
The instruction addresses sent by 8 are the instruction buses 108 and 111
Is one of the two instruction addresses selected according to the contents of the source operand bus 113.

At the timing when the next machine cycle t2 starts, the fetched instruction receives the operand
In addition to being transferred to the fetch means 12, when the instruction is a branch instruction, the instruction is transferred to the branch address generation means 19 via the instruction bus 110 at the timing when the latter half cycle of the machine cycle t1 starts. Also, incrementer 17
Sends the value obtained by adding one to the instruction address of the instruction address bus 107 to the instruction fetch means 11 via the instruction address bus 112.

The operand fetch means 12 is provided for the machine cycle t1.
In the latter half cycle of the instruction, the address of the register from which the operand is fetched is changed based on the instruction transferred through the instruction bus 101, by using the register address buses 114 and 116.
To the register read bus 115 and the register read / write bus 117 from the general-purpose register file 16.
Fetch the operand via the two buses.

When the operand fetch is complete, the instruction is placed on the instruction bus.
The two fetched operands are transferred to the instruction execution means 13 via the source operand buses 103 and 104 at the timing when the next machine cycle t2 starts. When the instruction is a branch instruction, operand information for determining whether a branch is taken / not taken is transferred to the multiplexer 18 via the source operand bus 113.

The branch address generation unit 19 executes the machine cycle t1
In the latter half cycle, the branch destination address generated based on the instruction transferred via the instruction bus 110 is sent to the multiplexer 18.

The instruction executing means 13 executes the instruction transferred via the instruction bus 102 in one machine cycle (t2), using the operand transferred via the source operand buses 103 and 104. The instruction whose execution has been completed is sent to the instruction bus 10
5, and the data obtained as a result of the instruction execution are transferred to the operand writing means 14 via the destination operand bus 106 at the timing when the next machine cycle t3 starts.

The operand write means 14 sends the address of the register to which the operand is to be written to the register address bus 116 based on the instruction transferred via the instruction bus 105 in the first half cycle of the machine cycle t3, and Operands transferred via destination operand bus 106 are transferred to register read / write bus
Transmit via 117 and write to general register file 16. Note that the above-described register write is performed during the first half cycle of the machine cycle t3, and the operand
The write means 14 is in the idle state in the latter half cycle of the machine cycle t3.

Each instruction is executed by the operation described above. These operations are superimposed on each machine cycle to form an instruction pipeline.

In FIG. 2, when the instruction 1 is a branch instruction, the branch address generation unit 19 transfers the instruction from the instruction fetch unit 11 via the instruction bus 110 in the latter half cycle (OF / BA stage) of t1. A branch destination address is generated based on the executed instruction, and the instruction address and the
The signal is sent to the multiplexer 18 via the bus 111. At this time, in the conventional example of FIG. 3 (b), the generation of the branch destination address had to be started after waiting for the EX stage in which the arithmetic unit became usable. Because of this, the generation of branch addresses can be completed in the OF / BA stage. Further, the operand fetch means 12 transfers operand information for determining whether the condition is satisfied / not satisfied to the multiplexer 18 via the source operand bus 113.

The first machine of instruction 2, which is the instruction following the branch instruction
In the first half cycle (IF stage) of the cycle (t2), the multiplexer 18 controls the instruction address transferred from the instruction fetch means 11 via the instruction address bus 108 and the instruction address bus 11 from the branch address generation means 19.
An appropriate address is selected from the two instruction addresses of the instruction addresses transferred via 1 according to the operand information transferred from the operand fetch means 12 and transmitted to the instruction address bus 107. Instruction fetch means 11
The multiplexer fetches the instruction read from the instruction memory 15 by the instruction address sent out via the instruction address bus 107 via the instruction bus 109. That is, the instruction fetch cycle of the instruction 2 can be executed in the machine cycle t2.

Therefore, even between the branch instruction and the succeeding instruction, there is no space in the instruction execution pipeline, so that the instructions can be executed in parallel.

By the way, in the instruction pipeline of this embodiment,
As shown in FIG. 2, since the OW cycle of instruction 1 and the OF / BA cycle of instruction 3 operate at mutually exclusive timings, the general-purpose register file
The bus connecting the operand fetch means 12 and the operand fetch means 14 with the bus 16 can be shared.

It is needless to say that the present invention is not limited to the above-described embodiment, but can be realized by other appropriate configurations.

 Next, the second invention will be described with reference to the drawings.

FIG. 4 is a block diagram of one embodiment of the present invention when n = 4. A parallel pipeline instruction for executing four instructions in parallel by a VLIW type parallel instruction sequence composed of four instructions. 2 shows a configuration of a processing device.

In FIG. 4, reference numeral 411 denotes an instruction sequence memory; 412, an instruction sequence fetch means; 413, a data register having eight read ports and four write ports; 414 to 417, operand fetch means; Address generating means for generating an address of an instruction sequence to be executed, 419 to 421 are instruction executing means, 422 to 425 are operand writing means, 4101
Is an instruction sequence bus for fetching instruction sequences, 4102 is an address bus, 4103 to 4106 are instruction buses for transferring fetched instructions, and 4107 to 4110 are two instruction buses used for fetching operands necessary for executing the instructions. Register read bus,
4111 to 4114 are two source operand buses for transferring fetched operands, 4115 to 4118 are destination operand buses for transferring instruction execution results, 41
19 to 4122 are registers used for writing operands.
It is a light bus.

FIG. 5 shows an instruction format of the parallel pipeline instruction processing device having the configuration of FIG.

FIG. 6 is a diagram showing the structure of the pipeline of the second invention. The meanings of the abbreviations in the figure are as follows.

IF: instruction sequence fetch OF: operand fetch AG: address generation EX: instruction execution OW: write back FIG. 7 is a diagram showing an example of a program sequence including a conditional branch instruction, and FIG. FIG. 8 is a diagram showing the operation of the instruction pipeline in the invention, and shows the pipeline operation when executing the program sequence shown in FIG. 7;

 In FIG. 8, IF denotes an instruction sequence fetch, OF denotes an operand fetch, AG denotes a branch address generation, operations 1 to 6 and operations 10 to 12 execute respective instructions, and WB denotes an operand write back.

First, an operation when an instruction sequence is executed will be described with reference to FIGS. 4 and 5.

The instruction sequence fetch means 412 stores the instruction sequence specified by the address bus 4102 from the instruction sequence memory 411 into the instruction sequence bus 410.
Fetch through one. The instruction sequence fetch means 412 transfers the instructions 1, 2, 3, and branch instructions shown in FIG. 5 to the operand fetch means 414 to 417 via instruction buses 4103, 4104, 4105 and 4106, respectively. And to the address generation means 418.

Next, the operand fetch means 414 to 417 decode the transferred instructions and fetch the operands used in each instruction from the data register 413 via the register read buses 4107 to 4110, respectively. Operand fetch means 414 to 416 transfer fetched operands to instruction execution means 419 to 421 via source operand buses 4112 to 4114, respectively. On the other hand, the operand fetch means 417 outputs the fetched operand to the address generation means via the source operand bus 4111.
Transfer to 418. The operation so far is the same for all instruction processing.

Instruction execution means 419 to 421 are provided by a source operand bus
The respective instructions are executed using the operands transferred via 4112 to 4114, and the respective execution results are transferred to operand writing means 423 to 425 via destination operand buses 4116 to 4118. operand·
The write means 423 to 425 rewrite each result operand to a register designated by each instruction via the register write buses 4119 to 4121.

On the other hand, the address generation means 418 increments the instruction sequence address held therein to generate a next address. At the same time, it decodes the branch instruction given via the instruction bus 4106 and executes generation of a branch destination address. Then, with reference to the operand given via the source operand bus 4111, it is determined whether the branch condition is satisfied or not. If a branch occurs, the branch destination address is set.
If no branch occurs, the next address is output to address bus 4102. When the branch instruction involves an operation of storing the next address in a register at the same time, that is, in the case of a branch and link instruction, the branch destination address is output to the address bus 4102 and the next address is stored in the destination bus. The data is transferred to the operand writing means 422 via the operand bus 4115. Next, the operand write means 422 writes the next address as an operand back to the data register 413 via the register write bus 4122.

The timing of the above-described processing will be described with reference to FIG. FIG. 6 is a diagram showing a flow of processing when one instruction sequence is executed. The processing of the first to third lines corresponds to the processing of the instructions I to III. The processing over the two lowermost lines corresponds to the processing of the branch instruction. The timing at which the instruction sequence fetch means 412 fetches an instruction sequence in FIG. 4 corresponds to the IF. Similarly, operand fetch means
Fetching operands from registers by 414-417,
The address generation unit 418 generates the next address and the branch destination address, the instruction execution units 419 to 421 execute the instruction, and the operand write units 422 to 425 adjust the operand write timing to the register by OF, AG, and EX, respectively.
And WB.

Now, consider the case where the parallel pipeline instruction processing apparatus of the present embodiment processes the program sequence shown in FIG. In this sequence, the instruction sequence 2 includes a conditional branch instruction, and the sequence branches from the instruction sequence 2 to the instruction sequence A when the condition is satisfied.

FIG. 8 shows the operation of the pipeline when the sequence of FIG. 7 is executed. In the processing of instruction sequence 2, the pipeline for processing the branch field includes operands
At the same time as the fetch, the generation of the next address and the generation of the branch destination address are executed in parallel, and the next address or the branch destination address is used at the end of the t2 cycle using the contents of the fetched operand. Can be determined and output to the address bus 4102. Therefore, the processing of the instruction A can be started from the cycle t3.

Therefore, even when an instruction sequence including a branch is executed, there is no vacancy in the pipeline, and the number of vacant slots of instructions that must be filled by the compiler can be reduced as compared with the conventional one, and parallel pipeline instruction processing with high efficiency can be achieved. The device can be realized.

For example, in a conventional device having a branch delay of one machine cycle, in order to obtain the maximum performance, the compiler uses three instruction slots of instructions 4 to 6 and three instruction slots in the following delayed instruction sequence, for a total of six. A valid instruction must be embedded in one instruction slot. On the other hand, in the parallel pipeline instruction processing device of the present embodiment, three instruction slots of instructions 4 to 6 need only be filled with valid instructions.

It is needless to say that the present invention is not limited to the above-described embodiment, but can be realized by another appropriate configuration.

〔The invention's effect〕

As described above, in the first aspect, in the pipeline computer, even when a branch instruction is executed, the instructions are executed in parallel without disturbing the pipeline operation, so that the speed of instruction execution can be increased. There is an effect that the bus used for reading / writing of the general-purpose register can be shared in a time-sharing manner, so that the amount of hardware can be reduced.

Further, as described above, the parallel pipeline instruction processing device according to the second aspect of the present invention uses simple hardware and parallel instruction scheduling at compile time because there is no occurrence of an empty slot of instructions due to an instruction sequence having branch instructions. It has the effect of realizing a highly efficient parallel pipeline instruction processing device that combines VLIW type parallel processing that realizes parallel processing and high-speed processing by the instruction pipeline method. Since the number of unused instruction slots that can be reduced can be reduced, there is an effect that parallel instruction scheduling becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the first invention, FIG. 2 is a timing chart of the pipeline of FIG. 1, and FIG. 3 (a) is a timing of a pipeline of a conventional instruction processing device. FIG. 3 (b) is a timing diagram of a pipeline of a branch instruction in the conventional instruction processing device, and FIG.
4 is a block diagram showing the configuration of an embodiment of the second invention, FIG. 5 is a diagram showing an instruction format of a parallel pipeline instruction processing device having the configuration of FIG. 4, and FIG. FIG. 7 is a diagram showing a pipeline of the invention, FIG. 7 is a diagram of a program sequence including a conditional branch instruction, FIG. 8 is a diagram showing operation of the instruction pipeline when the instruction shown in FIG. 7 is executed, FIG. Is a diagram showing the principle of a VLIW parallel computer,
FIG. 10 is a diagram showing an instruction pipeline of a conventional serial instruction processor, FIG. 11 is a diagram showing an operation when a branch occurs in a conventional pipeline, and FIG. 12 is an operation of a delayed branch instruction in a conventional pipeline. FIG. AG: Address generation, EX: Instruction execution cycle, IF:
Instruction fetch cycle, OF: Register fetch
Cycle, OW ... Register write cycle, 11 ...
Instruction fetch means, 12 ... Operand fetch means,
13 ... instruction execution means, 14 ... operand write means,
15 ... Instruction memory, 16 ... General purpose register file, 17
... Incrementer, 18 multiplexer, 19 branch address generating means 101-102 instruction bus, 108-104
... source operand bus, 105 ... instruction bus, 106
…… Destination operand bus, 107-108
…… Instruction address bus, 109 to 110 …… Instruction bus, 111
... 112 Instruction address bus, 113 Source operand bus, 114 Register address bus, 115
... Register read bus, 116 ... Register address bus, 117 ... Register read / write bus, 4
11 ... instruction string memory, 412 ... instruction string fetch means, 413
... data register, 414 to 417 ... operand fetch means, 418 ... address generation means, 419 to 421 ... instruction execution means, 422 to 425 ... operand write means, 41
01: Instruction string bus, 4102: Address bus, 4103 to 41
06 Instruction bus, 4107-4110 Register read bus, 4111-4114 Source operand bus, 4115-
4118 …… Destination operand bus, 4119
~ 4122 ... Register write bus.

Claims (2)

(57) [Claims] An instruction set that can be executed in a single machine cycle; a first storage means for storing the instruction; a second storage means for storing operands; Command reading means for reading a command;
An operand reading means for reading an operand necessary to execute the read instruction from the second storage means, an instruction executing means for executing an instruction using the read operand, A operand writing means for writing the obtained operand to the second storage means, a first stage for executing the reading of the instruction and reading of the operand, and a second stage for executing the processing of the instruction. In a computer system including a pipeline instruction processing mechanism comprising a stage and a third stage for executing the writing of the operand, the computer system further comprises a branch address generating means for generating a branch destination address, and the first storage means If the instruction read from the instruction reading means is a branch instruction,
In the first stage, the reading of the operand and the generation of the branch address by the address generation means are performed simultaneously, thereby eliminating disturbance of the pipeline operation at the time of execution of the branch instruction and speeding up the pipeline operation. Instruction processing unit. 2. An apparatus according to claim 1, further comprising: a first storage unit for storing an instruction sequence comprising a parallel arrangement of n instructions (n is a natural number of n ≧ 2); Instruction string reading means for reading the instruction string, n instruction processing means corresponding to n instructions in the read instruction string, and processing an instruction specified by the instruction; An instruction processing device for storing operands used by the instruction processing means and having a second storage means readable / writable independently of the n instruction processing means, and for processing the n instructions in parallel; The n-1 instruction processing means in the instruction processing means includes: operand reading means for reading, from the second storage means, an operand necessary for executing the instruction specified by the instruction; and using the read operand. Instruction executor who executes instructions And a operand writing means for writing back the operand obtained as a result of the instruction execution to the second storage means, a first stage for executing reading of the instruction sequence and reading of the operand, processing of the instruction. And a third stage for executing the writing of the operand executes an instruction other than a branch instruction by a pipeline instruction processing mechanism. The instruction processing means includes an operand reading means for reading, from the second storage means, an operand required for executing a conditional branch instruction specified by the instruction, and generating an address of a next instruction sequence and generating a branch destination address. Address generating means for executing in parallel, wherein an instruction read from the first storage means by the instruction reading means is provided with a branch instruction. In the latter case, in the latter half of the first stage, the reading of the operand and the generation of the address of the branch destination are simultaneously executed, thereby eliminating the disturbance of the pipeline operation at the time of executing the branch instruction, and the empty instruction due to the branch delay. An instruction processing device characterized by suppressing an increase in slots.