JP2001092663A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a compiler technique and a circuit constitution in the parallel processing of data. SOLUTION: This data processor is provided with a first processing unit 10 and a second processing unit 20. The first processing unit 10 executes a memory access instruction whose executing time is dynamically changed, and the second processing unit 20 executes an arithmetic instruction whose executing time is statically decided. The both instructions are asynchronously processed in parallel so that a compiler technique can be simplified, and the circuit can be made simpler than a circuit constitution in a super scalar system. When any dependency is present between the both instructions, data are transferred between processing units by using a register 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a device for executing a plurality of instructions in parallel by a plurality of processing units installed in parallel in a stored program type digital computer.

[0002]

2. Description of the Related Art In order to improve the processing performance of a microprocessor, a method of operating a plurality of processing units in parallel and simultaneously executing a plurality of instructions is effective. Conventional methods for realizing this are the superscalar method and V
There is an LIW (Very Long Instruction Word) system.

FIG. 5 shows a conceptual diagram of the super scalar system. In the super scalar method, first, a plurality of instructions to be sequentially executed are analyzed, and the dependency relation of the instructions is checked. By this analysis, simultaneously executable instructions are dynamically detected, and these instructions are distributed to the respective processing units and executed in parallel. In the figure, Add (addition), Sub (subtraction), and Load (load) are instructions that can be executed simultaneously.
Are extracted and distributed. Since a plurality of instructions having different execution times are dynamically scheduled, efficient parallel execution becomes possible.

On the other hand, FIG. 6 shows a conceptual diagram of the VLIW system. In the VLIW method, instructions that can be executed in parallel are statically analyzed at the time of compilation, and instructions for each processing unit are connected to form a long instruction format. That is, the processing unit is, for example, units 1, 2, 3, 4, 5,
, The instruction is the instruction for unit 1 + the instruction for unit 2
Instruction + unit 3 instruction + unit 4 instruction + unit 5 instruction. The processor decomposes the instruction in the long instruction format at the time of execution and issues a small instruction to each of the predetermined processing units so that the processor can execute the instructions in parallel. In the figure, Add, Sub, Mul (multiplication),
The figure shows a case where the data is divided into Div (division) and Load and issued to each processing unit. Since all instruction dependency analysis is performed statically by software at the time of compilation, a complicated dependency analysis circuit is not required, and it is relatively easy to increase the overall parallelism.

[0005]

However, in the superscalar system, all instructions are dynamically analyzed, so that a circuit for analyzing dependence of instructions and a circuit for simultaneously issuing a plurality of instructions become complicated, and the parallelism is reduced. However, there is a problem that the circuit scale is increased as the value is increased and the operating frequency is reduced. In addition, since the hardware configuration of the parallel control part is fixed depending on the degree of parallelism, it is difficult to easily add or delete a processing unit once designed, and there is a problem of lack of flexibility.

Also in the VLIW method, it is difficult to statically schedule an instruction whose execution time changes dynamically, such as a memory access instruction such as a load instruction or a store instruction, and the compiler technology becomes extremely difficult. There's a problem. Moreover, since instructions are issued synchronously to the memory access unit and the operation processing unit which are originally operating asynchronously, when the memory access is stalled, the other operation units are also stalled at the same time, and the parallel processing is performed. There is a problem that the advantage of is lost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to simplify the circuit configuration while simplifying the compiler technology, and
It can also handle addition and deletion of processing units.
An object of the present invention is to provide a data processing device capable of parallel processing.

[0008]

In order to achieve the above object, a data processing apparatus according to the present invention statically determines an execution time with a first processing unit for processing an instruction whose execution time changes dynamically. The second processing units for processing instructions operate in parallel independently of each other.

Further, the first processing unit receives and decodes the instruction whose execution time changes dynamically.
A second execution unit that has a control unit and a first execution unit that executes an instruction supplied from the first control unit, wherein the second processing unit fetches and decodes the instruction whose execution time is statically determined; And a second execution unit that executes an instruction supplied from the second control unit.

The data processing means further comprises data storage means shared by the first processing unit and the second processing unit. And transmitting a dependency between the instruction and an instruction whose execution time is determined.

Further, the first processing unit has first data storage means, and the second processing unit has second data storage means, between the first storage means and the second storage means. By performing data transfer, a dependency between the instruction whose execution time dynamically changes and the instruction whose execution time is statically determined is transmitted.

A plurality of the second processing units exist and operate in parallel independently of each other. The first processing unit has first data storage means, and each of the plurality of second processing units has a second storage unit. Means for performing a data transfer between the first storage means and the second storage means, between the instruction whose execution time dynamically changes and the instruction whose execution time is statically determined. Is transmitted.

Here, it is preferable that the apparatus further comprises rewriting means for rewriting the contents of the first control section or the second control section. Preferably, the instruction whose execution time dynamically changes is a memory access instruction, and the instruction whose execution time is statically determined is an operation instruction.

As described above, in the present invention, an instruction whose execution time dynamically changes, such as a memory access instruction, and an instruction whose execution time is statically determined, such as an operation instruction, are separated from each other. Run independently in another processing unit. FIG. 1 illustrates the concept of the present invention. Load is exemplified as an instruction whose execution time dynamically changes, and Add, Sub, Mul, and Di are instructions that statically determine the execution time.
The example of “v” indicates that both are separated from each other and processed in parallel. This ensures that instructions that do not depend on instructions whose execution time changes dynamically can be executed in parallel,
It is possible to facilitate a compiler technique for performing efficient scheduling. In addition, by scheduling software instructions whose execution time is determined statically by software, it is not necessary to perform an instruction dependence analysis at the time of execution of the instruction, thereby simplifying the circuit configuration and preventing a decrease in operating frequency. Further, for instructions whose execution time is determined statically, instruction dependency analysis is performed by software, so that it is possible to easily cope with addition or deletion of a processing unit at the time of redesign.

The first processing unit for processing an instruction whose execution time dynamically changes and the second processing unit for processing an instruction whose execution time is statically determined have respective control units (program control units). , And decodes the supplied instructions to supply the instructions to the respective execution units, which are independently processed in parallel. When an instruction determined by a static execution time uses an execution result of an instruction whose execution time dynamically changes, a shared or individual data storage unit is used. That is, the execution result of the first processing unit is stored in the data storage unit, and the result is read out by the second processing unit, thereby executing a process according to the dependency between the two and guaranteeing synchronization. Each of the first processing unit and the second processing unit has a control unit, and these contents can be rewritten with each other so that one of the processing units manages or controls execution of another processing unit. Is also possible.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a configuration diagram of the present embodiment. A first processing unit 10, a second processing unit 20, and an external memory 14 are provided. The first processing unit 10 includes a program control unit 10a having a program counter (PC), a load / store (L / S) unit 1
0b, and a register 12. Program control unit 1
0a has an instruction fetch unit and an instruction decode unit in addition to the PC, fetches and decodes a memory access instruction such as a load instruction or a store instruction at the time of compilation, and supplies it to the load / store unit 10b. The load / store unit 10b calculates an address according to an instruction given from the instruction decode unit, a memory access unit that accesses the external memory 14 according to the address calculated by the address calculation unit, and is loaded from the external memory 14. It has a register writing unit that writes data to the register 12, and executes a load instruction or a store instruction supplied from the program control unit 10a. On the other hand, the second processing unit 20
Has a program control unit 20a having a PC, operation units 20b and 20c, and a register 12. The program control unit 20a also has an instruction fetch unit and an instruction decode unit as in the case of the program control unit 10a.
Operation instructions such as b and Mul are fetched and decoded, and supplied to the operation units 20b and 20c for each operation instruction. The operation units 20b and 20c each execute a predetermined operation (for example, the operation unit 20b is Add and the operation unit 20c is Sub), and writes the operation result to the register 12. The operation units 20b and 20c can operate in parallel, and the program control unit 20a issues operation instructions to these operation processing units 20b and 20c in parallel.
The register 12 is a register common to the first processing unit 10 and the second processing unit 20, and supplies a processing result of the first processing unit, that is, data loaded from the external memory 14 to the second processing unit 20, or Second
The operation result obtained by the processing unit 20 is supplied to the first processing unit 10.

As described above, in the present embodiment, since the first processing unit 10 and the second processing unit 20 each have the program control unit and the execution unit, the memory access instruction and the operation instruction are separated at the time of compiling the program. And
Memory access instructions such as load instructions and store instructions whose execution time dynamically changes are supplied to the first processing unit 10 and executed. Operation instructions such as Add instructions and Sub instructions whose execution time is statically determined are executed by the first processing unit 10. By supplying and executing the two processing units 20, both can be executed independently and asynchronously. Therefore, the operation instructions can be executed in parallel without being affected by the dynamically changing memory access time.

When there is a dependency between the memory access instruction and the operation instruction, for example, when a certain operation is performed and another operation is performed by using the operation result, the register 12 shared by the two processing units is used. By writing data and passing data between processing units,
Synchronization of both instructions can be ensured.

FIG. 3 shows the configuration of another embodiment. The difference from FIG. 2 is that each of the first processing unit 10 and the second processing unit 20 has its own register. That is, the first processing unit 10 includes a program control unit 10a, an L / S unit 10b, and a register 10c, and the second processing unit 20 includes a program control unit 20a, operation units 20b, 20c, and a register 2c.
0d.

The processing in the first processing unit 10 and the second processing unit 20 is the same as that in FIG. 2. The first processing unit 10 fetches a memory access instruction, decodes it, accesses the external memory 14, and The two-processing unit 20 takes in the operation instruction, decodes it, and executes various operations in parallel, thereby asynchronously executing the memory access instruction and the operation instruction in parallel.

When there is a dependency between the memory access instruction and the operation instruction, data is transferred using the registers 10c and 20d provided in the respective processing units. For example, data loaded from the external memory 14 is written to the register 10c, and further written to the register 20d by data transfer means (not shown). Arithmetic unit 2 of second processing unit 20
0b (or 20c) can read the data written in the register 20d and perform an operation to ensure the synchronization between the two instructions. Of course, the reverse is also possible,
The result calculated by the arithmetic unit 20b (or 20c) is written to the register 20d, and further written to the register 10c by the data transfer means. The L / S unit 10b of the first processing unit 10 stores the data written in the register 10c in the external memory 1 according to a store instruction.
4, the dependencies between the two instructions can be reliably executed.

FIG. 4 shows the configuration of still another embodiment. The difference from FIG. 3 is that a plurality of second processing units are provided as units 22, 24, and 26, which are connected to each other by an interconnection network 30 and also connected to the first processing unit 10. is there. Multiple second
Each of the processing units 22, 24, and 26 has program control units 22a, 24a, and 26a as in FIG.
In addition, it has arithmetic units 22b, 24b, 26b and registers 22c, 24c, 26c, respectively. The processing of each processing unit is the same as that of FIG. 3. The first processing unit 10 holds and decodes a memory access instruction, accesses the external memory 14, and
In steps 4 and 26, the operation instruction is held and decoded, and various operations are executed in parallel, so that the memory access instruction and the operation instruction are asynchronously executed in parallel.

When there is a dependency between the memory access instruction and the operation instruction, the registers 10c, 22c, 24 provided in the respective processing units are provided.
Data transfer is performed using c and 26d.

In this embodiment, since the second processing units for executing the operation instructions independently and asynchronously perform the processing, it is possible to flexibly cope with even more complicated instructions. When there is a dependency between the plurality of registers 22c, 24c,
6c can be easily handled by transferring data.

In this embodiment, for example, the first
The program control unit 10 a in the processing unit 10 is connected to the second processing units 22, 24, 26 via the interconnection network 30.
Of each program control unit 22a, 24a, 26a in the PC
Can be controlled so as to rewrite the contents.
For example, when there is a dependency relationship in which the second processing unit 24 performs an operation based on data loaded by a load instruction executed by the first processing unit 10, and when the load instruction requires a certain time or more, In other words, the program control unit 10a accesses the program control unit 24a, rewrites the contents of the PC, and changes the order of the calculations, thereby increasing the efficiency of the processing.

Although the embodiments of the present invention have been described above, various modifications can be made within the scope of the technical concept of the present invention. For example, the number of first processing units is not limited to one, and two or more first processing units can be provided as necessary. In this case, each first processing unit has a program control unit and an execution unit (L / S unit). ) May be provided. Also, any number of arithmetic units in the second processing unit can be provided.

Further, in this embodiment, a memory access instruction is used as an instruction whose execution time dynamically changes, and an arithmetic instruction is used as an instruction whose execution time is statically determined. However, other instructions are separated according to this. can do. The essence of the present invention is that an instruction whose execution time can be changed and an instruction whose execution time is fixed are separated at compile time and executed asynchronously. Good.

[0029]

As described above, according to the present invention,
In parallel processing of data, it is possible to simplify the compiler technology and simplify the circuit configuration, and to cope with addition and deletion of processing units.

[Brief description of the drawings]

FIG. 1 is a conceptual explanatory diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a configuration diagram of another embodiment.

FIG. 4 is a configuration diagram of still another embodiment.

FIG. 5 is a conceptual diagram of a superscalar system.

FIG. 6 is a conceptual diagram of the VLIW method.

[Explanation of symbols]

10 first processing unit, 14 external memory, 20 to 2
6 Second processing unit.

Claims (7)

[Claims] 1. A data processing apparatus, wherein a first processing unit for processing an instruction whose execution time dynamically changes and a second processing unit for processing an instruction whose execution time is statically determined are independent of each other. A data processing device that operates in parallel. 2. The apparatus according to claim 1, wherein the first processing unit receives and decodes the instruction whose execution time changes dynamically, and an instruction supplied from the first control unit. A second execution unit that executes the first execution unit, wherein the second processing unit receives and decodes the instruction whose execution time is statically determined, and an instruction supplied from the second control unit. And a second execution unit that executes the following. 3. The apparatus according to claim 2, further comprising a data storage unit shared by the first processing unit and the second processing unit, wherein the execution time is dynamically increased by writing data to the data storage unit. A data processing device for transmitting a dependency relationship between an instruction whose value changes and an instruction whose execution time is statically determined. 4. The apparatus according to claim 2, wherein the first processing unit has a first data storage unit, the second processing unit has a second data storage unit, and the first storage unit and the first storage unit have a first data storage unit. Data for transmitting a dependency relationship between the instruction whose execution time is dynamically changed and the instruction whose execution time is statically determined by performing data transfer with the second storage means. Processing equipment. 5. The apparatus according to claim 2, wherein a plurality of the second processing units exist and operate independently in parallel, the first processing unit includes a first data storage unit, and the plurality of second processing units Each of the processing units has a second storage means, and the data whose execution time changes dynamically by performing data transfer between the first storage means and the second storage means and the static execution A data processing device for transmitting a dependency relationship with a time-determined instruction. 6. The data processing apparatus according to claim 5, further comprising rewriting means for rewriting the contents of said first control unit or said second control unit. 7. The apparatus according to claim 1, wherein said instruction whose execution time dynamically changes is a memory access instruction, and said instruction whose execution time is statically determined is an operation instruction. A data processing device, comprising: