JPH0721155A - Central arithmetic processor - Google Patents

Abstract

PURPOSE:To lighten the load on a CPU without reducing the computing capability of the CPU itself on a main bus by incorporating a dedicated arithmetic part for performing geometrical arithmetic in the CPU as hardware. CONSTITUTION:In an image processing system which uses the CPU 12, the CPU 12, a main memory 13, and a raster processor 14 are connected to a main bus 11. The CPU 12 is provided with a matrix arithmetic part 100 as a dedicated arithmetic part for the function part of a geometric processor. A CPU part 22 is connected to this arithmetic part 100 through an internal bus 21 and for a process for converting coordinates of polygon data, a function for the multiplication of a matrix of nXm=3X3 and a vector of degree m=3, a function for the addition and subtraction of a vector of degree n=3 and a vector of degree n=3, a function for the term-classified multiplication of a vector of degree n=3 and a vector of degree n=3, and a function for the multiplication of a vector of degree n=3 and a scalar value, and a function for division between scalar values are exclusively executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a device which needs to generate and operate an image at high speed such as an image generating device using a computer such as a graphic computer, a special effect device and a game machine. And a suitable central processing unit (hereinafter referred to as CPU).

[0002]

2. Description of the Related Art For example, when an image is generated (drawn) by a graphic computer, an image drawing process is performed according to the processing procedure shown in FIG.

That is, in computer graphics, an object to be drawn is divided into small basic figures (polygons (polygons)), and the shape, position, direction, color, pattern, etc. of the polygons are used as polygon data for determining an image. Given. The shape, position, and orientation of a polygon are determined by the coordinates of its vertices.

As the image drawing process, first, step S
At 1, the drawing data stored in, for example, a memory or a recording medium is read, and at step S2, only polygon data is extracted from the drawing data.

Next, in step S3, based on the viewpoint position information input from the predetermined input means, the screen facing the viewpoint is hypothesized, and the vertex coordinates of each polygon are converted into the coordinates on the screen. To do. The coordinate transformation of the vertex coordinates includes a three-dimensional coordinate transformation OP1 for transforming the orientation of the object based on the viewpoint, and a perspective transformation (two-dimensional coordinate) according to the distance from the viewpoint to the screen with respect to the screen. Conversion) OP2. The three-dimensional coordinate conversion OP1 is
The coordinate transformation matrix is used, and the perspective transformation OP2 is
The division operation is performed using the depth information (Z information) of the vertex.

Then, the obtained converted vertex data is
In step S4, it is taken out from the memory, and in step S5, a polygon is drawn on the video RAM according to the coordinates.

As an apparatus for performing the processing shown in FIG. 5 at high speed, conventionally, an image processing system having a configuration as shown in FIGS. 6 and 7 is used.

In the system of FIG. 6, the main bus 1
On the other hand, the CPU 2 and the main memory 3 are connected. Then, the geometry processor 4 is connected to the CPU 2 via a local bus, and the raster processor 5 is connected to the geometry processor 4 via a local bus. Then, the video RAM 6 is connected to the raster processor 5.

Further, in the system of FIG. 7, a CPU 2, a main memory 3, a geometry processor 7, and a raster processor 8 are connected to a main bus 1.
A video RAM 9 is connected to the raster processor 8.

In the system of FIGS. 6 and 7, the CPU
2 controls the entire system. The geometry processors 4 and 7 perform geometrical operations for the coordinate conversion in step S3 described above. The raster processors 5 and 8 are
Drawing on the video RAMs 6 and 9 in step S5 is performed.

[0011]

In the system shown in FIGS. 6 and 7, the CPU 2 does not need to perform geometric calculation or drawing in the video RAM, so that the burden is lightened and the processing speed can be increased. It has the following drawbacks.

In the system configuration shown in FIG. 6, since the geometric operation after step S3 is executed by pipeline processing,
Although the processing speed is fast, the CPU 2 and the geometry processor 4, and the geometry processor 4 and the raster processor 5
However, since they are connected to each other via independent local buses, there is a drawback that the scale of hardware becomes large.

Further, in the system configuration of FIG. 7, since all the information passes through the main bus 1, the access of the CPU 2 to the main memory 3 is obstructed and the processing speed becomes slower.

In view of the above points, the present invention provides a CPU capable of increasing the drawing speed without increasing the hardware when, for example, a small-sized graphic device having a high drawing function is manufactured. The purpose is to

[0015]

In order to solve the above-mentioned problems, the CPU according to the present invention makes the matrix of n × m (n, m ≧ 2) and m-th order correspond to the reference numerals of the embodiments described later. Function of multiplying by vector of n, vector of addition and subtraction of vector of nth order, vector of nth order and vector of nth order, multiplication of vector of nth order and scalar value A dedicated arithmetic unit 100 is provided for exclusively performing the function and the function of dividing the scalar value.

[0016]

When the CPU according to the present invention having the above-mentioned structure is used to form the above-mentioned image processing system, the function of the geometry processor is the function of the dedicated arithmetic unit 10 of the CPU.
It is executed at 0. Therefore, the amount of data passing through the main bus decreases accordingly, and high-speed processing is possible without adopting the pipeline configuration as shown in FIG.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a CPU according to the present invention will be described below with reference to the drawings.

FIG. 2 is a structural example of an image processing system using the CPU 12 according to the present invention. In this system, a CPU 12, a main memory 13, and a raster processor 14 are connected to the main bus 11. In this case, the functional part of the geometry processor is the CPU
12 is provided with a matrix calculator 100 as a dedicated calculator, and is executed by the CPU 12.

In the case of this example, in the CPU 12, C
The matrix calculator 100 is connected to the internal bus 21 to which the PU unit 22 is connected. Matrix calculator 100
For processing such as coordinate conversion of polygon data in this example, a multiplication function of a matrix of n × m = 3 × 3 and a vector of m = third order, n = third order vector and n = third vector Addition / subtraction function with third-order vector, item-wise multiplication function with n = third-order vector and n = third-order vector, multiplication function with n = third-order vector and scalar value, and between scalar values Dedicated division function and.

FIG. 1 is a block diagram showing the configuration of an embodiment of the CPU 12 according to the present invention. In the CPU 12,
The internal bus 21 is connected to the main bus 11, which is an external bus, via the bus interface unit 24. A CPU unit 22 and a cache memory 23 are connected to the internal bus 21. Further, the matrix calculator 100 is connected to the internal bus 21.

The matrix calculator 100 includes an input / output register 30, three product-sum calculation circuits 31, 32 and 33, and a divider 34. Although not shown, the matrix calculator 100 includes a control unit that receives and decodes an instruction from the CPU unit 22 and supplies a control signal and a control clock to a register and each circuit.

Each of the three product-sum operation circuits 31, 32, 33 includes a coefficient register 41, 42, 43 and a multiplier 5.
1, 52, 53, adders / subtractors 61, 62, 63, and registers 71, 72, 73. Reference numeral 74 is a register for storing a scalar value used at the time of division.

The coefficient registers 41, 42, 43 output the coefficients to the multipliers 51, 52, 53, respectively, and the registers 71, 72 for the adder / subtractors 61, 62, 63, respectively.
The coefficient is output via 73. Multipliers 51, 52, 53
Is supplied to the adders / subtractors 61, 62, 63. The outputs of the adders / subtractors 61, 62, 63 are the registers 71, 72,
It is supplied to the input / output register 30 as well as to the input terminal 73. Further, the output of the adder / subtractor 63 is supplied to the divider 34.

In the case of this example, three product-sum operation circuits are provided because three coordinates x, y, z are required for coordinate conversion for image drawing processing and perspective conversion. This is because the calculations for the three coordinates are performed in parallel. Also,
This is because the color of the object to be drawn is determined by the three primary color data.

In the CPU 12 having the above configuration, the input / output register 30, each coefficient register 41, 42, 43, and the register 44 are connected to the internal bus 21, and can read and write at high speed without passing through the external bus. The input / output register 30 transfers necessary data to the product-sum operation circuits 31, 32, 3
3 and the divider 34, and the calculation result is received as output data, and the calculation result is transmitted to the CPU unit 22 via the internal bus 21.

In this case, the configuration of the CPU 12 according to the present invention can be configured as shown in FIG. 3 or FIG. 4 depending on the way of giving the instruction to the matrix calculator 100. That is, the example of FIG.
In the example in which 00 is connected as a coprocessor, the matrix calculator 100 is the instruction cache 2
Receive and execute coprocessor instructions directly from 3I. Data is transferred from the data cache 23D to the internal bus 2
1 via the data bus 21D.

In the example shown in FIG. 4, the matrix calculator 100 is a C
This is an example in which the memory is mapped on the internal bus 21 of the PU 12, and in this case, the operation is executed by writing an instruction in the instruction register. That is, an instruction is sent from the CPU unit 22 to the matrix operation unit 100 by the address bus 21A and the data bus 21D of the internal bus 21.
Written in.

In either case of the configurations shown in FIGS. 3 and 4, CP is not output to the external bus 11 at the time of operation and CP
The U unit 22 and the matrix calculator 100 can be driven in parallel. Therefore, even when the matrix calculator 100 is performing the calculation, the CPU unit 22
Using the internal bus 21, other operations can be calculated in parallel.

In the above image processing apparatus, the matrix calculator 100 performs the above-mentioned three-dimensional coordinate conversion OP1 and perspective conversion OP2. The three-dimensional coordinate transformation OP1 is represented by the following expression shown as the equation 1, and is composed of multiplication of a 3 × 3 matrix and a cubic vector, and addition of the multiplication result and the cubic vector.

[0030]

[Equation 1] In Equation 1, [M11, M12, M13, M21, M22, M23, M31, M32, M33] is a coordinate transformation matrix. [B1, B2, B3] are vertex coordinates. [C1, C2, C3] are translation vectors. Also,
[A1, A2, A3] are the vertex coordinates after coordinate conversion.

The perspective transformation OP2 is expressed by the following equation (2).

[0032]

[Equation 2] In Equation 2, [O1, O2, O3] is the offset value, and [S1, S2, S3]
Corresponds to the vertex coordinates ([A1, A2, A3]) after coordinate conversion. H is the distance from the viewpoint to the perspective conversion screen. [D1, D2, D3] are the vertex coordinates after perspective transformation.

When performing the above-mentioned coordinate transformation and perspective transformation, the coefficient register 41 has coefficients (M11, M12, M13) for the multiplier 51 and coefficients (C1, O for the adder / subtractor 61).
1) is set, the coefficient register 42 is set with coefficients (M21, M22, M23) for the multiplier 52 and the coefficient (C2, O2) is used for the adder / subtractor 62, and the coefficient register 43 is set with the multiplier The coefficient (M31, M32, M33) for 53 is used by the adder / subtractor 6
The coefficient (C3, O3) is set for 3. Then, the scalar value H is set in the register 74 and supplied as one input of the divider 34, and the value A3 obtained by the adder / subtractor 63 is input as the other input of the divider 34. To be done.

Then, the vertex coordinates [B1, B2, B3] of the polygon are set as input values in the input / output register 30, and the calculation results [A1, A2, A3], [D1, D2, D3] are set. Is set as the output value.

With the above settings, the calculation for each row of the arithmetic expressions of the equations 1 and 2 is performed by each product-sum arithmetic circuit 3
1, 32, 33 are in charge and execute operations in parallel.

In computer graphics, the brightness of an object and the brightness of the atmosphere are blended using the distance from the viewpoint to the object in consideration of attenuation of light due to the atmosphere, so-called fog effect, so that the farther the object appears, the more vague. Then, it may be made to approximate the actual landscape. The calculation for determining the color of the object at this time can be similarly performed using the matrix calculator 100.

Also in this case, the same calculation as in the equation 1 is performed. In this case, in equation 1, [M11, M12, M1
[3, M21, M22, M23, M31, M32, M33] is a matrix representing the properties of the light source, and [B1, B2, B3] is the direction of the light source, that is, the light source vector. [C1, C2, C3] is the ambient light vector. Then, [A1, A2, A3] represents a light source effect. By using this light source effect, the color [D1, D2, D3] of the object can be obtained by the following equation shown as Equation 3.

[0038]

[Equation 3] In this equation 3, [E1, E2, E3] is the original color of the object and [F
[1, F2, F3] is the fog color, and [D1, D2, D3] is the color of the desired object. P is a scalar value. In the case of calculating the color of an object in consideration of the fog effect, each product-sum calculation circuit 3
1, 32, and 33 calculate color data of red R, green G, and blue B.

In this case, the coefficient register 31
To 33 are the coefficients of the matrix and the addition vector For the multiplier 51: Coefficients (M11, M12, M13, E1) For the multiplier 52: Coefficients (M21, M22, M23, E2) For the multiplier 53: Coefficients (M31, M32, M33, E3) For adder / subtractor 61: coefficient (C1, F1) For adder / subtractor 62: coefficient (C2, F2) For adder / subtractor 63: coefficient (C3, F3) Then, in the input / output register 30,
The light source vector [B1, B2, B3] is set as an input value, and the calculation results [A1, A2, A3] and [D1, D2, D3] are set as output values.

[0040]

As described above, according to the present invention, since the dedicated arithmetic unit is built in the CPU as hardware, the load on the CPU is reduced by causing the dedicated arithmetic unit to execute the geometric operation. Reduce and C on the main bus
It is possible not to disturb the calculation function of the PU itself.

Therefore, by using this CPU, even if the raster processor is connected to the main bus as shown in FIG. 2, the congestion of the data on the main bus can be reduced and the high speed processing can be performed. Become. Therefore, by using the CPU of the present invention, it is possible to make a small graphic device having a high drawing function.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a CPU according to the present invention.

FIG. 2 is a diagram showing a configuration example of an image processing system using a CPU according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example of a main part of an embodiment of a CPU according to the present invention.

FIG. 4 is a diagram showing a configuration example of a main part of another embodiment of the CPU according to the present invention.

FIG. 5 is a diagram showing a flow of an image drawing processing procedure.

FIG. 6 is a diagram showing a configuration example of a conventional image processing system.

FIG. 7 is a diagram showing another configuration example of a conventional image processing system.

[Explanation of symbols]

 11 Main Bus 12 CPU 13 Main Memory 14 Raster Processor 15 Video RAM 21 CPU Internal Bus 30 Input / Output Registers 31-33 Product Sum Operation Circuit 34 Divider 100 Matrix Operator

Claims (3)

[Claims] 1. A function of multiplying an n × m (n, m ≧ 2) matrix by an m-th vector, an addition / subtraction function of an n-th vector and an n-th vector, and an n-th vector and n A central processing unit provided with a dedicated arithmetic unit for exclusively performing a function of multiplying a next vector by terms, a function of multiplying an nth-order vector by a scalar value, and a function of dividing between scalar values. 2. The central processing unit according to claim 1, wherein the dedicated arithmetic unit is provided as a coprocessor, and an arithmetic operation in which the arithmetic functions of the dedicated arithmetic unit are combined is executed as one of the instructions. . 3. The central processing unit according to claim 1, wherein the dedicated arithmetic unit is provided as a coprocessor, and an arithmetic operation in which the arithmetic functions of the dedicated arithmetic unit are combined is executed by a combination of instructions.