JPH11328438A - Method and device for high-efficiency floating-point z buffering - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a floating-point Z buffer value process with high numeric precision while minimizing hardware by determining the exponent having the largest specific primitive and generating a common Z exponential value according to it. SOLUTION: A Z value represents the Z coordinate of the vertex of a triangle primitive which can be used to plat a three-dimensional body on a display device. The Z value of the specific primitive is represented in floating-point format through converting operation (S402). Then the Z value of the specific primitive having the largest exponential part is determined (S404) and the common Z exponent of the primitive is generated (S406). Then the Z value of the specific primitive is converted to the fixed-point format (S408). In this state, the common Z value exponential value is advanced forward together with the primitive (S410). After being transferred, the primitive is processed on a fixed- point basis (S412). Consequently, the Z value can be processed with higher efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present application relates to Michael
U.S. patent application Ser. No. 08 / 673,117, filed Jul. 1, 1996 by F. Deering and assigned to the assignee of the present application, entitled "Methods for Implementing High-Resolution Drawing of Z-Buffer Primitives; Is a continuation-in-part application for "device".

The present invention relates to 3D graphics, and more particularly, to processing Z buffer values in a pipeline for 3D graphics accelerator processing.

[0003]

2. Description of the Related Art Current three-dimensional computer graphics technology uses a wide range of geometries to describe three-dimensional objects. Complex and smooth object surfaces to be displayed are represented using a high degree of abstraction. Detailed surface geometry is drawn using a texture map,
For more realism, raw geometry, usually in the form of triangular primitives, is required. In current workstation computer systems, generally the position, color (eg, red, blue, green and optionally α) and the vertical components of these triangles are represented as floating point numbers. You. Fole
The article "Computer Graphics: Principles and Practice" (2nd edition) by y, van Dam et al. provides a fairly detailed description of three-dimensional graphics in general, so if you want more background, Check this out.

FIG. 1 shows a prior art graphics system 10, which is used, for example, in a computer system to display an image created by a user. As shown, the graphics system 10 has a CP via a system bus 22.
The graphics input data is received from U20. The graphics input data includes instructions and data representing a triangle primitive used for drawing a three-dimensional object on the display device 30. Generally, the graphics system 10 includes a graphics accelerator unit 14, a random buffer for the frame buffer.
An access memory 16 (implemented using 3DRAM or other type of memory), and a video control unit 18 are included. The processed video from graphics system 10 is then communicated to monitor 30, which displays images such as 40 and 50.

In the context of the present invention described below, generally, the display objects 40 and 50 have a three-dimensional surface, where a portion of one object is usually hidden by a portion of another object. Have been. For example, in FIG. 1, a portion of the object 40 is in front of a portion of the object 50, thus hiding a hidden portion of the object 50 from view. The part of the object 50 that is hidden from view is called a hidden surface.

[0006] The sense of realism obtained by drawing a three-dimensional object depends on a number of factors, including the ability to quickly calculate the visible and hidden parts (eg, with hidden surfaces) of the object. Depends on. In this manner, the graphics accelerator, such as device 14, removes the hidden surface of each displayed object. The Z buffer device 12 associated with the graphics accelerator device 10 includes, for example, a Z value of each pixel to be drawn,
For example, a depth value is stored. Since more than one object is mapped to a given pixel, a Z-buffer device 12 is used to ensure that objects far away from the viewpoint are projected behind objects near the viewpoint. For example, the Z value of a pixel of the object 50 is
Only when the value is closer to the viewing location than the Z value of that pixel's screen location already stored,
Must be written in In effect, the old Z value of the current pixel being drawn is read from the buffer and the numerical value is compared with the newly created Z value of the current pixel. Depending on the result of the comparison, the old Z value and color frame buffer
The pixel value is left as is or replaced with a newly calculated value. This concept is commonly referred to as "Z buffering."

When graphics input data is input to graphics accelerator 14, geometry data (ie, coordinates) is transformed from model coordinates to viewpoint clipping coordinates via a transformation matrix. . The resulting clipping coordinates are "homogeneous", meaning that they include "W" coordinates in addition to normal Cartesian coordinates. The W coordinate indicates the scaled distance along the z-axis from the viewpoint to the transformed point. The z-axis refers to the same scaled distance, but to a point other than the viewpoint at the origin (typically, the origin of the front clipping plane or the point between the front and rear clipping planes)
Is the distance to be set. According to the perspective division, a new value of Z (Z ') is obtained from the quantity Z / W. Where Z and W
Represents coordinate values before perspective division. For orthographic projection (in this case, the size of the object does not decrease with increasing distance from the viewpoint), the Z 'value of a given point is directly proportional to the distance to the point in the world coordinate system. . Early three-dimensional computer graphics systems were mostly concerned with this type of projection. In these applications, the numerical representation of the Z value using either fixed point or floating point arithmetic has been well matched to the numeric value obtained by the arithmetic.

[0008] However, perspective projection (which decreases in size as the distance from the viewpoint increases) has been adopted in three-dimensional computer graphics. Numerical representations could not be changed and were no longer satisfactorily adapted to the mathematical operations used. For example, in perspective projection, the Z 'value of a point is directly proportional to the reciprocal of the distance to the point in world coordinates. The Z value of the screen space (transformed) generated by the equation used in the prior art is related to the world space coordinate by the following equation.

[0009]

(Equation 1)

Here, F is the distance to the front clipping plane in world coordinates, and B is the distance to the rear clipping plane in world coordinates. Equation (1)
It should be noted that is defined such that points close to the front clipping plane F have values close to zero and points close to the rear clipping plane B have values close to 1. (By using a slightly different equation, the Z value approaches 1 and -1 or -1 and 1 at the front and rear clipping planes).

When B is much larger than F, equation (1) becomes

[0012]

(Equation 2)

## EQU1 ## The ratio B / F plays an important role in Z buffering. In the early days of perspective projection graphics, the ratio B / F was generally a small integer.
Generally, the front clipping plane was two feet from the viewpoint and the rear clipping plane was four to ten feet away. These coordinates were sufficient to see a three-dimensional object of visible size with a few feet.

However, very recent realistic large virtual environments require the front clipping plane to be only a few inches from the viewer's nose and the rear clipping plane to be several miles away. . For this configuration,
The B / F ratio is consequently very large. For example, with a front clipping plane at 6 inches and a rear clipping plane 10 miles away, the B / F ratio exceeds 100,000. Relatively small ranges of 6 inches and 600 feet still have ratios in excess of 1,000.

In a general prior art Z buffer, B
If the / F ratio is large, a problem arises in the accuracy of the numerical value representing the Z value. Consider a particular case where B / F = 1,024.
In the screen space using the expression (1), points located in the rear half of this range (a range beyond the middle toward the rear clipping plane) are set to 10 points before any other bit indicating the distance starts. Has a leading 1 digit. For example,. 11111111111xxx ... xxx. Therefore, in the world coordinates, any point that requires n-bit precision to represent a value between B / 2 and B can be expressed in screen space by using equation (1). 10 + n
This would require bit precision. Generally,
Equation (1) expresses the maximum limit (log2
(B / F)). For example, 10
A B / F ratio of 0000 requires an additional 17 bits. It should be noted that the above loss of representation affects both fixed-point and floating-point representations.
Floating point representation is useful for encoding values where the leading bit is zero, but the Z value in screen space at the point near the back clipping plane is mapped to 1, so the extra bits generated are Is one bit.

Consider another example where the front clipping plane F is 5 cm from the viewpoint. However, the rear clipping plane B is located at 100,000 cm (1 km) from the viewpoint. Using the conventional fixed-point format to represent these Z-buffer values results in very large discrepancies in the individual steps in the front and back clipping planes. In one embodiment, a 24-bit fixed point Z-buffer has 2,796,324 steps in the first 1 cm, but only 94 in the last 10,000 cm.
Step (106.4 cm / step). on the other hand,
An improvement is seen when using a floating point (28 bit) representation in another embodiment (44,74 for the first 1 cm).
1,478 steps, the last 10,000 cm is 14
However, higher accuracy is required for a large F / B ratio.

The use of prior art numerical representations of the Z value results in visible artifacts. With the Z-buffer data properly calculated, the images 40 and 50 are displayed as shown in FIG. 1 and the apple 40 is in front of the box 50. FIG. 2 illustrates a properly projected image representation of these two images. However, in situations where the Z / F distance is such that the Z-buffer data is very inaccurate, an error occurs. Thus, in FIG. 3, without overwriting the lower pixel data for the hidden surface of the box 50, the prior art Z-buffer device 12 erroneously deletes the pixels of the object 40 and the object 50. I decided to paint at the same time.
This "Z-buffering contention" creates an undesirable area of overlap. FIG. 4 illustrates yet another type of display error resulting from incorrect Z-buffering. In FIG. 4, a part of the box 50 is erroneously clearly shown in front of a part of the apple 40.

The above-mentioned problem of the resolution loss particularly depends on the B / F ratio. Assume that the ratio B / F is M. That is, the front clipping plane is at a distance F and the rear clipping plane is at a distance MF. Now, assume that the distance to the rear clipping plane has doubled (ie, the rear clipping plane is now at a distance of 2MF). Thus, each time the distance is doubled, one more bit of resolution is lost. Then, when the remaining bits become very small, the remaining distance farther from half the Z-buffer (eg, MF and 2
(During MF) cannot be resolved. Assuming a Z representation of up to n bits, points at a distance between 1F and 2F are represented with n-1 bits of precision. Points between 2F and 4F are represented with an accuracy of at most n-2. In this way, the remaining bits will not be able to adequately resolve the distance between the objects to be obscured, causing incorrect calculations and displays of hidden surfaces.

This concept is illustrated in FIG. The front and rear clipping planes are shown as F and B, respectively. “0” on the left side of FIG. 5 represents the viewpoint. That is, the eyes of the person observing the depiction of the object being displayed. Objects 40 and 50 shown in FIG. 1 are also depicted in FIG.

[0020]

The above-cited applicant's original patent application provides a Z-buffering method and apparatus that does not suffer from the numerical accuracy problems found in prior art systems. The Z value disclosed in the original application is calculated by an equation different from the equation (1), and is represented by a floating point. The advantage of this Z-buffering is that it does not impose a loss of bit non-linearity on objects rendered far away.

However, applying this new floating point representation to the entire graphics pipeline is expensive because it requires dedicated floating point hardware. Since the added precision is not used in much of the rendering pipeline, the disadvantages are probably greater than the advantages of the new Z-buffered display.

Therefore, it is desirable to take advantage of the floating point Z-buffer representation disclosed in the original patent application while minimizing the extra hardware required.

[0023]

SUMMARY OF THE INVENTION The problems outlined above are largely solved by the method of Z-value processing according to the present invention. Z-values correspond to vertices of certain primitives that are processed in the graphics pipeline. The Z value received in the pipeline is represented in a first floating point format including a mantissa and an exponent (eg, an IEEE floating point format). The method includes determining which of the Z values of a given primitive has the largest exponent value. In one embodiment, this includes comparing the current index value with the current maximum index value to test all Z values. The method of the invention substantially comprises the step of generating a common Z-index value in response to determining the largest exponent value of the predetermined primitive. In one embodiment, the common index value is generated by subtracting a constant value from the largest index value. Next, the method of the invention comprises the step of converting the Z value of the given primitive into a fixed point format in which the mantissa is scaled to a common Z exponent value. The transformed value is then converted to a primitive as graphics processing continues with the first set of operations utilizing the Z value (represented in fixed point format) and the common exponent value. Sent with. After this first set of operations, the Z values are converted back to a second floating point format. Next, a second set of graphics operations (i.e., hidden surface removal) is performed using this second floating point format.

The use of a single exponent for all vertices of a given primitive allows the Z value to be represented more efficiently, resulting in improved graphics pipeline performance. Efficiency is further improved by using an intermediate fixed-point format that is more compact than the equivalent floating-point format. Finally, in one embodiment, the Z value is represented using the formula W _f / W. Unlike prior art systems, this representation does not impose a loss of bit nonlinearity at points in the far region where the F / B ratio is large.

The present invention may be better understood with reference to the following detailed description of the preferred embodiment, taken in conjunction with the following drawings.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG . 6 Computer System Referring to FIG. 6, a computer system 80 including a three-dimensional (3-D) graphics accelerator according to the present invention is shown. As shown in the figure, the computer
The monitor system 80 includes a system unit 82 and a video monitor or display device 84 coupled to the system unit 82. Display device 84 may be any of a variety of types of display monitors or devices. Various input devices, including a keyboard 86 and / or a mouse 88, or other input device, can be connected to the computer system. The application software runs on the computer system 80 to display the 3-D graphics object on the video monitor 84. As further described below,
3-D graphics computer system 80
The accelerator includes an improved ability to process the Z values of the geometry data corresponding to the primitives used to render the three-dimensional graphics object on the display device 84.

FIG . 7 Blocks of the computer system
Referring now to FIG. 7, a simplified block diagram illustrating the computer system of FIG. 6 is shown. Elements of the computer system that are not necessary for understanding the present invention are not shown for convenience. As shown in the figure,
Computer system 80 includes a central processing unit (CPU) 1 coupled to a high speed bus or system bus 104.
02. System memory 106 is also preferably coupled to the high speed bus 104.

The host processor 102 may be any of various types of computer processors, multiprocessors and CPUs. System memory 106 may be any of various types of memory subsystems, including random access memory and mass storage. The system bus or the host bus 104 includes a host processor, a CPU, as well as a dedicated subsystem.
And any type of communication bus between the memory subsystem and the host computer bus for communication. In the preferred embodiment, host bus 104 is a UPA bus, which is a 64-bit bus operating at 83 MHz.

The 3-D graphics accelerator 112 according to the present invention is coupled to the high speed memory bus 104. 3-D graphics accelerator 11
2 may be connected to bus 104 by, for example, a crossbar switch or other bus connectivity logic. Various other peripherals, or other buses, may be connected to the high speed memory bus 104, as is well known in the art. It should be noted that the 3-D graphics accelerator can be connected to any of a variety of buses, as desired. As shown, the video monitor or display device 84 has 3
-Connect to D graphics accelerator 112. About Graphics Accelerator 112
This will be described in more detail below.

FIG . 8 Graphics Accelerator Referring now to FIG. 8, a block diagram illustrating the graphics accelerator 112 according to a preferred embodiment of the present invention is shown. As shown, the graphics accelerator 112 is in principle a command
Block 142, floating point processing units 152A-152
Set F, drawing processing devices 172A and 172B, 3DR
It comprises a frame buffer 100 composed of an AM and a random access memory / digital-analog converter (RAMDAC) 196.

As shown, the graphics accelerator 112 includes a command block 142 that interfaces with the memory bus 104. Command block 142 is a graphics accelerator
It interfaces the data bus 112 with the host bus 104 and controls data transfer between other blocks or chips within the graphics accelerator. The command block 142 performs pre-processing of the triangle data and the vector data, and decompresses the geometry data.

Command block 142 interfaces with a plurality of floating point processors 152A-152F. Preferably, graphics accelerator
The data 112 includes up to six floating point processors labeled 152A-152F as shown. The floating point processing units 152A to 152F receive high-level drawing commands and generate graphics primitives such as triangles and lines for drawing a three-dimensional object on a screen. Floating point processing units 152A-152
F performs transformation, clipping, surface determination, lighting and setup operations on the received geometry data. Floating point processor 152A-
Each of the 152F has a respective memory 153A-153.
Connected to F. The memories 153A to 153F store 32
It is preferably a k.times.36-bit SRAM and is used for storing microcode and data.

Each of the floating point processors 152A-F is connected to two rendering processors 172A and 172B. Graphics accelerator 112 preferably includes two rendering processors 172A and 172B, although more or less rendering devices could be used. Drawing processing devices 172A and 172B
Performs screen space rendering of various graphics primitives and acts to sequentially process the completed pixels into an array of 3DRAMs.
Further, the drawing processors 172A and 172B also function as control chips of the 3DRAM for the frame buffer 100. The drawing processors 172A and 172B simultaneously process one image according to a drawing packet received from one of the floating-point processors 152A to 152F or according to a direct port packet received from the command processor 142. Draw in the frame buffer 100.

Each of the floating point processors 152A-152F preferably operates to broadcast the same data to the two rendering processors 172A, 172B. In other words, the same data is always present on both sets of data lines coming from each floating point processor 152A-152F. Therefore, the floating point processing units 152A-1
When 52F transfers the data, the floating point processor will send both F to drawing processors 172A and 172B.
The same data is transferred to the D bus.

Each of the drawing processing units 172A and 172
Each of B is connected to a frame buffer 100. The frame buffer 100 includes four banks 192A, B and 194A, B of 3DRAM memory. The drawing processing unit 172A includes two 3DRAM banks 192A and 192.
B, the drawing processing device 172B has two 3DRAs.
It is connected to M banks 194A and 194B. Each bank consists of three 3DRAM chips as shown. The three DRAM memories or banks 192A, B and 194A, B together form a frame buffer 100. The frame buffer 100 is 1280 × 1024 at a depth of 96 bits. The frame buffer is drawn by the drawing processors 172A and 172B.
The pixel corresponding to the D object is stored.

Each of the 3 DRAM memories 192A, 192B and 194A, 194B is a RAMDAC (random access memory / digital-to-analog converter).
196. The RAMDAC 196 has a programmable video timing generator and a programmable pixel clock synthesizer, as well as a conventional color look-up table circuit and a triple video DAC circuit, as well as a crossbar function. Also, the RAMDAC is coupled to a video monitor 84.

The command block is preferably implemented on a single chip. Floating point processor 152A-15
Each of the 2Fs is preferably implemented on a separate chip.
In the preferred embodiment, up to six floating point processors or chips 152A-152F are included. Preferably, each of the drawing blocks or processors 172A and 172B also comprises a separate chip.

FIG . 9 is a block diagram of a floating point processor. FIG . 9 is a block diagram illustrating one of the floating point processors 152A-152F according to a preferred embodiment of the present invention. Since each of the floating-point processing units 152A to 152F is the same, only one of them (indicated by 152) will be described here for convenience. As shown in the figure, the floating point processing units 152A-1
Each of 52F includes three main functional units, a core processor, namely, an F-core processor 202, an L-core processor 204, and an S-core processor 206.
The F-core processor 202 executes the command block 142
Are connected so as to receive data transferred from the CF bus from the CF bus. The F-core processor supplies output data to each of the L-core processor 204 and the S-core processor 206. The L-core processor 204 is
Data to the S-core processor 206. S-core processor 206 provides output data to the FD bus.

The F-core processor 202 performs all floating point intensive operations, including geometry transformation, clip testing, surface determination, perspective splitting, and screen space transformation. The F co-processor 202 performs clipping when necessary. In the preferred embodiment, the three bits stored in a 32 kword SRAM (153) are used.
Using a 6-bit microinstruction word, the F-core processor 202 is fully programmable.

The L-core processor 204 performs most lighting calculations using on-chip RAM-based microcode. Unlike prior art lighting devices, L-core processor 204 uses fixed-point arithmetic to perform these calculations. In the preferred embodiment, the numerical range of the L-core processor 204 is -2.0 to +2.0 using the s1.14 format (1 sign bit, 1 integer bit, and 14 fractional bits). . Most of the lighting calculations are performed in this range using 16-bit operands of this type. However, some parameters required for the lighting calculation are processed as follows, beyond this range.

The L-core processor 204 also includes an efficient triple word design for more efficient lighting calculations. The triple word design operates on a 48-bit data word consisting of 16-bit fixed point values. Therefore, with one command, all three color components (RGB) or the normal three components (N
x, Ny, and Nz) perform the same function in one cycle. By means of a numerical calculator included in the L-core processor, the numbers are automatically clamped to the permissible value range, so that no additional branches are required.

The S-core processor performs setup calculations for all primitives. This setup calculation involves calculating the distance from one vertex to another vertex in multiple dimensions, and calculating the gradient along that edge. For triangles, the gradient of Z depth, color and UV (for texture) are also calculated in the direction of the scan line.

FIG . 10 is a block diagram of the drawing apparatus. FIG. 10 is a block diagram showing the drawing apparatus 172A. Drawing devices 172A and 172B
Are the same, and here, for convenience, one of them (indicated by 172) will be described. Drawing device 172
Controls the order of arrangement of the three DRAM chips. The rendering processing unit 172 performs 3DR that performs logical scheduling of an internal cache for pixels and a video output refresh.
With AM. These resources include queuing the pixel to be rendered before it reaches the 3DRAM, and searching the 3D
Controlled by predicting RAM cache misses.

As shown in the figure, the drawing processing device 172
It includes an FD bus interface block 302 that interfaces to the FD bus. The FD bus interface block 302 couples to the CDC bus interface logic 312. The CDC bus interface logic 312 includes a scratch buffer 314
And the direct port device 316. The direct port device 316 has a frame buffer interface.
It receives an input from the face logic 336 and provides an output to the pixel data multiplexer logic 332. Also,
CDC bus interface logic 312 is coupled to provide output to the DC bus. The FD bus interface 302 includes the primitive accumulation buffer 30
4 to the output.

Further, the drawing processing device 172 has a command
It includes scoreboard logic 318, which keeps track of the order of the primitives as specified by block 142.
As shown, the scoreboard logic receives the F_Num input and provides an output to a primitive accumulation buffer 304. Command block 142 renders a 3-bit code each time a (unicast) primitive is copied to one of the CF bus output FIFOs.
Feed to 2. The code specifies which of the six processing units 152A-152F of the floating point block will receive the primitive. Also, the core
The field contains a bit that indicates whether the primitive is ordered or not. All ordered primitives need to exit in the order in which they entered. Unordered primitives are removed from primitive accumulation buffer 304 whenever possible. There are primitives, such as text and markers, that output multiple primitives for each input primitive, and these primitives are preferably placed in an unordered mode to increase efficiency. However, all attributes sent to the rendering processor 172 must remain ordered with respect to the primitives they modify.
Further, there may be lines and triangles that must be strictly ordered. Scoreboard logic 318 tracks at least 64 primitives. The scoreboard logic 318 includes a command block 142 to prevent the scoreboard logic 318 from overflowing when the scoreboard logic 318 is nearly full.
Send a signal back to.

As mentioned above, primitive accumulation buffer 304 receives outputs from FD bus interface 302 and scoreboard logic 318. The primitive accumulation buffer 304 stores an edge line walker (walk).
r) provides an output to logic 322, whose edge walker logic 322 then provides an output to span fill logic 324. The span fill logic 324 provides an output to the texture pixel processor 326. In addition, span
Fill logic 324 provides an output to direct port device 316. The primitive accumulation buffer 30
4 provides an output to the texture expander logic 328.
Texture expander logic 328 includes a texture memory
It is connected to the cache 330. Texture memory cache 330 provides data to texture pixel processor 326. Also, the texture memory cache 330 has a direct port device 316.
Supply data to Texture / pixel processing unit 3
26 and the direct port device 316 each have a pixel
Data is provided to data multiplexer logic 332. The pixel data multiplexer logic 332 includes:
The output is provided to a pixel processing unit 334. Pixel processing unit 334 provides its output to frame buffer interface 336 and direct port
The output is supplied to the switching device 316.

The primitive accumulation buffer 304 is used to accumulate primitive data until a complete primitive is received. Thus, as data is collected from the six floating point processors 152A-152F, the data will eventually form complete primitives. Primitive accumulation buffer 304 has sufficient memory space to store a portion of the second primitive in order to keep the pipeline running smoothly, in addition to enough memory space to hold one complete primitive. Contains. The six primitive accumulation buffers 304 include six floating point processing units 152A to 152A.
Full when data comes in from each of the 52Fs. As soon as a primitive is completely received, the next primitive generally follows. Thus, the primitive accumulation buffer 304 has sufficient extra data to transfer the complete primitive from the primitive accumulation buffer 304 to the edge walker logic 322 before being filled with incoming data from the next primitive. Includes buffering. In the preferred embodiment, the primitive accumulation buffer 304 is several words larger than the largest primitive (triangle) to be processed. Primitive accumulation buffer 304 provides a 64-bit output to edge walker logic 322. Primitives are retrieved from the primitive accumulation buffer 304 at a time based on the contents of the scoreboard logic 318.

[0048] The edge walker logic 322 is designed to be easily processed by the span fill unit 324.
Split primitives apart. In the case of a triangle, the edge walker logic 322 follows the two current edges and produces a set of vertical spans adjusted to the nearest pixel sample point. The set of vertical spans is then sent to a span fill unit 324. The ridge walker unit 322 also makes similar adjustments for straight lines and sends a straight line description very similar to a triangular span to the span fill unit 324. Edge walker logic 322 comprises two 16 × 24 multipliers used to make these adjustments. In addition, the edge walker logic 322 includes several adders that keep track of the counts used to make other calculations. Primitives other than triangles and straight lines are segmented based on the most efficient use of resources. Both jagged and anti-aliased dots are sent through the logic with minimal adjustment (eg, adding 0.5 to the jagged dots). Large dots are provided as individual pixels via the edge walker logic 322. Edge walker logic 322 converts polygons and rectangles to horizontal spans. Edge line walker logic 322 is Bresen
The ham line is sent to the span fill device 324 without modification.

The span fill unit 324 interpolates values (usually for triangles and straight lines) over spans oriented in any direction, and filters the weighted tables for anti-aliased straight lines. Perform a search.
For optimized primitives, including triangle span pairs, rectangular and polygon spans and anti-aliased lines and points, two pixels are generated per cycle. All other primitives generate one pixel per cycle. The last stage of the span fill device 324 performs dithering, and converts a 12-bit color into an 8-bit value using a dither pattern of a 4 × 4 screen space. The span fill logic 324 provides an output to the texture pixel processor 326.

The texture / pixel processing unit 326 includes:
It performs texture calculations and controls the search for texels in the texture memory cache 330. texture·
Pixel processing unit 326 generates colors to be blended into pixels by pixel processing unit 334. The texture pixel processor 326 sends data for all other primitives except the textured triangles to the pixel data multiplexer logic 332.

As mentioned above, primitive accumulation buffer 304 provides an output to texture expander logic 328. Texture expander 328 operates to expand received textures for storage in texture memory cache 330. Thus, the texture memory cache 330 is loaded directly from the primitive accumulation buffer 304 and is connected to the texture pixel processing unit for texel search. The texture memory cache 330 is designed to hold enough data to texture map a 16x16 texel area, including all relatively small mipmaps. texture·
The memory cache 330 is preferably double buffered so that other buffers can be loaded while the current buffer is in use.
It should be noted that the 16x16 texel area is actually stored as a 17x17 array for the interpolation to be performed correctly.

As mentioned above, the pixel data multiplexer logic 332 receives input data from the texture pixel processing unit 326 and the direct port unit 316. Pixel data multiplexer logic 332 arbitrates between pixels coming from span fill unit 324 and pixels coming from the CD bus. Pixels from the CD bus are always preferred. Pixel Day
Data multiplexer logic 332 provides its output to pixel processing unit 334.

The pixel processing device 334 includes the 3DRAM 1
For logical operations at 92, 194, mixed,
Perform alias removal, depth curing and set up. Further, the pixel processing device 334 includes a line pattern.
Logic operable to inhibit pixel writing for patterning, template patterning, V port clipping, and other operations. The pixel processing unit 334 includes a frame buffer interface 336.
Supply output to

Frame buffer interface 336
Have the necessary logic to read and write pixels from the 3DRAM memories 192A, 192B. Frame
The buffer interface 336 manages the level 1 (L1) and level 2 (L2) caches of the 3DRAM chips. This is done by predicting the pixel to be written and paging the required cache while other pixel accesses are occurring. Next, as shown in the figure, the frame buffer interface 336 includes 3DRAM memories 192A, 192B,
194A and 194B.

Processing of Z Value Now, FIG. 11 shows a flowchart of a method 400 of processing a Z value in a pipeline for graphics processing. The Z value is part of the graphics data transferred to the graphics accelerator 112 on the system bus 104 by the central processing unit 102, which is the system CPU. This Z value represents the Z coordinate of the vertex of a triangle primitive that can be used to draw a three-dimensional object on the display device 84. The transferred Z value is a model space coordinate, and the I value shown in FIG.
It is expressed in a first floating point format such as the EEE floating point standard 500. As shown in the figure, the IEEE format 500 includes a sign bit 502, an exponent part 504.
And a mantissa 506. This includes the "hidden 1" location 508. Other floating point formats can also be used.

The model space coordinates received by the graphics accelerator 112 are transformed to homogeneous clipping coordinates, normalized in the F-core processor 202, and
The value comes to be expressed as Z / W. This value is -1
Exists in the range from to +1. After clipping, the Z values of the given primitive (along with the X and Y coordinates) are mapped to screen space via the transform operation of step 402 of processing method 400. X and Y of screen space
The coordinates correspond to pixel values on the display device 84. On the other hand, the Z coordinate corresponds to a depth along an imaginary z-axis perpendicular to the screen. As disclosed in the original patent application, the Z value is preferably expressed as W _f / W. Here, W _f represents the W in the front clipping plane. As explained above,
The Z value converted in this way extends between 1.0 (inclusive) at the front clipping plane and 0.0 (not included) when the object approaches the rear clipping plane. Unlike prior art systems, this transformation does not result in significant loss of precision for numbers near zero (close to the back clipping plane according to one embodiment of the invention). After step 402, the Z value is in floating point format 50
Note that it is represented by zero.

Next, in steps 404 and 406,
Z for a given primitive with the largest exponent 504
The value is determined and a common Z index for the primitive is generated. As explained above, the use of a floating point Z-buffer has the potential disadvantage of being more expensive to implement due to the additional indication bits. This disadvantage is largely small within the scope of the present invention by using a single exponent for each Z value of a given primitive. This is possible because it is statistically possible that all vertices of a given primitive have the same exponent for all Z values (or that the exponents are very close). Polygons with exponents that are not closely related are generally due to poor graphic programming practices.

Step 404 includes several sub-steps described with reference to FIGS. FIG.
Is the exponent comparator unit 6 inside the F-core processor 202.
00 is illustrated. The exponent comparator device 600 has a current Z value of 60.
2 includes a current Z index register 610 coupled to receive two. The output of register 610 is the maximum Z exponent register 6
20, adder 622 and comparator 640. Comparator 640 is connected to receive the output of register 620, and outputs comparison signals 642A and 642A.
B is transmitted to the controller 650. Next, the control device 650
Conveys the load index signal 652 not only to the register 620 but also to the common Z index register 630. Register 620
Receives a clear signal 604. Register 630
Receives an input from a clamp multiplexer 624 coupled to the output of adder 622. The adder 622 receives a subtraction constant 626 as another input.

At step 404A, the maximum Z index register 620 is cleared by asserting a clear signal 604. Register 620 is designed to hold the current maximum Z-index value of the current primitive, so
This register is cleared before receiving the Z value of the current primitive. In the preferred embodiment, this is done by executing a "fixz" instruction with a special status bit set.

Next, in step 404B, the current Z value 602 is received in the register 610. Register 610
And 620 are used to determine whether the current Z value 602 is greater than the contents of register 620.
Proceed to The comparator 640 outputs the comparison signals 642A, 6
42B is transmitted to the controller 650. Controller 650 (at step 404C) stores the contents of 620 in register 61.
Determine whether to replace with the contents of 0. The contents of register 620 are always replaced with the first Z value received for a given primitive.

If replacement is required, step 404D
Then, the contents of the current Z index register 610 are written to the maximum Z index register 620. When the contents of the register 610 are transmitted to the comparator 640 and the comparison operation is performed in the step 404B, the value of the register 610 is also transmitted to the input of the register 620 (purely). If controller 650 determines (based on comparison signal 642) that replacement is required, load index signal 652 is asserted and register 6
The current value of 10 is copied to register 620. Thus, the current Z value becomes the current maximum exponent value. In the preferred embodiment, the operation is triggered by a “fix gtz” instruction stored in SRAM 153 and executed by circuitry within F-core processor 202.

The common Z index value is calculated at step 406 at the same time as the replacement operation. Common Z exponent value (register 630)
Is associated with the contents of register 620, and the number of bits used in the representation is reduced. For example, as shown in FIG. 12A, the exponent part 504 of the IEEE format 500 is 8 bits. This number of bits is needed to represent the entire range of the floating point, but fewer bits are used to represent numbers between 0 and 1. In addition, this maintains the size of the interval used to represent the Z value.

In a preferred embodiment of the present invention,
Four bits are used to encode a common Z-index value that allows values between 0 and 15. This allows for 15 normalized expressions and 1 unnormalized expression. 1
A common Z index value of 5 corresponds to a maximum index value 504 of less than 1.0. This is 1 in format 500
26. In this way, the current Z value (eg, the value 60
The conversion from 2) to a 4-bit representation involves subtracting a constant value. In the preferred embodiment, this is accomplished by subtracting 111 (or, alternatively, adding -111).

Each time a comparison is made in step 404B,
The value of the register 610 is transmitted to the adder 622. Further, the adder 622 receives the subtraction constant 626. In a preferred embodiment of the invention, this constant is equal to 0x91 (decimal number -111). Next, the output of adder 622 is passed to clamp multiplexer 624. When the output of adder 622 has a negative result, clamp multiplexer 624 clamps the result to zero. Otherwise, the output of adder 622 does not change. In both cases, the clamp multiplexer 6
The output of 24 is communicated to the input of a common Z index register 630. When no replacement is performed (indicated by assertion of load index signal 652), the output of multiplexer 624 is not written to register 630. When the replacement operation is performed in step 404D, the corresponding common Z index value is stored in the register 630 in step 406.

As shown in decision box 404E,
The above steps are also performed for the remaining vertices of the primitive (two more in the general case of triangle primitives). After the last Z value has been compared (and possibly written to register 620), register 62
0 holds the maximum value of the exponent part 504 for the Z value of the current primitive. Similarly, register 630 contains
The common Z exponent value corresponding to the value of the register 620 is stored.

At step 408, the Z value of the given primitive is converted to a fixed point format (eg, format 510 shown in FIG. 12B). As shown, format 510 includes a sign bit 512, an integer bit 514, and a mantissa 516. This is
It is referred to as 1.30 format (sign bit, integer bit, and fractional 30 bit). Since the mantissa 516 is scaled with respect to the common Z exponent value calculated in step 406, the fixed-point format 510 has no exponent. In the preferred embodiment, each Z value is normalized within F-core processor 202 with a code sequence that implements the following algorithm.

[0067]

[Table 1]

Thus, the algorithm takes the difference between the exponent parts 504 of both the maximum Z index and the current Z index. This value is stored in a variable "shift". Next, the hidden one bit is ORed and put into the floating-point mantissa,
Create a 4-bit mantissa value. This 24-bit value is then shifted left by 6 bits (the rest of the 30-bit mantissa field 516 is padded with zeros). It should be noted that these extra 6 bits increase the precision of subsequent fixed point processing. Finally, the 30-bit value is shifted right by the appropriate number of bits so that the mantissa value 516 is normalized to the primitive's common Z exponent.
In other embodiments, floating-fixed conversion processing is performed separately, including by a dedicated hardware circuit.

With the Z value converted to fixed point in step 408, the common Z index value is advanced with the primitive and further processed in step 410. FIG.
As shown in FIG.
It is stored in the Z exponent field 702 within zero. The header word 700 is written by the F-core processor 202 and transmitted to the S-core processor 206 via the FS buffer shown in FIG. The header word 700 propagates down the pipeline as the corresponding primitive is processed. Thus, the Z-index value of field 702 is available for calculations as described below.

After a common Z index has been generated and transferred with the primitive, fixed-point processing is performed on the primitive in step 412. As shown in FIG. 11, step 412 includes sub-step 412A (setup),
412B (ridgeline walking) and 412C (span filling). These operations are performed as described above. In a preferred embodiment,
The setup is performed by the S-core processor 2 of the processing unit 152.
At 06, the edge interpolation is performed by the edge walker unit 322 in the drawing processing unit 172, and the span interpolation is performed by the span filling unit 324 of the drawing processing unit 172. These steps correspond to s1.
Using the 30 format 510 can be performed more accurately and effectively. It should be noted that in other embodiments, operations different from those shown here are performed within step 412.

In FIG. 15, the pixel processing device 334
Is shown in FIG. Following the span interpolation of step 412C, the primitive data is sent to the processing unit 334 for additional operations before being transferred to the frame buffer 100 via the frame buffer interface 336. Will be transferred. As shown in the figure,
The common Z-index value calculated as described above is
Odd and even YZ pipelines 802A, 80 on 10
2B. Similarly, fixed-point Z values (in s1.30 format) are transferred to pipelines 802A and 802B on buses 812A and 812B, respectively. Although separate pipelines (odd and even) are shown in FIG. 12 for pixel processing of the Z values, in another embodiment, the Z values are processed using a single pipeline. . FIG. 15 also shows fixed-point buses 814A and 814A.
Pipelines 802A and 802 respectively by 14B
Depth queuing pipeline 8 connected to B
04A and 804B are also shown.

As described below, the pipeline 802
Performs two types of conversions on s1.30 format data carried on buses 810 and 812. First, this data is, for example, in a format 53 shown in FIG.
It is converted to an equivalent fixed point such as 0. This conversion corresponds to step 414 shown in FIG. The fixed point data represented using the format 530 is then used in step 418 to make depth queuing and Z-clip decisions.

Secondly, the pipeline 802 is used to store incoming data before it is transferred to the frame buffer 100.
If necessary, this data is configured to be converted to a floating point format. This conversion process (step 416) is performed when the Z value is chosen to be represented in frame buffer 100 in floating point notation. One example of such a representation is the format 520 shown in FIG. In the description of FIG. 16, cp_z
It is assumed that the f signal 916 is asserted. This means that a floating point Z value is required. The Z value resulting from the fixed-floating conversion process of step 416 is then used in step 420 to perform a hidden surface removal operation in the frame buffer 100.

Referring to FIG. 16, a block diagram of the pipeline 802 is shown. Only the part that processes the Z pixel values is shown. Pipeline 802 represents pipelines 802A and 802B. In one embodiment, pipeline 802 includes stages 900A-900.
H. However, in other embodiments, the pipeline 802 can be divided into more or fewer stages.

The first stage (stage 900A) of the Z pipeline 802 is a two-source Z pixel database.
Data, i.e., a constant Z value 902 and a Z value from the pixel data multiplexer 332 (comprising a common Z index value on bus 810 and a fixed point Z value on bus 812). Multiplexer 906. In processing method 400, multiplexer 906
Transfers data on the bus 810/812 in response to the control signal 904. This data is sent to the pixel output bus 907
Conveyed above.

The pixel output bus 907 is connected to the inverter 90
8 and the barrel shifter 912. At step 414, these units, along with logic gate 910, convert the data on bus 907 to fixed point format 530. This step involves shifting the mantissa 516 of the format 510 by an amount equal to the complement of the common Z exponent value. Therefore, format 53
The mantissa part 532 of 0 is the mantissa part 51 of the format 510.
Unlike 6, it must be tied to an index value corresponding to the common Z index value generated in step 406.

The four most significant bits of the data (common Z index value) on the bus 907 are transmitted to the inverter 908. Next, the inverted bit is passed to logic gate 910,
Therefore, the correction is made by the control signal 916. Thus, the output of logic gate 910 is a shift count of the value of mantissa 516 provided to barrel shifter 912. For example, if the common Z index value is 15 (maximum value), the inverter 90
The shift number given by 8 is zero. As a result, shifter 912 does not shift. Conversely, a common Z index value of 0 produces a shift number of 15.

The barrel shifter 912 forms a 28-bit fixed-point mantissa 532 from the data transmitted from the multiplexer 906. This data is latched at the end of the first pipeline stage for transmission to the Z-clip test hardware in the next clock cycle. Also, the most significant mantissa bit on bus 907 is passed on to leading zero encoding unit 914. Unit 91
4 communicates the number of leading zeros of the mantissa value on bus 907 to the hardware of pipeline stage 900B.

At pipeline stage 900B, a Z-clip decision is also made, as well as the first part of converting the data on input bus 812 to a normalized floating point number. A Z-clip decision on the data transferred from the previous pipeline stage 900A is made by comparator 922. Comparator 922A converts the Z pixel value transmitted on p1_zfix bus 814 to a zmin value of 92.
Compare with 0. Similarly, comparator 922B is connected to bus 814
Compare the above value with the zmax value 918. When the Z pixel value is outside any of these values, clipping should occur in the Z direction. Accordingly, logic gate 924 asserts its output, which is output at a later pipeline stage 900C by the zp_zclip signal 926.
Conveyed as. Further, the fixed point values on bus 814 are communicated to depth queuing pipeline 804 for further processing.

The floating point normalization of the Z buffer value is started at pipeline stage 900B. z
To convert the value from format 510 to format 520, the most significant bit of mantissa 516 is
Needs to be shifted to position 524. This process
Beginned by a unit 914 that counts the number of leading zeros in the mantissa 514 of a given Z value.

The subtractor 936 calculates this number of leading zeros of the Z value on bus 928 and the common Z index value (the most significant four
Bit). Subtractor 93
6 is configured to subtract the number of leading zeros from the common index value and communicate the result to the difference bus 940. If the result is non-negative, the number of leading zeros is incremented by 1 to produce the value of the mantissa 526 (which is normalized).
Must be shifted by a number equal to the sum of. If the result is negative (the number of leading zeros is greater than the common Z index),
7 indicates that the mantissa value 516 carried over must be shifted by the common Z-index value (but
This results in unnormalized numbers).

Therefore, the subtractor 936 has two outputs,
That is, the difference bus 940 (the result of the subtraction) and the carry-out signal 942 (which is asserted when the difference bus is negative) are transmitted. The difference bus 940 is passed to logic gate 938.
If difference bus 940 is non-zero, logic gate 938 is:
The asserted signal 934 is transmitted to the adder 932. Adder 932 also receives the number of leading zeros on bus 928. If difference bus 940 is not zero, adder 932 communicates the number of leading zeros plus one to multiplexer 948. The other input of multiplexer 948 is connected to bus 9
A common Z index value is received from 30.

Thus, the output (shift count) of multiplexer 948 is selected based on the value of carry-out signal 942. If the number of leading zeros exceeds the common Z-index value, the common Z-index value is sent to multiplexer 956. Otherwise, the value on bus 944 is communicated. Multiplexer 956 communicates a selected one of these two values to pipeline stage 900C.
If signal 916 is not asserted, stage 90
The shift count conveyed to OC is 4 (this has the effect of passing the value on bus 907 without change. These 4 "lost" bits are described below. , Because they are reconnected.)

The multiplexer 950 is connected to the pipeline 8
02 is used to select which value to pass to multiplexer 952 as the four most significant bits of the Z value being processed. When the floating point mode is selected for the Z value (signal 916 is on), these four bits are
2 to form the value of the floating point exponent 522 shown in C.
If the floating point mode is not selected, these four bits become the most significant mantissa bits of the mantissa 532 shown in FIG. The value selected by the multiplexer 950 is
It depends on the value of the carry-out signal 942. If carry out signal 942 is active, zero constant 94
6 is communicated to the multiplexer 952. This will set the exponent value to zero. However, if the carry-out signal 942 is inactive, the value on the difference bus 940 calculated by the subtractor 936 is transmitted as the value of the exponent 522.

The value transmitted from multiplexer 950 is transferred to pipeline stage 900C via multiplexer 952. Pipeline Stage 9
At 00C, the output of multiplexer 952 is the four most significant bits of the Z value. As explained above, if the Z value is represented in floating point format 520, these four bits form an exponent value 522. Also, pipeline stage 900C completes the normalization of the Z values that have been converted to floating point format 520. This is done by barrel shifter 958 which shifts the mantissa of bus 930 to the left, producing the value of mantissa 526. This mantissa value is concatenated with the exponent value in register 960. The fixed point Z value (signal 916 is inactive) is passed to register 960 unchanged.

At pipeline stage 900D, multiplexer 962 selects between the Z value transmitted from stage 900C and the pixel value transmitted from another pipeline. Stage 900E-9
00G is another data path data of the pixel processing unit 334.
It exists to align with the pipeline. At stage 900H, the floating point Z value is transmitted on bus 964. In the preferred embodiment, this value (which may or may not be normalized) is represented in floating point format 520. This value is used by the frame buffer interface 33 for hidden surface removal operations.
6 and subsequently to the frame buffer 100. In the floating point format used in the preferred embodiment of the present invention, a simple integer comparison is sufficient for the Z-buffer comparison, since a uniformly monotonically decreasing number distribution occurs from front to back. is there.

By utilizing the method 400, more efficient processing of the Z value is effectively enabled. By converting the transformed Z values to a fixed point format (eg, 510), the same hardware that handles color and alpha values in the graphics pipeline can be reused. By representing the entire primitive with a single Z value up to the pixel processing stage of the pipeline,
Increased efficiency is achieved. In one embodiment, the fixed-point format used as an intermediate representation (ie, format 520) is converted to an equivalent fixed-point format for operations such as Z-clip testing and depth queuing. -Can be converted to a mat.

Although the system and method of the present invention have been described in connection with the described embodiments, it is not intended to be limited to the specific form set forth herein.
On the contrary, it is intended to cover alternatives, modifications and equivalents, which are reasonably included within the spirit and scope of the invention as defined by the appended claims.

[Brief description of the drawings]

FIG. 1 shows a Z-buffering process in a graphics processing system according to the prior art.

FIG. 2 is an explanatory diagram of a three-dimensional object from which hidden surface removal has been correctly performed.

FIG. 3 is an explanatory diagram of a three-dimensional object in which hidden surface removal has not been correctly performed.

FIG. 4 is an explanatory diagram of a three-dimensional object for which hidden surface removal has not been correctly performed.

FIG. 5 illustrates the loss of precision caused by the prior art numerical representation of the Z value.

FIG. 6 illustrates a computer system including a three-dimensional (3-D) graphics accelerator according to the present invention.

FIG. 7 is a simplified block diagram of the computer system of FIG.

FIG. 8 is a block diagram illustrating a 3-D graphics accelerator according to a preferred embodiment of the present invention.

FIG. 9 is a block diagram illustrating one floating-point processing device of a 3-D graphics accelerator according to a preferred embodiment of the present invention.

FIG. 10 is a block diagram illustrating one of the rendering processing apparatuses of the 3-D graphics accelerator according to one embodiment of the present invention.

FIG. 11 is a flowchart illustrating a method of processing a Z value in a processing pipeline of a graphics system according to one embodiment of the present invention.

FIGS. 12A-12D illustrate various formats of Z values utilized in a 3-D graphics accelerator according to one embodiment of the present invention.

FIG. 13 is a block diagram illustrating an exponent comparator device according to one embodiment of the present invention.

FIG. 14 illustrates a header word used to store a common Z-index value according to one embodiment of the present invention.

FIG. 15 is a block diagram of a pixel processing apparatus according to one embodiment of the present invention.

FIG. 16 is a block diagram of a pipeline configured to process Z pixel values according to one embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continuation of front page (71) Applicant 597004720 2550 Garcia Avenue, MS PAL1-521, Mountain View, California 94043-1100, United States of America

Claims (31)

[Claims] 1. A first system in a graphics system.
The method of processing a set of z-coordinate values, wherein the first set of z-coordinate values corresponds to vertices of a first geometric primitive, the method represented in a first floating-point format. Receiving a first set of z-coordinate values; converting the first set of z-coordinate values to a fixed-point format; and receiving the first set of z-coordinate values in the fixed-point format. First set of graphics operators using z-coordinate values
Generating a second set of z-coordinate values expressed in the fixed-point format; and converting the second set of z-coordinate values to a second floating-point format. And the second floating point format represented by the second floating point format.
Performing a second set of graphics operations using the set of z-coordinate values. 2. The method according to claim 1, wherein the value represented in the first floating-point format includes a mantissa part and an exponent part. 3. The method according to claim 1, further comprising: setting a common z value of the first set of z coordinate values.
3. The method of claim 2, comprising generating an index value. 4. The step of generating the common z-index value comprises: determining a maximum z-coordinate value of the first set of z-coordinate values; and generating the common z-index value from the maximum z-coordinate value. 4. The method of claim 3, comprising: 5. The method of claim 1, wherein said first set of graphics
4. The method of claim 3, wherein performing an operation comprises utilizing the common z-index value. 6. The step of converting the first set of z coordinate values to the fixed point format comprises:
5. The method of claim 4, comprising scaling the first set of Z coordinate values according to an exponent value. 7. The method of claim 6, wherein performing the first set of graphics operations comprises utilizing the scaled first set of z coordinate values. 8. The method according to claim 1, wherein the first set of Z coordinate values is greater than 0.0 or less than 1.0 and the first set of Z coordinate values is 1.
A z-value of 0 indicates that the given vertex is in the front z-clipping plane, and a z-value approaching 0.0 for the given vertex is that the given vertex is near the back z-clipping plane. The method of claim 1, wherein the method comprises: 9. The method of claim 1, wherein the first set of graphics operations includes a setup operation of the first geometric primitive. 10. The method of claim 1, wherein the first set of graphics operations includes edge interpolation of the first geometric primitive. 11. The method of claim 1, wherein the first set of graphics operations includes span interpolation of the first geometric primitive. 12. The method of claim 3, wherein the value represented in the fixed-point format includes a mantissa. 13. The step of converting the second set of z-coordinate values to the second floating-point format, wherein the step of converting the second set of z-coordinate values to the second floating-point format comprises
Normalizing the mantissa of each of the coordinate values, wherein the normalizing utilizes the common Z-exponent value to generate a mantissa and an exponent of the second floating-point format. 13. The method of claim 12, comprising: 14. The method of claim 1, wherein the second set of graphics operations includes performing a Z-buffer comparison to achieve hidden surface removal. 15. The method of claim 15, further comprising enabling a floating point Z-buffer mode, converting the second set of z coordinate values to the second floating point format, and 2. The method of claim 1, wherein said step of performing a set of graphics operations is performed in response to said enabling step. 16. A system for processing z-coordinate values corresponding to vertices of a first graphics primitive, the system comprising a first graphics primitive corresponding to the first graphics primitive and represented in a first floating-point format. An input device coupled to receive the first set of z-coordinate values, and an input device coupled to receive the first set of z-coordinate values from the input device; A floating-point to fixed-point conversion device configured to convert to a fixed-point format; and a fixed-point format coupled to receive the representation of the first set of z-coordinate values in the fixed-point format.
A first graphics process configured to perform a first graphics operation using the first set of z-coordinate values represented in a matte to generate a second set of z-coordinate values; And a second set of z from the first graphics processing device.
A fixed-point to floating-point converter coupled to receive coordinate values and configured to convert the second set of z-coordinate values to a second floating-point format; The second expressed in matte
To perform a second set of graphics operations using the second set of z-coordinate values expressed in the second floating-point format. And a second graphics processing device configured as described above. 17. The system of claim 16, wherein the value represented in the first floating point format includes a mantissa and an exponent. 18. The system of claim 17, wherein the floating-point to fixed-point converter is configured to generate a common z-index value of the first set of z-coordinate values. 19. The floating-point to fixed-point conversion device is configured to determine a maximum z-coordinate value of the first set of z-coordinate values, and further comprising the common z-index from the maximum z-coordinate value. 19. The system of claim 18, wherein the system is configured to generate a value. 20. The first graphics processing device,
20. The system of claim 18, wherein the system is configured to utilize the common z-index value when performing the first set of graphics operations. 21. The system of claim 18, wherein the floating-point to fixed-point converter is configured to scale the first set of z-coordinate values according to the common z-index value. 22. The first graphics processing device,
22. The system of claim 21, wherein the system is configured to utilize the scaled first set of z-coordinate values in performing the first set of graphics operations. 23. The first set of z coordinate values is greater than 0.0 or less than or equal to 1.0, and a z value of 1.0 for a given vertex is such that the given vertex is in the forward z clipping plane. 17. The method of claim 16, indicating that a z value approaching 0.0 for the given vertex indicates that the given vertex is approaching a posterior z clipping plane. 24. The system of claim 16, wherein the first graphics processing device is configured to perform a setup operation of the first geometric primitive. 25. The system of claim 16, wherein the first graphics processing device is configured to perform edge interpolation of the first geometric primitive. 26. The system of claim 16, wherein the first graphics processing device is configured to perform span interpolation of the first geometric primitive. 27. The system of claim 16, wherein the value represented in the fixed point format includes a mantissa. 28. The fixed-point-to-floating-point converter converts the second point represented by the fixed point format into
And further configured to normalize a mantissa of each of the set of z-coordinate values, and further utilize the common z-exponent value to generate a mantissa and an exponent of the second floating-point format. 28. The system of claim 27, wherein the system is configured to: 29. The second graphics processing device,
17. The system of claim 16, wherein the system is configured to perform a Z-buffer comparison to achieve hidden surface removal. 30. The apparatus of claim 30, further comprising a controller configured to enable a floating point Z-buffer mode, wherein the fixed point-to-floating point converter includes a floating point Z-buffer mode. Responsive to being enabled, configured to convert the second set of z coordinate values to the second floating point format; and
17. The graphics processing unit is configured to perform the second set of graphics operations in response to the floating-point Z-buffer mode being enabled. System. 31. A system for processing a first set of z-coordinate values, wherein the first set of z-coordinate values corresponds to vertices of a first geometric primitive. Receiving means for receiving the first set of z-coordinate values expressed in a format; first converting means for converting the first set of z-coordinate values to a fixed-point format; and the fixed-point format. A first set of graphics operations is performed using the first set of z-coordinate values expressed in a matte, and a second set of z-coordinate values expressed in the fixed-point format. First graphics processing means for generating the second set of z-coordinate values into a second floating-point format, and the second set of z-coordinate values in the second floating-point format. Second
And a second graphics processing means for performing a second set of graphics operations using the set of z-coordinate values.