JP2007128180A - Arithmetic processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an arithmetic processing unit allowing reduction in a processing load for command issue and overhead of a system. <P>SOLUTION: Single commands, "Affine", Pproj" and "View", can be combined and executed as one command "APV", so that the processing load of a CPU 5 for issuing a command and the overhead of the system are reduced. An intermediate value (output value of a single command) generated in the processing stage for the command "APV" is not written in a main RAM 25, and is held in registers GR0 to GR15, so that a memory area necessary for execution of the command can be reduced and a bus band necessary for memory access can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device that processes geometric operations in three-dimensional graphics and related technology.

  Non-Patent Document 1 discloses a three-dimensional graphics technique. As described in this document, when drawing three-dimensional graphics, various coordinate transformations must be performed. When a processor dedicated to geometric operation for processing geometric operations such as coordinate transformation at high speed is provided, these operations are performed by issuing a command to the processor dedicated to geometric operation for each coordinate transformation. Alternatively, for a transformation matrix that can be synthesized, a transformation matrix is synthesized in advance, and a series of coordinate transformations are performed simultaneously by issuing one command. For a transformation matrix that cannot be synthesized, commands for that are sequentially issued and operations are performed. Do.

Sho Yamaoka, “3D Graphics by Turbo C”, 1st Edition, Morikita Publishing Co., Ltd., February 10, 1995, p. 160

  However, in any of the above cases, a plurality of commands must be issued to perform all necessary coordinate transformations. For this reason, the processing load of a functional unit (for example, a CPU) that issues a command increases, and the overhead of the system also increases.

  Therefore, an object of the present invention is to provide an arithmetic processing apparatus and related technology capable of reducing the processing load for issuing commands and the overhead of the system.

  According to a first aspect of the present invention, an arithmetic processing device is an arithmetic processing device that processes geometric operations, and executes an input means that executes geometric operations and commands input from the outside. Control means for controlling the execution means to cause the execution means to execute processing according to the command, and calculation target data used for the geometric calculation and / or calculation result data as a result of the geometric calculation are held. A plurality of types of commands, and the execution unit includes a memory external to the arithmetic processing unit according to the commands belonging to a first group among the plurality of types of commands, / Or receiving the operation target data from the data holding means, executing a geometric operation, outputting the operation result data to the external memory, and The command belonging to the second group is an instruction for instructing execution of a predetermined combination of the different commands belonging to the first group, and the execution means includes the command belonging to the second group Accordingly, when the first command among the commands included in the predetermined combination is executed, the calculation target data is received from the external memory and / or the data holding unit, and the geometric calculation is performed. When executing the command other than the first command, the calculation target data is received from the data holding unit, a geometric operation is performed, and the last command among the commands included in the predetermined combination is executed. After executing the command other than the command, the operation result data is output to the data holding means, After executing the command after the outputs the arithmetic result data to the external memory and / or the data holding means.

  According to this configuration, a single command (first group command: referred to as “single command”) can be combined and executed as one command (second group command: referred to as “composite command”). , The processing load of the functional unit that issues the command (for example, CPU) and the overhead of the system are reduced. Also, intermediate values (single command output values) generated during compound command processing are not written to the external memory but are held in the internal data holding means, so the memory area required for command execution is reduced. In addition, the bus bandwidth required for memory access can be reduced.

  According to the second aspect of the present invention, the arithmetic processing device is an arithmetic processing device for processing a geometric operation, and interprets and inputs an execution means for executing the geometric operation and a command input from the outside. Control means for controlling the execution means to cause the execution means to execute processing according to the command, and calculation target data used for the geometric calculation and / or calculation result data as a result of the geometric calculation are held. Data holding means, and the execution means outputs the input data as it is or converts the data into a predetermined data type according to the control from the control means, and the type conversion means Computing means for executing computation using data output by the control means, wherein the control means stores the computation object data in a memory external to the computation processing device and / or the data. Read from the holding means, input to the type conversion means, input data output from the type conversion means to the calculation means, and output data from the calculation means as the calculation result data in the memory and / or The execution means is controlled to write to the data holding means.

  According to this configuration, the number of bits of each matrix element as calculation target data is optimized and stored, and the optimized calculation target data is aligned with a predetermined data type before calculation by the type conversion unit. As a result, it is possible to save a memory area and a register area for storing operation target data. Note that the accuracy and expressible range of the elements of each matrix as calculation target data are not necessarily uniform, but the data types after conversion by the type conversion means are uniformly arranged due to the convenience of the arithmetic circuit.

  In this arithmetic processing unit, when the input command is for instructing execution of a predetermined matrix operation, the control means is the data input by the type conversion means for a predetermined element in the input matrix. The execution means is controlled to convert the data into the predetermined data type, and for the elements other than the predetermined element in the input matrix, the data input by the type conversion means is converted to the predetermined data type. The execution means is controlled so as to output the data as it is without being converted into the data.

  In this arithmetic processing unit, the conversion of the predetermined data type performed by the type conversion means is zero extension and / or sign extension.

  According to a third aspect of the present invention, the arithmetic processing device is an arithmetic processing device for processing a geometric operation, and includes an execution means for executing a geometric operation, operation target data used for the geometric operation, and / or the Data holding means for holding calculation result data which is a result of geometric calculation, and the execution means receives data including a plurality of numerical values and one magnification, and selects one of the plurality of numerical values Numerical value extraction means for performing multiplication with the magnification and outputting a multiplication result; and calculation means for executing an operation using the multiplication result output from the numerical value extraction means, wherein the execution means includes the calculation The target data is read from an external memory of the arithmetic processing unit and / or the data holding unit, input to the numerical value extracting unit, and the multiplication result output from the numerical value extracting unit is input to the arithmetic unit. Is written in the memory and / or the data holding means data output from said operation means as said operation result data.

  According to this configuration, since the data obtained by multiplying the matrix or vector element as the calculation target data by the magnification is calculated, a plurality of values can be changed by changing the setting of the magnification while keeping the size of the data actually subjected to the calculation constant. The range that can be expressed can be supported. Thereby, it is possible to save a memory area and a register area for storing operation target data.

  According to a fourth aspect of the present invention, the arithmetic processing device is an arithmetic processing device that processes geometric operations, and receives a plurality of vertex coordinates defining polygonal graphic elements in a three-dimensional orthogonal coordinate system as input, A coordinate conversion unit that performs coordinate conversion of each vertex coordinate, and calculates a sum total of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion, and outputs the calculated sum as a depth value of the polygonal graphic element Means.

  According to this configuration, even when a polygonal graphic element (for example, a polygon) is defined by one depth value in the rendering process (that is, when it is not possible to have a depth value for each vertex), each vertex The depth value of the polygonal graphic element can be calculated from the predetermined coordinate axis component (for example, the Z-axis component).

  According to a fifth aspect of the present invention, an arithmetic processing device is an arithmetic processing device that processes geometric operations, and receives a plurality of vertex coordinates that define a polygonal graphic element in a three-dimensional orthogonal coordinate system as input, A coordinate conversion unit that performs coordinate conversion of each vertex coordinate; a total calculation unit that calculates a sum of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion; and an initial value of the sum and the depth value of the polygonal graphic element Addition means for adding a value as an input, adding the sum and the initial value, and outputting the addition result as a depth value of the polygonal graphic element;

  According to this configuration, the initial value of the depth value of a polygonal graphic element (for example, a polygon) functions as a depth value bias, thereby intentionally raising or lowering the drawing priority of the polygonal graphic element. Can be expressed.

  In the arithmetic processing apparatus according to the fourth and fifth aspects, the sum calculation means converts the sum into a floating point number format and outputs the result.

  According to this configuration, by expressing the depth value in the floating-point number format, a wide range of coordinate space can be covered with a small number of bits. In addition, the depth value can be expressed with high accuracy in the region close to the viewpoint and with coarse accuracy in the far region, and the expression corresponding to the accuracy required for the drawing of the three-dimensional graphics can be performed with the depth value of a small number of bits.

  The arithmetic processing device further includes bias holding means for holding a bias value of the exponent part of the sum in a floating-point number format, and the bias holding means is accessible from outside the arithmetic processing device, and is read from the outside. And can be lighted.

  According to this configuration, the bias of the exponent part of the sum can be set by an external functional unit (for example, a CPU), so that the degree of dispersion of a plurality of polygonal graphic elements in the three-dimensional space can be set. Depth value can be optimized. That is, even if the depth value has a limited accuracy, the arrangement order of the polygonal graphic elements in the depth direction can be correctly expressed, so that the memory usage can be saved.

  The arithmetic processing device according to the fourth aspect and the fifth aspect may be configured such that when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range, the polygonal graphic A culling means for setting values outside the drawing range to all vertex coordinates of the element can be provided.

  According to this configuration, it is possible to reduce a drawing processing load by preventing a graphic element having a polygonal shape having a predetermined coordinate axis component (for example, a Z-axis component) of at least one vertex from being in a predetermined range.

  The arithmetic processing unit according to the fourth aspect and the fifth aspect may be configured such that when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range, the polygonal graphic Culling means for removing data defining elements from the drawing data string can be provided.

  According to this configuration, it is possible to save memory usage and draw by removing a polygonal graphic element whose predetermined coordinate axis component (for example, Z-axis component) of at least one vertex is not within a predetermined range from the drawing data string. The processing load can be reduced.

  The arithmetic processing device according to the fourth aspect and the fifth aspect may be configured such that when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range, the polygonal graphic A first culling means capable of setting values outside the drawing range for all vertex coordinates of the element, and at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is within the predetermined range A second culling means capable of removing data defining the polygonal graphic element from the drawing data sequence, and at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion. One of the first culling means and the second culling means is selected as means for executing processing when one is not within the predetermined range. It can comprise a selecting means.

  According to this configuration, an external functional unit (for example, a CPU or the like) can be selected by enabling processing to be performed when a predetermined coordinate axis component (for example, a Z-axis component) of at least one vertex is not within a predetermined range. If it is necessary to refer to and prepare the output result, the first culling means can be selected, otherwise the second culling means can be selected to save memory.

  The arithmetic processing device further includes a threshold value holding unit that holds a threshold value for setting the predetermined range, and the threshold value holding unit is accessible from outside the arithmetic processing device, and can read and write from the outside. it can.

  As described above, the threshold value that defines the predetermined range can be set by the threshold value holding means (for example, a register), so that an external functional unit (for example, a CPU) can freely set the range of the three-dimensional space to be rendered. Can be controlled.

  According to a sixth aspect of the present invention, the arithmetic processing device is an arithmetic processing device for processing geometric operations, and represents a surface in which the order of apexes in the three-dimensional orthogonal coordinate system is clockwise. Projection means for projecting each vertex coordinate of a polygonal graphic element defined with a clockwise surface as the back to a two-dimensional orthogonal coordinate system, and a first vertex coordinate and a second vertex from the projected all vertex coordinates Selecting means for selecting coordinates and third vertex coordinates; first vector calculating means for calculating a first vector by subtracting the first vertex coordinates from the second vertex coordinates; and A second vector calculating means for subtracting the first vertex coordinates to calculate a second vector; an outer product calculating means for calculating an outer product of the first vector and the second vector; and a sign of a result of the outer product operation. Based on the two-dimensional orthogonal coordinate system And a determining means for determining which side of the front and back of the graphic elements of the polygonal shape appears.

  According to this configuration, the front / back determination of the polygonal graphic element (for example, polygon) by the vector cross product operation is performed by using the vertex coordinates after projection onto the two-dimensional orthogonal coordinate system instead of the three-dimensional orthogonal coordinate system. The calculation amount can be greatly reduced.

  The arithmetic processing unit may include a culling unit that sets a value outside the drawing range to all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element determined to have the back surface appear.

  According to this configuration, it is possible to reduce the load of the drawing process by preventing the polygonal graphic element determined to be the reverse side from being drawn.

  The arithmetic processing unit may further include a culling unit that removes data defining the polygonal graphic element determined to have the back surface from the drawing data string.

  According to this configuration, by removing the polygonal graphic element determined to be the back from the drawing data string, it is possible to save the memory usage and reduce the drawing processing load.

  The arithmetic processing unit is a first culling means capable of setting a value outside the drawing range to all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element that is determined that the back surface appears. And a second culling means that can remove data defining the polygonal graphic element determined to appear on the back surface from the drawing data string, and a case where it is determined that the back surface appears As means for executing the process, a selection means for selecting either the first culling means or the second culling means can be provided.

  According to this configuration, when it is determined that the reverse side appears, it is possible to select a process, and when an external functional unit (for example, a CPU or the like) needs to refer to and prepare an output result. In order to select the first culling means, otherwise to save memory, it becomes possible to select the second culling means.

  According to a seventh aspect of the present invention, the arithmetic processing device is an arithmetic processing device for processing geometric operations, and each vertex coordinate of a polygonal graphic element defined in a three-dimensional orthogonal coordinate system is two-dimensionally orthogonal. Whether projection means for projecting to a coordinate system, addition means for adding a predetermined value to each of the coordinate axis components of the projected vertex coordinates, and whether the vertex coordinates made up of the coordinate axis components resulting from the addition are within a predetermined range Determination means for determining whether or not.

  According to this configuration, whether or not a polygonal graphic element (for example, a polygon) after adding a predetermined value is within a predetermined range is determined using a two-dimensional orthogonal coordinate system instead of a three-dimensional orthogonal coordinate system. By using the vertex coordinates after projection onto the screen, the amount of calculation can be greatly reduced.

  This arithmetic processing unit is configured to draw a drawing range on all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element including a vertex whose vertex coordinate consisting of a coordinate axis component as a result of the addition is determined to be outside a predetermined range. A culling means for setting an external value can be provided.

  According to this configuration, it is possible to reduce the drawing processing load by preventing the drawing of polygonal graphic elements including vertices that are determined not to fall within the predetermined range.

  The arithmetic processing unit includes a culling unit that removes data defining the polygonal graphic element including the vertices in which the vertex coordinates including the coordinate axis component as a result of the addition are out of a predetermined range from the drawing data string. Can be provided.

  According to this configuration, by removing polygonal graphic elements including vertices that are determined not to be within the predetermined range from the drawing data string, it is possible to save memory usage and reduce the drawing processing load.

  The arithmetic processing unit is configured to draw a drawing range on all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element including a vertex in which a vertex coordinate consisting of a coordinate axis component as a result of the addition is determined to be out of a predetermined range. Data defining a polygonal graphic element including a first culling means capable of setting an outside value, and a vertex coordinate having a vertex coordinate consisting of a coordinate axis component as a result of the addition determined to be outside a predetermined range As a means for executing processing when it is determined that a vertex coordinate consisting of a coordinate axis component as a result of the addition is out of a predetermined range. Selecting means for selecting either the second culling means or the second culling means.

  According to this configuration, by making it possible to select a process when it is determined that the vertex coordinates are not within the predetermined range, it is necessary for an external functional unit (for example, a CPU or the like) to refer to and prepare an output result. In some cases, it is possible to select the first culling means, otherwise to select the second culling means in order to save memory.

  The arithmetic processing unit further includes a predetermined value holding unit that holds the predetermined value used by the adding unit, and the predetermined value holding unit is accessible from outside the arithmetic processing unit, and reads and writes from outside. can do.

  In this way, the external function unit (for example, CPU) can change the predetermined value added to the coordinates after projection onto the two-dimensional coordinate system, so that the viewport can be set at an arbitrary position on the display screen. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is incorporated. When it is necessary to indicate which bit of the signal, [a: b] or [a] is added after the signal name. [A: b] means the a-th bit to the b-th bit of the signal, and [a] means the a-th bit of the signal. “0b” means a binary number, and “0x” means a hexadecimal number.

  FIG. 1 is a block diagram showing an internal configuration of a multimedia processor 1 according to the embodiment of the present invention. As shown in FIG. 1, the multimedia processor 1 includes an external memory interface 3, a DMAC (direct memory access controller) 4, a central processing unit (hereinafter referred to as “CPU”) 5, a CPU local RAM 7, and rendering processing. A unit (hereinafter referred to as “RPU”) 9, a color palette RAM 11, a sound processing unit (hereinafter referred to as “SPU”) 13, an SPU local RAM 15, a geometry engine (hereinafter referred to as “GE”) 17, Y sorting unit (hereinafter referred to as “YSU”) 19, external interface block 21, main RAM access arbiter 23, main RAM 25, I / O bus 27, video DAC (digital to analog co) Verter) 29, audio DAC block 31, and A / D converter (hereinafter, referred to as "ADC".) 33 comprises a. When it is not necessary to distinguish between the main RAM 25 and the external memory 50, they are referred to as “memory MEM”.

  The CPU 5 executes programs stored in the memory MEM to perform various calculations and control of the entire system. Further, the CPU 5 can make a program and data transfer request to the DMAC 4, and can directly fetch the program code from the external memory 50 and directly access the external memory 50 without going through the DMAC 4.

  The I / O bus 27 is a bus for system control using the CPU 5 as a bus master, and is a functional unit (external memory interface 3, DMAC 4, RPU 9, SPU 13, GE 17, YSU 19, and external interface block 21) that is a bus slave. It is used to access the control registers and local RAMs 7, 11 and 15. In this way, these functional units are controlled by the CPU 5 through the I / O bus 27.

  The CPU local RAM 7 is a RAM dedicated to the CPU 5, and is used as a stack area for saving data at the time of a subroutine call or interruption, a storage area for variables handled only by the CPU 5, and the like.

  The RPU 9 generates a three-dimensional image composed of polygons and sprites in real time. Specifically, the RPU 9 reads each structure instance of the polygon structure array and each structure instance of the sprite structure array sorted by the YSU 19 from the main RAM 25, executes a predetermined process, and executes a screen ( An image is generated for each horizontal line according to the scan of the display screen. The generated image is converted into a data stream indicating a composite video signal waveform and output to the video DAC 29. Further, the RPU 9 has a function of making a DMA transfer request to the DMAC 4 for taking in texture pattern data of polygons and sprites.

  The texture pattern data is two-dimensional pixel array data that is pasted on a polygon or sprite. Each pixel data is a part of information for designating an entry in the color palette RAM 11. Hereinafter, the pixels of the texture pattern data are referred to as “texels”, and are used separately from “pixels” that indicate the pixels constituting the image displayed on the screen. Therefore, the texture pattern data is a set of texel data.

  The polygon structure array is a structure array for polygons that are polygonal graphic elements, and the sprite structure array is a structure array for sprites that are rectangular graphic elements parallel to the screen. The elements of the polygon structure array are called “polygon structure instances”, and the elements of the sprite structure array are called “sprite structure instances”. However, when it is not necessary to distinguish between the two, they may be simply referred to as “structure instances”.

  Each polygon structure instance stored in the polygon structure array contains display information for each polygon (vertex coordinates on the screen, information on texture patterns in texture mapping mode, and color data in Gouraud shading mode (RGB color components)) In other words, one polygon corresponds to one polygon structure instance. Each sprite structure instance stored in the sprite structure array is display information for each sprite (including information on coordinates and texture patterns on the screen), and one sprite structure instance corresponds to one sprite structure instance. Yes.

  The video DAC 29 is a digital / analog converter for generating an analog video signal. The video DAC 29 converts the data stream input from the RPU 9 into an analog composite video signal, and outputs it from a video signal output terminal (not shown) to a television monitor or the like (not shown).

  In the present embodiment, the color palette RAM 11 is composed of a color palette of 512 colors, that is, 512 entries. The RPU 9 refers to the color palette RAM 11 using the texel data included in the texture pattern data as part of an index for designating the entry of the color palette, and converts the texture pattern data into color data (RGB color components).

  The SPU 13 generates PCM (pulse code modulation) waveform data (hereinafter referred to as “wave data”), amplitude data, and main volume data. Specifically, the SPU 13 generates wave data for a maximum of 64 channels and time-division multiplexes, generates envelope data for a maximum of 64 channels and multiplies the channel volume data, and time-divisions the amplitude data. Multiplex. Then, the SPU 13 outputs main volume data, time-division multiplexed wave data, and time-division multiplexed amplitude data to the audio DAC block 31. Further, the SPU 13 has a function of making a DMA transfer request for taking in wave data and envelope data to the DMAC 4. Details of the SPU 13 will be described later.

  The audio DAC block 31 converts the wave data, amplitude data, and main volume data input from the SPU 13 into analog signals, and multiplies the results to generate analog audio signals. This analog audio signal is output from an audio signal output terminal (not shown) to an audio input terminal (not shown) of a television monitor or the like (not shown).

  The SPU local RAM 15 stores parameters used when the SPU 13 performs wave reproduction and envelope generation (for example, storage addresses and pitch information of wave data and envelope data).

  The GE 17, which is one of the features of the present invention, executes a geometric operation for displaying a three-dimensional image. Specifically, the GE 17 performs operations such as matrix product, vector affine transformation, vector orthogonal transformation, perspective projection transformation, vertex lightness / polygon lightness calculation (vector inner product), and polygon back surface culling processing (vector outer product). Details will be described later.

  The YSU 19 sorts each structure instance of the polygon structure array and each structure instance of the sprite structure array stored in the main RAM 25 according to the sorting rules 1 to 4. In this case, the polygon structure array and the sprite structure array are separately sorted.

  Hereinafter, the sorting rules 1 to 4 by the YSU 19 will be described, but before that, the coordinate system will be described. A two-dimensional coordinate system used for actual display on a display device (not shown) such as a television monitor is called a screen coordinate system. In this embodiment, the screen coordinate system is composed of a two-dimensional pixel array of 2048 pixels in the horizontal direction and 1024 pixels in the vertical direction. The coordinate origin is at the upper left, the right direction corresponds to the positive X axis, and the lower direction corresponds to the positive Y axis. However, the area actually displayed is not the entire space of the screen coordinate system but a part of the space. This display area is called a screen.

  Sort rule 1 is to rearrange the polygon structure instances in ascending order of the minimum Y coordinate. The minimum Y coordinate is the smallest Y coordinate among the Y coordinates of all the vertices of the polygon. The Y coordinate is the vertical coordinate of the screen, and the downward direction is the positive direction. Sort rule 2 is to arrange the polygon structure instances in descending order of the depth value for a plurality of polygons having the same minimum Y coordinate. Note that the greater the depth value, the deeper the drawing.

  However, the YSU 19 regards a plurality of polygons having pixels displayed on the first line of the screen as being the same even if the minimum Y coordinate is different, so that the sorting rule 2 is not the sorting rule 1. According to the above, the polygon structure instances are rearranged. That is, when there are a plurality of polygons having pixels displayed on the top line of the screen, the minimum Y coordinate is regarded as the same, and they are rearranged in descending order of the depth value. This is the sort rule 3.

  Sort rules 1 to 3 are applied even in the case of interlaced scanning. However, in the sorting for displaying the odd field, the minimum Y coordinate of the polygon displayed on the odd line and / or the minimum Y coordinate of the polygon displayed on the even line immediately before the odd line are the same. As a result, the sorting by the sorting rule 2 is performed. However, the first odd line is excluded. This is because there is no previous even line. On the other hand, in the sorting for displaying the even field, the minimum Y coordinate of the polygon displayed on the even line and / or the minimum Y coordinate of the polygon displayed on the odd line immediately before the even line are the same. As a result, the sorting by the sorting rule 2 is performed. This is sort rule 4.

  Sort rules 1 to 4 for sprites are the same as sort rules 1 to 4 for polygons, respectively.

  The external memory interface 3 is responsible for reading data from the external memory 50 and writing data to the external memory 50 via the external bus 51. In this case, the external memory interface 3 arbitrates external bus access request factors (factors requesting access to the external bus 51) from the CPU 5 and the DMAC 4 in accordance with an EBI priority table (not shown), and any one of the external buses Select the access request factor. Then, access to the external bus 51 is permitted for the selected external bus access request factor. The EBI priority table is a table that defines priorities of a plurality of types of external bus access request factors from the CPU 5 and external bus access request factors from the DMAC 4.

  As external bus access request factors, there are a block transfer request by an IPL (initial program loader) (not shown) included in the CPU, a data access request by the CPU 5, an instruction fetch request by the CPU 5, and a DMA request by the DMAC 4.

  The DMAC 4 performs DMA transfer between the main RAM 25 and the external memory 50 connected to the external bus 51. In this case, the DMAC 4 arbitrates DMA transfer request factors (factors that request DMA transfer) from the CPU 5, RPU 9, and SPU 13 according to a DMA priority table (not shown), and selects any one DMA transfer request factor. . Then, a DMA request is made to the external memory interface 3. The DMA priority table is a table that defines the priority of DMA request factors from the CPU 5, RPU 9, and SPU 13.

  The DMA request factors of the SPU 13 include (1) transferring wave data to the wave buffer and (2) transferring envelope data to the envelope buffer. The wave buffer and envelope buffer are temporary storage areas for wave data and envelope data set on the main RAM 25, respectively. The arbitration between the two DMA request factors of the SPU 13 is performed by hardware (not shown) in the SPU 13, and the DMAC 4 is not concerned.

  As a DMA request factor of the RPU 9, there is transferring the texture pattern data to the texture buffer. The texture buffer is a temporary storage area for texture pattern data set on the main RAM 25.

  The DMA request factors of the CPU 5 include (1) page transfer when a page miss occurs in virtual storage management, and (2) data transfer requested by an application program or the like. When a plurality of DMA transfer requests are generated simultaneously in the CPU 5, the arbitration is performed by software executed by the CPU 5, and the DMAC 4 is not concerned.

  The external interface block 21 is an interface with the peripheral device 54 and includes a 24-channel programmable digital input / output (I / O) port. Each 24 channel I / O port has 4 channels of mouse interface function, 4 channels of light gun interface function, 2 channels of general-purpose timer / counter, 1 channel of asynchronous serial interface function, 1 channel Are internally connected to one or more of the general-purpose parallel / serial conversion port functions.

  The ADC 33 is connected to 4-channel analog input ports, and converts the analog signal input from the analog input device 52 into a digital signal via these. For example, an analog input signal such as a microphone sound is sampled and converted into digital data.

  The main RAM access arbiter 23 arbitrates an access request to the main RAM 25 from the functional units (CPU 5, RPU 9, GE 17, YSU 19, DMAC 4, and external interface block 21 (general-purpose parallel / serial conversion port), and has any function. Grant access to the unit.

  The main RAM 25 is used as a work area, a variable storage area, a virtual storage management area, and the like for the CPU 5. Further, the main RAM 25 is a storage area for data that the CPU 5 delivers to other functional units, a storage area for data that the RPU 9 and SPU 13 have acquired from the external memory 50 by DMA, a storage area for input data and output data for the GE 17 and YSU 19, etc. Also used as

  The external bus 51 is a bus for accessing the external memory 50. It is accessed from the CPU 5 and the DMAC 4 via the external memory interface 3. The address bus of the external bus 51 is composed of 30 bits, and an external memory 50 having a maximum of 1 Gbyte (= 8 Gbit) can be connected thereto. The data bus of the external bus 51 is composed of 16 bits, and can connect an external memory 50 having a data bus width of 8 bits or 16 bits. External memories having different data bus widths can be connected at the same time, and a function of automatically switching the data bus width according to the external memory to be accessed is provided.

  Next, an outline of graphics processing by the multimedia processor 1 will be described.

  FIG. 2 is a flowchart showing an outline of the flow of graphics processing by the multimedia processor 1 of FIG. As shown in FIG. 2, in step S1, the CPU 5 enlarges each object (a unit composed of one or a plurality of polygons to which the same enlargement / reduction, rotation, and translation conversion are applied) and each sprite. Calculate the parameters for reduction, rotation and translation. From the calculated parameters, a transformation matrix for enlargement / reduction, rotation, and translation is generated for each object and each sprite. These transformation matrices are used to convert each object and sprite's local coordinate system (local coordinate system) to an orthogonal coordinate system (world coordinate system) that expresses all objects and all sprites in a unified coordinate system. Used.

  Further, the CPU 5 updates the viewpoint (camera) coordinates, the target point coordinates, the line-of-sight vector, and the like. From these parameters, a transformation matrix from the world coordinate system to an orthogonal coordinate system (view coordinate system) centered on the viewpoint is generated.

  In step S2, when there are a plurality of transformation matrices for enlargement / reduction, rotation, and translation for each object and each sprite, the GE 17 obtains a matrix product of the transformation matrices to obtain a plurality of transformation matrices. Combine transformation matrices into a single transformation matrix. Further, the GE 17 obtains a matrix product of the synthesized transformation matrix and the transformation matrix for the coordinate system transformation, and transforms the object vertex coordinate array, the object normal vector array, and the sprite coordinates. Are synthesized respectively.

  In step S3, the GE 17 performs geometric transformation of the object vertex coordinate array, the object normal vector array, and the sprite coordinates using the synthesized transformation matrix. Further, the GE 17 calculates the inner product of the converted object normal vector array and the light source vector, and calculates the brightness of each vertex or surface (polygon) of the object. The result of such geometric transformation and lighting is stored in the polygon structure array and the sprite structure array.

  In step S4, before the drawing process by the RPU 9 is performed, the YSU 19 sorts the polygon structure instance and the sprite structure instance according to the sorting rules 1 to 4.

  In step S5, the RPU 9 reads the polygon structure instance and the sprite structure instance after sorting by the YSU 19, and reads the texture attribute structure instance indicating the attributes of the polygon and sprite in the texture mapping mode, Generate a pixel data string. Further, in order to generate pixel data strings of polygons and sprites in the texture mapping mode, it is necessary to read out the texture pattern data to be pasted from the external memory 50. Such pixel data string generation processing is called “rasterizing”.

  In this embodiment, a texture mapping mode for drawing using texture mapping and a Gouraud shading mode for drawing polygons using Gouraud shading are implemented as polygon drawing modes. Texture mapping is a drawing technique in which texel patterns arranged in a two-dimensional grid are pasted on the polygon surface. Gouraud shading is a type of smooth shading used to express a pseudo smooth surface with a small number of polygons. In Gouraud shading, the drawing color of each pixel in the polygon is obtained by linearly complementing the vertex color of the polygon specified independently.

  The RPU 9 performs scissoring. Scissoring is a process of cutting off a portion that protrudes from a specified viewport area and not displaying it when generating a pixel data string of polygons and sprites. The generated pixel data string is written to a line buffer (not shown) in the RPU 9, and when the writing pixel is set to a semi-transparent color, the color of the pixel in the line buffer and the writing pixel are set. Color blending that mixes colors is performed.

  In step S6, the RPU 9 reads information on each pixel to be displayed from the line buffer, adds a synchronization signal, a color burst signal, and the like to generate a digital data stream of the composite video signal. The generated data stream is input to the video DAC 29, and an analog composite video signal is output from the video DAC 29.

  Now, before entering the detailed description of the GE 17, a coordinate system in the three-dimensional graphics processing will be described.

  The three-dimensional orthogonal coordinate system includes a left-handed coordinate system and a right-handed coordinate system. In the present embodiment, a right-handed coordinate system is adopted. The right-handed coordinate system is a coordinate system in which the thumb, the index finger, and the middle finger stand upright to each other, the thumb is positive on the X axis, the index finger is positive on the Y axis, and the middle finger is positive on the Z axis. .

  The local coordinate system is a three-dimensional coordinate system in which the coordinates of each vertex constituting the object are expressed as a relative value from the origin of the object itself. The coordinates of each vertex of the object are represented by values in the local coordinate system and stored in an external memory 50 such as a ROM. Some objects have a hierarchical structure in the local coordinate system.

  The world coordinate system is a common three-dimensional coordinate system for all objects constituting one scene. The movement and rotation of each object and viewpoint (camera) are usually calculated in this coordinate system.

  The view coordinate system is a three-dimensional orthogonal coordinate system in which the position of the viewpoint (camera) is the origin, and the horizontal right direction and the vertical downward direction of the viewpoint are positive on the X axis and the Y axis, respectively. In this coordinate system, the value of the line-of-sight vector (X, Y, Z) is given as (0, 0, −1), and is defined as a unit vector from the target point to the viewpoint.

  The perspective coordinate system is a two-dimensional coordinate system obtained by perspective projection conversion of an object in the view coordinate system. Perspective projection is a projection technique for obtaining an image viewed from the human eye in which an object close to the viewpoint is large and a distant object is small. The transformation that performs this projection is called perspective projection transformation. When performing perspective projection conversion, it is necessary to specify the distance from the viewpoint to the projection plane. The origin of this coordinate system is located at the center of the space, and the coordinates are represented by a signed value.

  The screen coordinate system is a two-dimensional coordinate system used for screen display. However, the area actually displayed on the screen is a part of this coordinate space. The origin of this coordinate system is located at the upper left of the entire space, and the coordinates are represented by unsigned values. The coordinate system handled by the RPU 9 is only this coordinate system.

  As described above, the coordinates of each vertex of the object are stored in the external memory 50 as values in the local coordinate system. Therefore, when displaying three-dimensional graphics, the coordinate system is converted to the final value. Must be converted to a screen coordinate system for display on the screen.

  FIG. 3 is a diagram illustrating an example of a coordinate conversion flow in the present embodiment. FIG. 3 shows conversion of the vertex coordinate array of the polygon as an example. Referring to FIG. 3, the process of step S11 is performed only on objects having a hierarchical structure. In step S <b> 11, the multimedia processor 1 generates a local transformation matrix by synthesizing the transformation matrices of the respective layers, and uses this to convert vertex coordinates (local transformation). The transformation matrix itself is defined as a three-dimensional affine transformation matrix.

  In step S12, the multimedia processor 1 converts the vertex coordinates from the local coordinate system to the world coordinate system using the world conversion matrix (world conversion). The enlargement / reduction, rotation, and translation of each object are calculated in this coordinate system. The transformation matrix itself is defined as a three-dimensional affine transformation matrix.

  In step S13, the multimedia processor 1 converts the vertex coordinates of the world coordinate system into the view coordinate system using the view conversion matrix (view conversion). The transformation matrix itself is defined as a three-dimensional affine transformation matrix.

  In step S14, the multimedia processor 1 converts the vertex coordinates of the view coordinate system to the perspective coordinate system based on the distance from the viewpoint to the projection plane (perspective projection conversion). When the XYZ coordinate in the view coordinate system is (xv, yv, zv), the XY coordinate in the perspective coordinate system is (xp, yp), and the distance from the viewpoint to the projection plane is “d”, the perspective projection transformation is It is represented by

  In step S15, the multimedia processor 1 converts the vertex coordinates of the perspective coordinate system into the screen coordinate system using the offset values of the X component and the Y component (viewport conversion). In the perspective coordinate system, the vertex coordinates of the polygon are values with a sign centered on the origin. On the other hand, in the screen coordinate system actually used for screen display, since it is an unsigned value with the upper left as the origin, it is necessary to add a certain offset to the vertex coordinates of the polygon and move it (sprite) The same applies to. In addition, when providing a plurality of viewports on the screen such as an application for multiplayer, it is necessary to move to each viewport position (the same applies to sprites). These are viewport transformations.

  When the XY coordinates in the perspective coordinate system are (xp, yp), the XY coordinates in the screen coordinate system are (xs, ys), and the offset values added to the XY coordinates are “offx” and “offy”, respectively, the viewport The conversion is expressed by the following equation.

  Here, the transformation matrices in steps S11 to S13 are synthesized in advance, and a transformation matrix that can perform each transformation at a time is generated. For this reason, each conversion of step S11 to S13 is performed at once. That is, the local transformation three-dimensional affine transformation matrix, the world transformation three-dimensional affine transformation matrix, and the view transformation three-dimensional affine transformation matrix are combined and these coordinate transformations are performed collectively.

  Next, three-dimensional affine transformation and three-dimensional orthogonal transformation will be described. When a vector (x ′, y ′, z ′) obtained by converting a vector (x, y, z) in a three-dimensional orthogonal space is expressed as follows, this conversion is called a three-dimensional affine transformation.

  In this conversion, enlargement / reduction, rotation, and translation can be performed. When the transformation matrix for performing this transformation is expressed in homogeneous coordinates, the following quartic square matrix is obtained.

  In the multimedia processor 1, the three-dimensional affine transformation is mainly used for transformation of polygon vertex coordinates. When performing three-dimensional three-dimensional affine transformation on one vector, it is possible to synthesize a plurality of transformation matrices into one transformation matrix using a matrix combination rule. In relation to the affine transformation, the GE 17 is provided with a command “MatrixMulti” for obtaining a matrix product and a command “Affine” for performing a three-dimensional affine transformation. These commands will be described in detail later.

  When a vector (x ′, y ′, z ′) obtained by converting a vector (x, y, z) in a three-dimensional orthogonal space is expressed as follows, this conversion is called a three-dimensional orthogonal transformation.

  In this conversion, enlargement / reduction and rotation can be performed. A conversion matrix for performing this conversion is represented by the following cubic matrix.

  In the multimedia processor 1, the three-dimensional vector orthogonal transformation is mainly used for the conversion of the vertex normal vector and the polygon (surface) normal vector. When a plurality of three-dimensional vector orthogonal transformations are performed on one vector, it is possible to synthesize a plurality of transformation matrices into one transformation matrix using matrix combination rules. In relation to the three-dimensional vector orthogonal transformation, the GE 17 is provided with a command “MatrixMulti” for obtaining a matrix product and a command “Trans” for performing the three-dimensional vector orthogonal transformation. These will be described in detail later.

  Next, various processes performed by the GE 17 will be described with reference to the drawings as appropriate. First, vertex coordinate conversion will be described.

  FIG. 4 is a flowchart showing a flow of polygon vertex coordinate conversion processing by the GE 17. First, a vertex coordinate array is prepared as input data. The format of this vertex coordinate array is a Vector10 structure described later, and each member is a vertex coordinate of the local coordinate system.

  In step S21, the GE 17 performs an affine transformation from the local coordinate system to the view coordinate system on the vertex coordinates by the command “Affine”, and outputs the vertex coordinates of the view coordinate system. Before executing the command, each element of the transformation matrix from the local coordinate system to the view coordinate system is stored in registers GR0 to GR11 described later in the GE17. The format of the output data is a Vector32 structure described later.

  In step S22, the GE 17 performs perspective projection conversion from the view coordinate system to the perspective coordinate system on the vertex coordinates converted to the view coordinate system by the command “Pproj”, and outputs the vertex coordinates of the perspective coordinate system. To do. Before executing the command, the distance from the viewpoint to the projection plane is stored in a register “Distance” described later in the GE 17. The format of the output data is a Vector16 structure described later.

  In step S23, the GE 17 performs viewport conversion from the perspective coordinate system to the screen coordinate system on the vertex coordinates converted to the perspective coordinate system by the command “View”, and outputs the vertex coordinates of the screen coordinate system. To do. Before executing the command, the X coordinate offset value and the Y coordinate offset value are stored in registers “ViewportOffsetX” and “ViewportOffsetY” to be described later in the GE 17. The format of the output data is a Vector16 structure described later.

  Here, instead of executing each of the commands “Affine”, “Pproj”, and “View” independently, it is also possible to execute these processes collectively by the command “APV”.

  This vertex coordinate conversion process can be used not only for polygon vertex coordinate conversion but also for sprite coordinate conversion.

  Next, lighting will be described. In standard 3D graphics handled by the multimedia processor 1, it is assumed that only one parallel light source exists in the world coordinates as a light source. That is, the coordinates of the light source are not set, and the direction of the arrow pointing to the light source is set as the light source vector. An example of a parallel light source is sunlight.

  In the standard lighting process handled by the multimedia processor 1, the object surface is assumed to perform 100% diffuse reflection, and specular reflection is not considered. Here, 100% diffuse reflection is defined as “the incident light is uniformly reflected in all directions”. In this case, the brightness does not change regardless of the direction of the surface of the object. That is, the brightness of the object surface is determined only by the angle formed by the normal vector of the surface and the light source vector, and is not affected by the position of the viewpoint. Accordingly, the diffuse light brightness “diffuse” is obtained from the inner product of two vectors as shown in the following equation. However, if the inner product operation result is negative, the result is saturated to “0”.

  In (Expression 7), a vector L is a light source vector (unit vector), a vector N is a unit normal vector on the object surface, and an angle θ is an angle formed by the vector L and the vector N.

  However, with this lighting model, the lighting result cannot be obtained correctly when the object surface is viewed from the back side. For this reason, when looking at the surface illuminated by the light source regardless of the front and back of the object, that is, when the sign of the inner product of the vector L and the vector N is equal to the sign of the inner product of the line-of-sight vector and the vector N, A correct lighting result is obtained by obtaining the absolute value of the inner product calculation result of the unit normal vector on the object surface and the light source vector. If this is rearranged, the formula for calculating the diffused light brightness in (Expression 7) is corrected as follows.

  In (Equation 8), the vector V is a line-of-sight vector (unit vector), and the angle θ ′ indicates an angle formed by the vector V and the vector N. The line-of-sight vector should be given as a vector from the point where the normal vector is set on the object surface to the viewpoint, but each line-of-sight vector is calculated for all vertices and polygons (surfaces) to which lighting is applied. In this case, since the amount of calculation becomes enormous, the lighting model of the multimedia processor 1 always treats the line-of-sight vector in the view coordinate system as (0, 0, −1).

  Up to this point, the vector N is treated as a unit normal vector on the object surface. However, as will be described later, in the lighting processing for polygons in texture mapping mode, the normal vector of the polygon (surface) is treated as input data, In the lighting process for the polygon in the shading mode, the normal vector for the vertex of the polygon is handled as input data. Therefore, the vector N is treated as a “polygon (surface) unit normal vector” or “vertex unit normal vector” depending on the drawing mode of the polygon to be illuminated.

  By the way, an object that exists in an actual space is not illuminated only by a light source that emits light such as the sun or an electric light, but light reflected by another object or another surface of the object itself further illuminates the object surface. If this is obtained by calculation, the calculation amount becomes enormous, and is not suitable for generating real-time 3D graphics. However, if only the reflected light of a single parallel light source is modeled, the surface of the polygonal table (front) will be used when the angle between the light source vector and the normal vector is π / 2 radians (= 90 degrees) or more. Will not be exposed to light at all. As a result, the front surface of the polygon is drawn in black, resulting in an expression lacking reality.

  Therefore, the multimedia processor 1 takes an expression in which a constant value is added to the diffuse light intensity “diffuse” as the ambient light intensity “ambient” on all surfaces of the object. Therefore, the brightness of the polygon / vertex “brightness” is obtained as follows.

  However, since the addition is performed as a saturation operation as described above, when the addition result is 1.0 or more, the result is saturated to 1.0.

  Next, lighting processing in the texture mapping mode will be described using a flowchart. Note that the lighting process is performed in units of polygons (surfaces) for polygons in texture mapping mode.

  FIG. 5 is a flowchart of lighting processing for polygons in the texture mapping mode. First, a normal vector array for each polygon (surface) is prepared as input data. The number of elements and the order of arrangement in this array need to match the number of elements and the order of arrangement in a polygon structure array (to be described later) that stores output data. Each element of the normal vector array is a Vector10 structure to be described later, and indicates a unit normal vector in the local coordinate system.

  When the object is not deformed, it is preferable to store the unit normal vector of the local coordinate system calculated in advance in the external memory 50. On the other hand, when the unit normal vector of each polygon (surface) needs to be calculated in real time, such as when the object is deformed, it is calculated using the outer product of the vectors. If the front surface of the polygon (or the visible surface of the single-sided polygon) is the side on which the vertex ABC is arranged clockwise, the unit normal vector N of the polygon can be obtained by the following equation. In the present embodiment, the polygon is limited to a triangle.

  In (Equation 10), vector B is a vector from vertex A to vertex B, and vector C is a vector from vertex A to vertex C.

  In step S31, the GE 17 performs orthogonal transformation (rotation transformation) from the local coordinate system to the view coordinate system with respect to the polygon normal vector by the command “Trans”, and obtains the unit normal vector of the view coordinate system. Output. Before executing the command, each element of the transformation matrix from the local coordinate system to the view coordinate system is stored in the registers GR0 to GR8 in the GE17. The format of the output vector is a Vector32 structure described later.

  In step S32, the GE 17 calculates the inner product of the polygon normal vector in the view coordinate system and the light source vector in the view coordinate system by the command “Dot”, and outputs the result to the polygon brightness array. Before executing the command, each element of the light source vector in the view coordinate system is stored in the registers “LightVX”, “LightVY”, and “LightVZ” in the GE 17. The format of the output data is a Dot structure which will be described later.

  In step S33, the GE 17 uses the command “Bright-P” to calculate the inner product operation result of the normal vector of the polygon in the view coordinate system and the light source vector in the view coordinate system stored in the Dot structure array, The brightness for each polygon (surface) is calculated from the ambient light brightness stored in the register “Ambient” and stored as a member “Light” of a polygon structure array, which will be described later.

  Instead of executing the commands “Trans”, “Dot”, and “Bright-P” individually, these processes can be executed collectively by the command “TDBP”.

  The RPU 9 calculates the drawing color of each pixel of the polygon from the multiplication result of the value of the member “Light” of the polygon structure instance and the RGB value of each texel read from the color palette RAM 11 during the drawing process. Therefore, the value set in the color palette RAM 11 is the color data when the brightness is 100%, that is, the original color data of the texture.

  Next, lighting processing in the Gouraud shading mode will be described using a flowchart. Note that lighting processing is performed on a vertex basis for polygons in Gouraud shading mode.

  FIG. 6 is a flowchart showing the flow of lighting processing in the Gouraud shading mode. Referring to FIG. 6, first, a normal vector array for each vertex is prepared as input data. The number of elements and the arrangement order of this array must match the number of elements and the arrangement order of the vertex coordinate array in the screen coordinate system referred to by a polygon structure array described later that stores output data. Each element of the normal vector array is a Vector10 structure to be described later, and indicates a unit normal vector in the local coordinate system.

  When the object is not deformed, it is preferable to store the unit normal vector of the local coordinate system calculated in advance in the external memory 50. On the other hand, when it is necessary to calculate the unit normal vector of each vertex in real time, such as when the object is deformed, as an example of the calculation method, it is approximated by the average of the unit normal vectors of polygons (faces) sharing the vertex. A method is mentioned.

  In step S41, the GE 17 performs orthogonal transformation (rotation transformation) from the local coordinate system to the view coordinate system with respect to the vertex normal vector by the command “Trans” to obtain the unit normal vector of the view coordinate system. Output. Before executing the command, each element of the transformation matrix from the local coordinate system to the view coordinate system is stored in the registers GR0 to GR8 in the GE17. The format of the output vector is a Vector32 structure described later.

  In step S42, the GE 17 calculates the inner product of the normal vector of the vertex in the view coordinate system and the light source vector in the view coordinate system by the command “Dot”, and outputs the result to the vertex brightness array. Before executing the command, each element of the light source vector in the view coordinate system is stored in the registers “LightVX”, “LightVY”, and “LightVZ” in the GE 17. The format of the output data is a Dot structure which will be described later.

  In step S43, the GE 17 first executes the inner product calculation result of the normal vector of the vertex in the view coordinate system and the light source vector in the view coordinate system stored in the Dot structure array by the command “Ccalc”, The brightness for each vertex is calculated from the ambient light brightness stored in the register “Ambient”. Thereafter, from the multiplication result of the calculated brightness of the vertex and the RGB value of each vertex stored in the members “Ac”, “Bc”, and “Cc” of the polygon structure instance, each vertex after lighting is calculated. The RGB values are calculated and written back to the members “Ac”, “Bc”, and “Cc” of the polygon structure instance.

  Instead of executing the commands “Trans” and “Dot” independently, these processes can be executed collectively by the command “TD”.

  The RPU 9 calculates the drawing color of each pixel of the polygon by linear interpolation from the RGB values of each vertex stored in “Ac”, “Bc”, and “Cc” of the polygon structure instance during the drawing process.

  Next, back surface culling will be described. Polygons handled by the multimedia processor 1 include single-sided polygons and double-sided polygons. Since single-sided polygons are defined as those that are not displayed when viewed from the back side, drawing on the back side of single-sided polygons can be omitted, so that drawing processing is not wasted and overall drawing ability can be improved. . The process of omitting the drawing of the back side of a single-sided polygon is called back side culling.

  FIG. 7A is an exemplary diagram of the front surface of the polygon, and FIG. 7B is an exemplary diagram of the back surface of the polygon. As shown in FIGS. 7A and 7B, the multimedia processor 1 determines the front and back of the polygon P in the order of apexes. That is, the surface where the vertices ABC of the polygon P can be viewed side by side in the clockwise direction is defined as the “front surface”, and the surface that is viewed in the counterclockwise direction is defined as the “back surface”. Based on such a definition, an outer product of vectors can be used to determine whether the polygon P is front or back.

  The vector a × b obtained by the outer product of the vector a and the vector b is perpendicular to the vectors a and b, and is directed in the screw traveling direction when the right screw is turned from the vector a to the vector b. Therefore, by calculating the inner product of the vector a × b and the line-of-sight vector, it is possible to determine which side of the front and back is visible when viewing the polygon P from the viewpoint.

  In the polygon front / back determination performed by the GE 17, polygons converted into the screen coordinate system are used, and the Z coordinates of the vertices of all the polygons are regarded as the same value. Even if it does in this way, since the relationship between the front and back viewed from the viewpoint does not change, there is an advantage that the calculation of the outer product can be simplified.

  For example, the components of the vector a, the vector b, and the vector a × b in the three-dimensional orthogonal coordinate system are respectively (Xa, Ya, Za), (Xb, Yb, Zb), and (Xab, Yab, Zab), each component of the vector a × b is obtained as follows.

  However, since GE17 considers Za = Zb = 0, only the following equation is executed.

  If the XY coordinates of the vertex ABC of the polygon in the screen coordinate system are (Ax, Ay), (Bx, By), and (Cx, Cy), respectively, the Z component Vz of the outer product of the vectors for front / back determination is It becomes like this.

  In response to the command “CWD”, the GE 17 selects the members “Ax”, “Ay”, “Bx”, “By”, “Cx”, and “Cy” of the polygon structure instance in which the vertex coordinates of the screen coordinate system are stored. The Z component Vz of the outer product of the vectors is obtained from the value of "."

  Further, the GE 17 determines whether the polygon is a “single-sided polygon” or a “double-sided polygon” from the member “Face” of the polygon structure instance, and performs back surface culling processing as described below. That is, the GE 17 performs back surface culling when the member “Face” = 0 (that is, a single-sided polygon), and Vz ≧ 0, and when the member “Face” = 1 (that is, a double-sided polygon). Do not perform backside culling.

  The GE 17 sets “2047” (the maximum value of the X coordinate) to the members “Ax”, “Bx”, and “Cx” of the polygon structure instance to be back-culled, and sets the members “Ay”, “By”. ”And“ Cy ”are set to“ 1023 ”(the maximum value of the Y coordinate), respectively.

  Also, when the command “CWD” is issued and the field “InvalidStructureRemove” of the register “GECommand” in the GE 17 is set to “1”, the GE 17 outputs the polygon structure instance that has been back-culled to the output polygon. Remove from the structure array and store only valid polygon structure instances in the array, padded.

  Next, view volume clipping will be described. View volume clipping is a function for realizing efficient drawing processing by omitting drawing of polygons that are too close to the viewpoint or far from the viewpoint, or polygons that protrude from the screen coordinate system after perspective projection conversion. It is.

  The view volume clipping in the multimedia processor 1 is performed in the view volume in which the vertex coordinates are set by the commands “Pproj” and “View” (or the composite command “APV” including the commands “Pproj” and “View”) for the GE 17. And culling a polygon structure instance having a vertex not in the view volume by a command “CWD” to the GE 17. These will be described with reference to the drawings.

  FIG. 8 is an explanatory diagram of view volume clipping. Referring to FIG. 8, the near clip plane NC is defined by a register “ZNear” in the GE 17, and the far clip plane FC is defined by a register “ZFar” in the GE 17. The view volume VV is a space surrounded by the near clip surface NC and the far clip surface FC. The GE 17 tests whether the value of the Z coordinate of the vertex of the view coordinate system is within the range of the view volume VV before performing perspective projection conversion.

  The GE 17 is a member of the Vector 16 structure that stores the vertex coordinates in the screen coordinate system when the Z coordinate of the vertex in the view coordinate system is less than the value of the register “ZNear” or exceeds the value of the register “ZFar”. Set “1” to “Clipping”. In addition, the GE 17 determines that the value of the vertex X coordinate in the screen coordinate system after the viewport conversion by the command “View” is less than “0” or greater than “2048”, or the value of the vertex Y coordinate in the screen coordinate system is “0”. "1" is set to the member "Clipping" of the Vector16 structure that stores the vertex coordinates in the screen coordinate system even when the value is less than "" or greater than "1024".

  Then, according to the command “CWD”, the GE 17 refers to the vertex coordinate array in the screen coordinate system and sets the vertex coordinates of the polygon structure instance. At this time, “1” is set to the member “Clipping”. If the selected vertex is included in any of the three vertices of the polygon structure instance, the polygon structure instance is culled. That is, “2047” is set for each of the members “Ax”, “Bx”, and “Cx” of the polygon structure instance, and “1023” is set for each of the members “Ay”, “By”, and “Cy”. To do.

  Further, when the command “CWD” is issued and the field “InvalidStructureRemove” of the register “GECommand” in the GE 17 is set to “1”, the GE 17 outputs the polygon structure instance to which the culled polygon structure instance is output. Remove from the body array and store only valid polygon structure instances in the array justified.

  Next, perspective correction (perspective correction) will be described.

  FIG. 9A is an exemplary diagram of texture mapping subjected to perspective correction, and FIG. 9B is an exemplary diagram of texture mapping not subjected to perspective correction. In texture mapping expressing a perspective projection transformed three-dimensional image, the texel UV coordinate corresponding to the drawing pixel on the screen is obtained by mere linear interpolation of the texel UV coordinate corresponding to each vertex coordinate of the polygon. As shown in FIG. 9B, the mapped image may be distorted. In particular, when there is a large difference in the Z coordinate (depth) of the vertices, the distortion becomes large, and problems such as unnatural appearance of a joint of a plane composed of a plurality of triangular polygons occur. Therefore, in order to eliminate such distortion and generate an image without distortion as shown in FIG. 9A, a function of perspective correct (perspective correction) is installed.

  Here, the UV coordinate system is a two-dimensional orthogonal coordinate system for storing texel data, and a space defined by the UV coordinates is a UV space. The coordinates when the vertices A, B, and C of the triangular polygon are mapped to the UV space are (Au, Av), (Bu, Bv), and (Cu, Cv). Further, XYZ coordinates in the view coordinate system of the vertices A, B and C are (Ax, Ay, Az), (Bx, By, Bz) and (Cx, Cy, Cz).

  When doing so, it is obtained by linear interpolation of (Au / Az, Av / Az, 1 / Az), (Bu / Bz, Bv / Bz, 1 / Bz) and (Cu / Cz, Cv / Cz, 1 / Cz). Value u / z, v / z, 1 / z multiplied by the inverse of “1 / z”, and “v / z” is the inverse of “1 / z” Accurate texture mapping after perspective projection conversion is realized by acquiring texel data using the value v multiplied by as texel coordinates (u, v) in the UV space.

  However, in the multimedia processor 1, instead of setting “1 / Az”, “1 / Bz” and “1 / Cz” for each vertex, “Az” is set to “1 / Bz” and “1 / Cz”. The multiplied values, that is, “Az / Bz” and “Az / Cz” are set to the members “Bw” and “Cw” of the polygon structure instance, respectively. However, since the parameter for the vertex A is always “1”, it is not included in the polygon structure.

  The command “CWD” indicates that the value of the member “Type” of the polygon structure instance indicates “0” (that is, in the texture mapping mode) and the member “Bw” and the polygon structure instance that is not culled are A process of calculating “Cw” is performed.

  Next, calculation of the depth value indicating the drawing priority will be described. The RPU 9 draws polygons according to drawing priority in polygon units. Therefore, the GE 17 needs to calculate a depth value representing the drawing priority of polygons from the Z coordinates of the three vertices of the polygons in the view coordinate system. The polygon is drawn in the back (first) as the depth value increases, and is drawn toward the front (after) as the depth value decreases. The depth value is stored in the member “Depth” of the polygon structure instance to be drawn.

  The member “Depth” of the polygon structure is a 12-bit floating point number, and consists of a lower 8-bit mantissa field and an upper 4-bit exponent field. The value indicated by the member “Depth” in the 12-bit floating point number format is represented by the following expression.

  In (Expression 14), “M” indicates a mantissa field, and “E” indicates an exponent field. “DEB” indicates a bias (getter) with respect to the exponent field E, and is set as a 3-bit value indicating one of 0 to 7 in the register “DepthBias” in the GE 17.

  Since the member “Depth” is an unsigned value, no sign bit is provided. The mantissa is 1. Normalized in the form of ******, but the mantissa field does not include the MSB "1", and the actual mantissa is a value obtained by adding 1.0 to the 8 bits of the mantissa field. (So-called “implicit 1” is set). The exponent field is a so-called “gettery expression” with a bias added.

  In response to the command “CWD”, the GE 17 refers to the vertex coordinate array of the view coordinate system, and the members “Clipping” (Vector16 structure) corresponding to the three vertexes of the polygon are all “0” (that is, no culling). In this case, depth value calculation is executed. The GE 17 converts the result of adding all the Z coordinates of the three vertices of the polygon into the above-mentioned 12-bit floating point number format, and converts the conversion result value and the depth initial value stored in the member “Depth” of the polygon structure instance. The value is added, and the addition result is written back to the member “Depth”. Note that the depth initial value is a 12-bit signed value (2's complement). Also, the rounding mode for obtaining 8 bits of the mantissa field is truncation.

  As described above, the depth value for each vertex is not given to the polygon, but only the depth value for each polygon is given.

  Next, details of the internal configuration of the GE 17 will be described.

  FIG. 10 is a block diagram showing an internal configuration of the GE 17 in FIG. Referring to FIG. 10, the GE 17 includes an execution unit 100, a control unit 200, an I / O register set 300, and a load / store unit 400.

  The I / O register set 300 includes a register for writing a command executed by the GE 17, a register for performing various controls of the GE 17, and a register for storing an input argument used for the command. The CPU 5 can access all these registers through the I / O bus 27. Details of each register will be described later. The I / O register set 300 outputs an interrupt request signal IRQ to the CPU 5 when the command is completed. However, this is limited to the case where the output of the interrupt request signal IRQ from the GE 17 is enabled.

  The control unit 200 follows the command written in the register “GECommand” (described later) included in the I / O register set 300 and the number of command repetitions written in the register “RepeatCount” included in the I / O register set 300. The execution unit 100 and the load / store unit 400 are controlled to execute a command.

  The state of the control signal in each cycle of each command is stored as microcode. In the present embodiment, the microcode is hardwired and thus indicates a fixed value. However, when the microcode storage area is configured by RAM or EEPROM, the microcode can be made variable. If the microcode is made variable, the die area (area on the semiconductor) increases, but the GE 17 command can be optimized according to the required processing. Further, the control unit 200 outputs a command execution flag indicating whether or not the command is being executed and a command completion flag asserted when the command is completed to the I / O register set 300. The states of these flags are reflected in the register “GEStatus” included in the I / O register set 300.

  The execution unit 100 includes various arithmetic units and executes various arithmetic operations according to the control of the control unit 200. Also, read data from the main RAM 25 is received through the load / store unit 400 and used as an input value for the operation, and the operation result is written to the main RAM 25 as write data.

  The load / store unit 400 issues a read request or a write request for the main RAM 25 to the main RAM access arbiter 23 according to the address and the control signal input from the control unit 200. When the read request is accepted, the read data read from the main RAM 25 is transferred to the execution unit 100. When the write request is accepted, the write data received from the execution unit 100 is transferred to the main RAM access arbiter 23.

  FIG. 11 is an explanatory diagram of various registers included in the I / O register set 300 of FIG. As illustrated in FIG. 11, the I / O register set 300 includes registers “GR0” to “GR15”, a register “Distance”, a register “ZNear”, a register “ZFar”, a register “ViewportOffsetX”, a register “ViewportOffsetY”, a register “Ambient”, register “LightVX”, register “LightVY”, register “LightVZ”, register “DepthBias”, register “GECommand”, register “GEStatus”, register “RepeatCount”, register “PolyCount”, register “GESourA register” “GEDestinationAddress” and register “GEBaseAddress” Including the. Each register is arranged at a corresponding I / O bus address in the figure.

  The registers “GR0” to “GR15” are registers for storing input data or output data when executing each command. Each of the registers “GR0” to “GR15” has 32 bits. Some commands may be used in units of half words (16 bits).

  The register “Distance” designates the distance from the viewpoint to the projection plane in the perspective projection transformation as a 16-bit unsigned integer. The register “ZNear” designates a near clip value (view clip plane NC in FIG. 8) of view volume clipping performed at the time of perspective projection conversion by a 16-bit unsigned integer. The register “ZFar” specifies a far clip value (far clip plane FC in FIG. 8) of view volume clipping performed at the time of perspective projection conversion by a 16-bit unsigned integer.

  The register “ViewportOffsetX” designates an offset value (“offx” in (Expression 2)) to be added to the X coordinate at the time of viewport conversion as a 12-bit unsigned fixed-point number. The register “ViewportOffsetY” designates an offset value (“offy” in (Expression 2)) to be added to the Y coordinate at the time of viewport conversion by a 12-bit unsigned fixed-point number. The register “Ambient” designates the value of the ambient light brightness required for calculating the polygon brightness or the polygon vertex color as an unsigned fixed-point number (see (Expression 9)).

  The register “LightVX” designates the X component of one vector input at the time of vector inner product calculation by a signed fixed-point number. It is assumed that the X component of the light source vector in the view coordinate system is set. The register “LightVY” designates the Y component of one vector input at the time of vector inner product calculation by a signed fixed-point number. It is assumed that the Y component of the light source vector in the view coordinate system is set. The register “LightVZ” designates the Z component of one vector input at the time of vector inner product calculation by a signed fixed-point number. It is assumed that the Z component of the light source vector in the view coordinate system is set. Refer to step S32 in FIG. 5 and step S42 in FIG.

  The register “DepthBias” sets the bias (getter) of the exponent part of the depth value Depth of the polygon. When the bias value is “DEB”, the mantissa part of the depth value Depth is “M”, and the exponent part is “E”, the depth value Depth is as shown in (Expression 14).

  The register “GECommand” is a register for setting a command for controlling the GE 17. By writing a command code to this register, execution of each command is started. As will be described in detail later, as commands for controlling the GE 17, a command “NOP (no operation)”, a command “Affine (vector affine transformation)”, a command “Pproj (perspective projection transformation)”, a command “View ( Viewport conversion), command “Cull (vertex coordinate setting and culling)”, command “Trans (vector orthogonal transformation)”, command “Dot (vector dot product)”, command “Bright-P” (polygon brightness calculation), Command “Ccal (polygon vertex color calculation)”, command “APV (vector affine transformation / perspective projection transformation / viewport transformation)”, command “CWD (vertex coordinate setting and culling / perspective collect / depth calculation)”, command “TDBP (Vector Orthogonal Transform / Vector Product / polygon brightness calculation), command “TD (vector orthogonal transformation / vector inner product)”, command “MatrixMulti (matrix product)”, and command “Sqrt (square root calculation)”, each having a 5-bit command code Is assigned.

  The register “GECommand” includes a field for storing a 5-bit command code, a 1-bit “Invalid Structure Remove (unnecessary polygon structure instance deletion control)” field, and a 1-bit “Interrupt Enable (interrupt control)” field.

  When the field “InvalidStructureRemove” is “0”, it indicates that the polygon structure instance determined by culling / clipping is not deleted from the array. When the field is “1”, the polygon structure instance determined by culling / clipping is deleted from the array. Indicates to delete. When the field “Interrupt Enable” is “0”, it indicates that an interrupt request is not generated after the command execution is completed. When the field “Interrupt Enable” is “1”, an interrupt request IRQ (see FIG. 10) is generated after the command execution is completed. Show.

  The register “GEStatus” is an 8-bit register indicating the status of GE17 and the operation result. The register “GEStatus” includes a 1-bit carry flag CY, an overflow flag OV, a sign flag S, a zero division flag ZeroDiv, an interrupt flag Interrupt, and a command executing flag Operating.

  When the carry flag CY is “0”, it indicates that no carry has occurred during command execution. When the carry flag CY is “1”, it means that a carry has occurred once or more during command execution. When the overflow flag OV is “0”, it means that no overflow has occurred during command execution, and “1” means that an overflow has occurred once or more during command execution.

  When the sign flag S is “0”, it indicates that the sign (sign) flag (MSB) of the command execution (final) result is “0”, and when it is “1”, the sign flag of the command execution (final) result (MSB) is “1”. When the zero division flag ZeroDiv is “0”, it means that zero division has not occurred, and when it is “1”, it means that zero division has occurred (command execution is stopped).

  When the interrupt flag Interrupt is “0”, it means that there is no interrupt request, and when it is “1”, it means that an interrupt is being requested. When the command executing flag Operating is “0”, it means that the GE 17 is in the idle state, and when it is “1”, it means that the GE 17 is in the command executing state.

  The register “RepeatCount” specifies the number of times to repeat execution of a SIMD (Single Instruction / Multiple Data) type command. The command is decremented every time the command is executed, and the execution is stopped when an underflow occurs. Therefore, the value actually set in this register is “repetition count−1”. For commands other than SIMD type, “0” is set in this register before the execution of the command is started.

  The register “PolygonCount” indicates the count value of the number of polygons for which command processing has been completed. However, polygons deleted by culling / clipping are not counted. This register is read-only, and the value is cleared to “0” at the start of the command. The register “GESourceAddress” sets a base address of a source operand (an area where an operation target is stored) when executing a command. The address is a physical address of the main RAM 25 area. Values need to be aligned according to the data type to be computed. The value of this register is incremented according to the data type when the SIMD type command is executed.

  The register “GEDestinationAddress” sets the base address of the destination operand (area where the operation result is stored) after the command is executed. The address is a physical address of the main RAM 25 area. The value needs to be aligned according to the data type of the operation result. The value of this register is incremented according to the data type when the SIMD type command is executed.

  The register “GEBaseAddress” sets the base address of the polygon structure instance processed by the GE 17. The address is a physical address of the main RAM 25 area. Since the polygon structure instance needs to be arranged in 16-byte alignment, the lower 4 bits of the address are always regarded as “0000”, and any other value is ignored. The value of this register is incremented in units of 16 bytes when a SIMD type command is executed.

  Next, the format of data processed by the GE 17 will be described.

  [1] Matrix32 array

  The Matrix32 array is a format of input data and output data in a command “MatrixMulti” for obtaining a matrix product.

  FIG. 12A is a diagram showing a configuration of the Matrix32 array, and FIG. 12B is a diagram showing a configuration of elements of the Matrix32 array of FIG. As shown in FIG. 12A, the Matrix32 array is composed of 12 elements D [0] to D [11], and each element D [0] to D [11] is a matrix of 4 rows and 3 columns. Indicates an element (see (Equation 15)). The command “MatrixMulti” is a command for obtaining a matrix product of quaternary square matrices, but the elements in the fourth row are always set to (0, 0, 0, 1) (see (Equation 15)). The elements in the fourth row are not included in either input data or output data. Each element D [0] to D [11] of the Matrix32 array is stored in the memory MEM in order from the element D [0] in the first row and first column.

  As shown in FIG. 12B, each element of the Matrix32 array is represented by a signed 32-bit fixed point number. In the output data of the command “MatrixMulti”, all the elements are 32-bit fixed-point numbers. However, in the conversion matrix used in the commands “Affine” and “Trans” described later, the first to third rows The matrix elements in the first column to the third column are 16-bit fixed point numbers. The conversion from the 32-bit fixed-point number to the 16-bit fixed-point number is performed by the CPU 5.

  [2] Vector10 structure

  The Vector 10 structure is a format of input data used in commands “Affine” and “Trans”. Each element of the vertex coordinate array and the unit normal vector array in the local coordinate system is expressed in the form of a Vector10 structure.

  FIG. 13A is a diagram showing the configuration of the Vector10 structure, FIG. 13B is an explanatory diagram of members of the Vector10 structure, and FIG. 13C is the members “X” to “Z” of the Vector10 structure. FIG. As illustrated in FIG. 13A, the Vector10 structure includes members “X”, “Y”, “Z”, and “Scale”. As shown in FIG. 13C, each of the members “X”, “Y”, and “Z” indicating the vector components is represented by a 10-bit signed fixed-point number. Each component of the vertex coordinate array and the normal vector array of the local coordinate system is basically normalized to a range of about −1.0 to about +1.0. However, as shown in FIG. 13B, it is possible to make the value expanded up to a range of about −8.0 to about +8.0 depending on the value of the member “Scale”.

  [3] Vector16 structure

  The Vector16 structure is a format of output data of the command “Pproj”, and is a format of input data and output data of the command “View”. Each element of the vertex coordinate array in the perspective coordinate system or the screen coordinate system is expressed in the form of a Vector16 structure. However, the vector 16 component value of the view coordinate system is included in the Vector 16 structure for culling and polygon parameter calculation.

  14A is a diagram showing the configuration of the Vector16 structure, FIG. 14B is an explanatory diagram of members of the Vector16 structure, and FIG. 14C is the configuration of the member “Z” of the Vector16 structure. FIG. 14D shows the configuration of members “X” and “Y” of the Vector16 structure. As shown in FIG. 14A, the Vector16 structure includes members “Clipping”, “X”, “Y”, and “Z”. As shown in FIG. 14C, the member “Z” indicating the Z component of the vector is represented by a 31-bit unsigned fixed-point number. Further, as shown in FIG. 14D, members “X” and “Y” indicating the XY component of the vector are represented by 16-bit signed fixed-point numbers.

  As shown in FIG. 14B, the value of the member “Clipping” is set such that the vertex coordinates indicated by the vector in the view volume clipping performed by the commands “Pproj” and “View” (or the compound command “APV”) are the view volume. Is set to “1” when it is determined that it is outside the range.

  [4] Vector32 structure

  The Vector32 structure has a format of output data of the commands “Affine” and “Trans”, and a format of input data of the command “Pproj”. Each element of the vertex coordinate array and the normal vector array in the view coordinate system is expressed in the form of a Vector32 structure.

  FIG. 15A is a diagram illustrating a configuration of the Vector32 structure, and FIG. 15B is an explanatory diagram of members of the Vector32 structure. Referring to FIG. 15A, the Vector 32 structure includes members “X”, “Y”, and “Z”. As shown in FIG. 15B, members “X”, “Y”, and “Z” indicate the X component, Y component, and Z component of the vector, respectively. Each of the members “X”, “Y”, and “Z” is represented by the same 32-bit signed fixed-point number as in FIG.

  [5] Dot structure

  The Dot structure is a format of output data of the commands “Dot” and “TD”, and is a format of input data of the command “Ccalc”. An inner product of the unit normal vector and the light source vector and an inner product of the unit normal vector and the line-of-sight vector are stored in the Dot structure.

  FIG. 16A is a diagram illustrating a configuration of a Dot structure, and FIG. 16B is an explanatory diagram of members of the Dot structure. Referring to FIG. 16A, the Dot structure includes members “Dvalue”, “S2B”, and “S1”. Referring to FIG. 16B, the member “Dvalue” represents the absolute value (0 to 1.0) of the inner product operation result of the normal vector and the light source vector as a 6-bit unsigned fixed-point number. 1LSB is subtracted from this and expressed as a 5-bit unsigned fixed-point number. However, when the result of the subtraction is negative, it is saturated to “0”.

  The member “S2B” is an inverted value of the sign of the inner product of the normal vector and the line-of-sight vector. The member “S1” is a sign of the inner product of the normal vector and the light source vector.

  Next, polygon data handled by the GE 17 will be described. In order to display a polygon on the screen, one polygon structure instance is required for each polygon. Further, in order to display a texture mapping mode polygon, a texture attribute structure instance is required.

  The format of the polygon structure is greatly different between the texture mapping mode and the Gouraud shading mode. In each mode, the format differs between the input data for GE 17 and the input data for RPU 9. However, in any configuration, the size of the polygon structure is fixed to 128 bits (16 bytes).

  In the polygon structure in the input format to the GE 17, the value of the member “Depth” is a signed offset value (that is, a depth initial value) added to the depth value. When it is desired to control the drawing priority of polygons, such as when a texture mapping mode polygon is raised, a value other than “0” is set as an offset value.

  In the polygon structure of the input format to the RPU 9, the member “Depth” indicates the depth (rendering priority) of the polygon expressed by a floating point number (mantissa part 8 bits + exponent part 4 bits).

  FIG. 17 is a diagram illustrating a configuration of a polygon structure (GE input format) in the texture mapping mode. FIG. 18 is an explanatory diagram of members of a polygon structure (GE input format) in texture mapping mode.

  Referring to FIG. 17, in the texture mapping mode, the polygon structure in the input format to GE 17 includes members “Type”, “Face”, “Via”, “Vib”, “Vic”, “Bw”, “Light”. ”,“ Tsegment ”,“ Tattribute ”,“ Map ”,“ Cw ”,“ Depth ”,“ Viewport ”, and“ Filter ”. The contents of these members are as shown in FIG.

  FIG. 19 is a diagram showing a configuration of a polygon structure (GE input format) in the Gouraud shading mode. FIG. 20 is an explanatory diagram of members of a polygon structure (GE input format) in the Gouraud shading mode.

  Referring to FIG. 19, in the Gouraud shading mode, the polygon structure of the input format to GE 17 has members “Type”, “Face”, “Via”, “Vib”, “Vic”, “Ac”, “Ac”. It consists of “Bc”, “Cc”, “Depth”, “Viewport” and “Nalpha”. The contents of these members are as shown in FIG.

  Next, each command for controlling the GE 17 will be described in detail.

  [1] Command “MatrixMulti”

  The command “MatrixMulti” is a command for obtaining a matrix product of quaternary square matrices. However, the matrix assumes an affine transformation of a three-dimensional orthogonal coordinate system vector, the matrix elements in the fourth row are always considered to be (0, 0, 0, 1), and the matrix elements in the fourth row are It is not included in the input matrix and output matrix.

  This command is mainly used to synthesize a plurality of coordinate system transformation matrices. For example, by generating a matrix product of a transformation matrix from the local coordinate system to the world coordinate system and a transformation matrix from the world coordinate system to the view coordinate system, a transformation matrix from the local coordinate system to the view coordinates is generated. Is possible.

  By executing this command once, a matrix product operation is performed once. Multiple matrix product operations cannot be performed with a single command execution. The formula of matrix operation executed by this command is as follows.

  In (Expression 15), the array D is a Matrix32 array for storing the matrix elements of the operation results, the matrix elements GR0 to GR11 of one input matrix are the values of the registers GR0 to GR11, respectively, and the array S is the other input matrix This is a Matrix32 array that stores the matrix elements. (Formula 15) is expanded as follows.

  In (Expression 15) and (Expression 16), the array S is arranged on the main RAM 25 with the value indicated by the register “GESourceAddress” as a base address. Each element S [0] to S [11] of the array S is a 32-bit signed fixed point format. Each element S [0] to S [11] needs to be arranged in a word (4 byte) alignment. Here, 4-byte (32-bit) data is referred to as a word, and 2-byte (8-bit) data is referred to as a halfword in accordance with the number of bits of operation data of the CPU 5.

  The values of the data (matrix elements) GR0 to GR11 are each in a 32-bit signed fixed point format.

  The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address. Each element D [0] to D [11] of the array D is a 32-bit signed fixed point format.

  When this command is executed, the register “RepeatCount” is set to “0”. The base address of the array S is set as the physical address of the main RAM 25 in the register “GESourceAddress”. Since each element of the array S needs to be arranged in word alignment, “00” is set in the lower 2 bits. In the register “GEDestinationAddress”, the base address of the array D is set as the physical address of the main RAM 25. Since each element of the array D is stored in word alignment, “00” is set in the lower 2 bits.

  The registers GR12 to GR15 are used as work areas.

  [2] Command “Affine”

  The command “Affine” is a command for affine transformation of a three-dimensional vector using a quartic square matrix. In this conversion, enlargement / reduction, rotation, and translation can be performed at a time. This command is mainly used to convert the vertex coordinate array and normal vector array of the local coordinate system to another orthogonal coordinate system. This command is a SIMD type command, and a plurality of vectors can be continuously converted for one conversion matrix. The formula of matrix operation executed by this command is as follows.

  The array D is a Vector32 structure array that stores vectors after affine transformation. The matrix elements GR0L to GR2L, GR4L to GR6L, GR8L to GR10L are values of lower 16 bits of the registers GR0 to GR2, GR4 to GR6, GR8 to GR10, respectively. The matrix elements GR3, GR7, GR11 are the values of the registers GR3, GR7, GR11, respectively. The array S is a Vector10 structure array that stores vectors before affine transformation. Note that the suffix after the period “.” In the arrays D and S indicates the member name of the structure (see FIGS. 13 and 15). Also, n = 0 to N (number of elements in the array) -1. (Expression 17) is expanded as follows.

  In (Expression 17) and (Expression 18), the array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element of the array S needs to be arranged in word alignment. Data (matrix elements) GR0L to GR2L, GR4L to GR6L, and GR8L to GR10L are values set in the lower 16 bits of registers GR0 to GR2, GR4 to GR6, and GR8 to GR10. Each value is a 16-bit signed fixed point format. However, the values of the 16-bit signed fixed-point format are converted to the 32-bit signed fixed-point format before (Equation 17) and (Equation 18) are performed by the type conversion units 108a and 108b described later. . Data (matrix elements) GR3, GR7, and GR11 are values set in the registers GR3, GR7, and GR11. Each value is a 32-bit signed fixed point format. The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address.

  When this command is executed, the number of elements of the array S−1 (= N−1) is set in the register “RepeatCount”. Further, the base address of the array S is set as the physical address of the main RAM 25 in the register “GESourceAddress”. Since each element of the array S needs to be arranged in word alignment, “00” is set in the lower 2 bits. In the register “GEDestinationAddress”, the base address of the array D is set as the physical address of the main RAM 25. Since each element of the array D is stored in word alignment, “00” is set in the lower 2 bits.

  Note that the register “RepeatCount”, the register “GESourceAddress”, and the register “GEDestinationAddress” are registers whose values change as the command is executed.

  [3] Command “Pproj”

  The command “Pproj” is a command for perspectively projecting a three-dimensional vector into a two-dimensional space and performing processing of a near clip and a far clip in view volume clipping. This command is used to project the three-dimensional coordinates given in the view coordinate system onto the perspective coordinate system. In addition, this command sets “1” to the member “Clipping” of the Vector16 structure instance to be output when the value of the Z component of the input vector is outside the predetermined range (see FIG. 14). This command is a SIMD type command, and a plurality of vectors can be converted continuously. The following calculation is executed by this command.

In (Equation 19), the array D is a Vector16 structure array that stores the converted vector, the data d is the value of the register “Distance” (distance from the viewpoint to the projection plane), and the data Z _N is , The value of the register “ZNear” (near clip value), the data Z _F is the value of the register “ZFar” (far clip value), and the array S is a Vector32 structure array that stores vectors before conversion. is there. Note that the suffix after the period “.” In the arrays D and S indicates the member name of the structure (see FIGS. 14 and 15).

  The array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element needs to be arranged in word alignment. A distance from the viewpoint to the projection plane is set in the register “Distance”. The set value is a 16-bit unsigned integer. In the register “RepeatCount”, the number of elements of the array S−1 (= N−1) is set.

The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address. The value of Z components of the input vector is less than the near clip value _{Z N,} or if more far clipping value _{Z F,} "1" is set in the member "Clipping" of Vector16 structure instance (see Figure 14).

  The base address of the array S is set as the physical address of the main RAM in the register “GESouiceAddress”. Since each element of the array S needs to be arranged in word alignment, “00” is set in the lower 2 bits. The register “GEDestinationAddress” sets the base address of the array D with the physical address of the main RAM 25. Since each element of the array D is stored in word alignment, “00” is set in the lower 2 bits.

  The register GR15 is used as a work area. The register “RepeatCount”, the register “GESourceAddress”, and the register “GEDestinationAddress” are registers whose values change as the command is executed.

  [4] Command “View”

  The command “View” is a command for performing a conversion process for adding an offset to a vector in the two-dimensional orthogonal coordinate system and performing a clipping process of the screen area in the view volume clipping. This command is used to convert the XY coordinate in the perspective coordinate system to the XY coordinate in the screen coordinate system. In addition, this command is a member of a Vector16 structure instance that is output when the X component of the conversion result exceeds the range of 0-2047, or when the Y component exceeds the range of 0-1023. “1” is set in “Clipping” (see FIG. 14). This command is a SIMD type command, and a plurality of vectors can be converted continuously. The operations executed by this command are as follows.

  In (Equation 20), the array D is a Vector16 structure array that stores the vector after conversion, the array S is a Vector16 structure array that stores the vector before conversion, and the data offx is stored in the register “ViewportOffsetX”. The data offy is the value of the register “ViewportOffsetY” (Y component offset). Note that the subscript after the period “.” In the arrays D and S indicates the member name of the structure (see FIG. 14).

  The array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element needs to be arranged in word alignment.

  The register “ViewportOffsetX” sets an offset value to be added to the X component. The set value is a 12-bit unsigned fixed-point format. The register “ViewportOffsetY” sets an offset value to be added to the Y component. The set value is a 12-bit unsigned fixed-point format.

  The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address. As a result of the operation, when the X component exceeds the range of 0 to 2047 or the Y component exceeds the range of 0 to 1023, “1” is set to the member “Clipping” of the Vector16 structure instance. .

  The register “GESourceAddress” sets the base address of the array S as the physical address of the main RAM 25. Since each element of the array S needs to be arranged in word alignment, “00” is set in the lower 2 bits. The register “GEDestinationAddress” sets the base address of the array D as the physical address of the main RAM 25. Since each element of the array is stored in word alignment, “00” is set in the lower 2 bits.

  The registers GR13 to GR15 are used as work areas. The register “RepeatCount”, the register “GESourceAddress”, and the register “GEDestinationAddress” are registers whose values change as the command is executed.

  [5] Command “Trans”

  The command “Trans” is a command for orthogonally transforming a three-dimensional vector with a cubic square matrix. In this conversion, enlargement / reduction and rotation can be performed. This command is mainly used to convert the vertex normal vector / polygon normal vector from the local coordinate system to another orthogonal coordinate system. It is also used when converting a light source vector defined in the world coordinate system into a view coordinate system. This command is a SIMD type command, and a plurality of vectors can be continuously converted for one conversion matrix. The matrix operation executed by this command is as follows.

  In (Expression 21), the array D is a Vector16 structure array that stores the converted vector, and the matrix elements GR0L to GR8L are the lower 16 bits of the registers GR0 to GR8. The array S is a Vector10 structure array that stores vectors before conversion. The member “Scale” included in the Vector10 structure of the input vector is ignored in the operation of this command (see FIG. 13). That is, regardless of the value of the member “Scale”, the magnification is always considered to be 1. The subscripts after the period “.” In the arrays D and S indicate the member names of the structures (see FIGS. 13 and 14). When the matrix operation of (Expression 21) is expanded, it is expressed by the following expression.

  In (Expression 21) and (Expression 22), the array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Data (matrix elements) GR0L to GR8L are values set in the lower 16 bits of the registers GR0 to GR8. The set value is a 16-bit signed fixed-point number. The register “RepeaCount” sets the number of elements of the array S−1 (= N−1). The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address.

  The register “GESourceAddress” sets the base address of the array S with the physical address of the main RAM 25. Since each element of the array S needs to be arranged in word alignment, “00” is set in the lower 2 bits. The register “GEDestinationAddress” sets the base address of the array D with the physical address of the main RAM 25. Since each element of the array D is stored in word alignment, “00” is set in the lower 2 bits.

  Note that the register “RepeatCount”, the register “GESourceAddress”, and the register “GEDestinationAddress” are registers whose values change as the command is executed.

  [6] Command “Dot”

  The command “Dot” is a command for obtaining an inner product of three-dimensional vectors. This command is used to obtain the inner product of the normal vector N and the light source vector L in order to obtain the diffused light brightness of the vertex / polygon. This command also calculates the inner product of the vector N and the line-of-sight vector V (0, 0, −1) at the same time in order to calculate the diffused light brightness of the polygon (surface). This command is a SIMD type command, and it is possible to continuously perform an inner product operation with several vectors N (vertex / polygon normal vectors) for one vector L (light source vector). The following calculation is performed by this command.

  In (Expression 23), the array D is a Dot structure array that stores the inner product of the vectors, the data Vx is the value of the register “LightVX” (the X component of the vector L), and the data Vy is the register “LightVY” ”(The Y component of the vector L), the data Vz is the value of the register“ LightVZ ”(the Z component of the vector L), and the array S is a Vector16 structure array that stores the vector N. Note that the suffix after the period “.” In the arrays D and S indicates the member name of the structure (see FIGS. 14 and 16).

  The array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element must be arranged in halfword alignment. The register “LightVX” sets the X component of the vector L. The set value is a 16-bit signed fixed-point number. The register “LightVY” sets the Y component of the vector L. The set value is a 16-bit signed fixed-point number. The register “LightVZ” sets the Z component of the vector L. The set value is a 16-bit signed fixed-point number. The array D is stored in the main RAM 25 with the value indicated by the register “GEDestinationAddress” as a base address.

  The register “RepeatCount” sets the number of elements of the array S−1 (= N−1). The register “GESourceAddress” sets the base address of the array S as the physical address of the main RAM 25. Since each element of the array S needs to be arranged in halfword alignment, “0” is set in the lower 1 bit. The register “GEDestinationAddress” sets the base address of the array D with the physical address of the main RAM 25.

  Note that the register “RepeatCount”, the register “GESourceAddress”, and the register “GEDestinationAddress” are registers whose values change as the command is executed.

  [7] Command “Bright-P”

  The command “Bright-P” is a command for calculating the polygon (surface) brightness by adding the diffused light brightness of the polygon (surface) and the ambient light brightness. When the polygon is a single-sided polygon, if the inner product of the light source vector L and the normal vector N of the polygon (surface) is 0 or more, the absolute value of the inner product is the diffused light brightness of the polygon (surface), and the inner product is less than 0. If there is, the diffused light brightness is set to “0”. When the polygon is a double-sided polygon, if the sign of the inner product of the light source vector L and the normal vector N matches the sign of the inner product of the line-of-sight vector V and the normal vector N, the absolute value of the inner product is determined as a polygon. If the signs do not match, the diffuse light brightness is set to “0”. When the addition result exceeds the maximum value in the addition of the diffuse light brightness and the ambient light brightness, the result is saturated to the maximum value. This command is a SIMD type command, and can process a plurality of polygons (surfaces) continuously. The following calculation is performed by this command.

  In (Equation 24) and (Equation 25), the array P is a polygon structure array (see FIG. 17), and the array S is an inner product of a polygon normal vector and a light source vector, and a polygon normal vector and a line-of-sight vector. This is a Dot structure array that stores the inner product of (see FIG. 16). The data “ambient” is the value (environment lightness) of the register “Ambient”. The data “diffuse” is diffused lightness. The subscript after the period “.” In the array S indicates the member name of the structure.

  The array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element must be arranged in byte alignment. The array P needs to be arranged on the main RAM 25 with the value indicated by the register “GEBaseaddress” as a base address. Each element of the array needs to be arranged in 16-byte alignment.

  The register “Ambient” sets the ambient lightness. The set value is a 5-bit unsigned fixed-point format. The register “RepeatCount” sets the number of elements of the array P−1 (= N−1). The register “GESourceAddress” sets the base address of the array S with the physical address of the main RAM 25. Since each element of the array needs to be arranged in halfword alignment, “0” is set in the lower 1 bit. The register “GEBaseaddress” sets the base address of the array P with the physical address of the main RAM 25. Since each element of the array P needs to be arranged in a 16-byte alignment, the lower 4 bits have no register entity.

  The value of the member “Light” (P [n] .Light (n = 0 to N−1)) of the polygon structure array P having N instances is rewritten by executing this command.

  [8] Command “Ccalc”

  The command “Ccalc” is a command for calculating the vertex lightness by adding the diffuse light brightness of the vertex and the ambient light brightness, and calculating the vertex color after lighting based on the calculated vertex lightness and the original vertex color. is there. This command is used only for polygons in the Gouraud shading mode, and the vertex colors after lighting are set in the members “Ac”, “Bc”, and “Cc” of the polygon structure instance (see FIG. 19). The following calculation is performed by this command.

  In (Equation 26) and (Equation 27), the array P is a polygon structure array (see FIG. 19), and the array S is the inner product of the vertex normal vector and the light source vector, and the vertex normal vector and the line of sight. It is a Dot structure array that stores the inner product with the vector (see FIG. 16). The data “ambient” is the value (environment lightness) of the register “Ambient”.

  The array S [m] (m = 0 to M−1) is a Dot structure array that stores M sets of inner products of vertex normal vectors and light source vectors and inner products of vertex normal vectors and line-of-sight vectors. . This array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. The array P [n] (n = 0 to N−1) is a polygon structure array having N instances. This array P is arranged on the main RAM 25 using the value indicated by the register “GEBaseaddress” as a base address. Each element of the array P needs to be arranged in 16-byte alignment.

  The register “Ambient” sets the ambient lightness. The set value is a 5-bit unsigned fixed-point format. The register “RepeatCount” sets the number of elements of the array P−1 (= N−1). The register “GESourceAddress” sets the base address of the array S with the physical address of the main RAM 25. Since each element of the array needs to be arranged in half word alignment, “0” is set in the lower 1 bit. The register “GEBaseaddress” sets the base address of the array P with the physical address of the main RAM 25. Since each element of the array needs to be arranged in 16-byte alignment, the lower 4 bits have no register entity.

  Note that the suffix after the period “.” In the arrays P and S indicates the member name of the structure (see FIGS. 16 and 19). In addition, the array P [n]. Ac, P [n]. Bc and P [n]. Subscripts R, G, and B attached to Cc indicate an R value (color red component), a G value (color green component), and a B value (color blue component), respectively.

  [9] Command “Cull”

  The command “Cull” is a command for setting the vertex coordinates of the polygon and processing for back surface culling and view volume clipping. This command first obtains each vertex coordinate stored in the polygon structure instance by referring to the Vector 16 structure array storing the vertex coordinates of the screen coordinate system. Determine the front and back of the polygon using the obtained vertex coordinates, and if the polygon is a single-sided polygon and is displayed on the back side, set the maximum value for all the vertex coordinates of the polygon so that it is not displayed on the screen, or the polygon Remove structure instance from polygon structure array (backside culling).

  If the value of the member “Clipping” is “1” in any one of the Vector16 structure instances indicating each vertex coordinate, the maximum value is set for all the vertex coordinates of the polygon as in the above case. The polygon structure instance is removed from the polygon structure array (view volume clipping). This command performs the following operations:

  In (Equation 28) to (Equation 31), the array P is a polygon structure array, and the array S is a Vector16 structure array that stores vertex coordinates of the screen coordinate system.

  The array S [m] (m = 0 to M−1) is a Vector16 structure array that stores the vertex coordinates of the M sets of screen coordinate systems. This array S is arranged on the main RAM 25 using the value indicated by the register “GESourceAddress” as a base address. Each element of the array S needs to be arranged in word alignment. The array P [n] (n = 0 to N−1) is a polygon structure array having N instances. This array P is arranged on the main RAM 25 using the value indicated by the register “GEBaseaddress” as a base address. Each element of the array P needs to be arranged in 16-byte alignment. Note that the suffix after the period “.” In the arrays P and S indicates the member name of the structure (see FIGS. 14, 17, and 19).

  The register “RepeatCount” sets the number of elements of the array P−1 (= N−1). The register “GESourceAddress” sets the base address of the array S with the physical address of the main RAM 25. Since each element of the array P needs to be arranged in halfword alignment, “0” is set in the lower 1 bit. The register “GEBaseaddress” sets the base address of the array P with the physical address of the main RAM 25. Since each element of the array S needs to be arranged in 16-byte alignment, the lower 4 bits have no register entity.

  The members “Via”, “Vib”, “Vic”, and “Face” of each polygon structure instance execute this command, so that the members “Ax”, “Ay”, “Bx”, “By”, “ Rewritten as “Cx” and “Cy”. When the value of “InvalidStructureRemove” of the register “GECommand” at the time of issuing the command is “1”, the polygon structure instance determined to be hidden by the back surface culling / view volume clipping is deleted from the array, and the subsequent polygon structure instance Rearranged to the front. The register “PolygonCount” indicates the total number of instances excluding the polygon structure instances deleted from the polygon structure array as a result of back surface culling / view volume clipping, that is, the number of effective polygons.

  [10] Command “Sqrt”

  The command “Sqrt” is a command for calculating a square root. This command is used for purposes such as calculating the size of a vector (scalar amount) when obtaining a unit vector. The following calculation is performed by this command.

  In (Expression 32), the data GR0 is the value of the register GR0. The register GR0 sets an input value. The value is expressed as a 32-bit unsigned fixed-point number. The register GR0 [31:16] is treated as an integer field, and the register GR0 [15: 0] is treated as a decimal field. A 32-bit signed fixed-point number can also be used as input data as long as the value is not negative.

  The data (calculated square root value) GR1L is stored in the lower 16 bits of the register GR1. The value is expressed as a 16-bit unsigned fixed-point number. The register GR0 [15: 8] stores an integer field, and the register GR0 [7: 0] stores a decimal field.

  [11] Command “APV”

  The command “APV” is a command for executing the command “Affine” (affine transformation), the command “PPproj” (perspective projection transformation), and the command “View” (viewport transformation) with one command. However, data in the middle of calculation, that is, output data of the command “Affine” and the command “PPproj” is not output to the main RAM 25.

  The calculation by the command “APV” is the same as the command “Affine”, the command “PPproj”, and the command “View”, and thus description thereof is omitted. The input data is the same as in the case of the command “Affine”, and the output data is the same as in the case of the command “View”.

  [12] Command “CWD”

  The command “CWD” is a command for performing perspective correction parameter calculation and depth calculation processing following the processing of the command “Cull” (vertex coordinate setting and culling). With this command, the following calculation is performed following the processing of the command “Cull”.

  In (Expression 34), data M is a mantissa field (8 bits) of a 12-bit floating point number “depth”, and data E is an exponent field (4 bits) of a 12-bit floating point number “depth”. The data DEB is a value (0 to 7) of the register “DepthBias”. The rounding mode of the mantissa field is truncation. The 12-bit value “depth” obtained here is stored in the array P [n]. The depth initial value stored in the depth is added to the array P [n]. Write back to Depth. That is, it is as follows.

  (Expression 35), the array P [n]. Depth is an initial depth value, array P [n]. Depth ′ is a depth value after the calculation.

  The input data in this command is the value of the register “DepthBias” in addition to the input data of the command “Cull”. The value of the register “DepthBias” is a bias value (getter) of the exponent field in floating point format conversion for depth calculation.

  This command also rewrites the values of the members “P [n] .Wb” and “P [n] .Wc” (n = 0 to N−1) of the polygon structure array. These are parameters for the perspective collection of the polygon structure array P having N polygon structure instances. These values are written only for polygon structure instances in texture mapping mode.

  Note that the suffix after the period “.” In the arrays P and S indicates the member name of the structure.

  [13] Command “TDBP”

  The command “TDBP” is a command for collectively performing lighting processing for polygons in the texture mapping mode. The command “Trans” (vector orthogonal transformation), the command “Dot” (vector dot product), and the command “Bright-P” (polygon brightness calculation) are executed with one command. However, data in the middle of calculation, that is, output data of the commands “Trans” and “Dot” is not output to the main RAM 25.

  The calculation by the command “TDBP” is the same as the command “Trans”, the command “Dot”, and the command “Bright-P”, and the description thereof will be omitted. The input data is the same as that of the command “Trans”, and the output data is the same as that of the command “Bright-P”.

  [14] Command “TD”

  The command “TD” is a command for collectively performing lighting preprocessing for polygons in the Gouraud shading mode. The command “Trans” (vector orthogonal transformation) and the command “Dot” (vector dot product) are executed with one command. However, data in the middle of calculation, that is, output data of the command “Trans” is not output to the main RAM 25. After executing this command, the command “Ccalc” is executed to calculate the polygon vertex color after the lighting processing.

  The calculation by the command “TD” is the same as the command “Trans” and the command “Dot”, and the description thereof will be omitted. The input data is the same as in the case of the command “Trans”, and the output data is the same as in the case of the command “Dot”.

  FIG. 21 is a block diagram showing an internal configuration of the execution unit 100 of FIG. In addition, the number in () attached | subjected after the name of each structure in a figure shows the bit number of the structure.

  Referring to FIG. 21, the execution unit 100 includes a division unit 102 (32 bits / 32 bits), a product-sum operation unit 104 (16 bits × 16 bits + 65 bits), an additional operation unit 106, type conversion units 108a and 108b, Multiplexers (MUX) 110a and 110b, multiplexers (MUX) 112a and 112b, Vector 10 format conversion unit 114, and buses 150a, 150b and 150c are included.

  The division unit 102 includes a dividend register 116, a divisor register 118, a 32-bit divider 120, and a quotient register 122. The product-sum operation unit 104 includes a multiplicand adjustment unit 124, a multiplicand register 126, a multiplier adjustment unit 128, a multiplier register 130, a 16-bit multiplier 132, a product adjustment unit 134, a product register 136, a shifter 138 with bit extension, a register 140, and a bit. It includes an expansion unit 142, a multiplexer (MUX) 144, a 65-bit adder 146, and a SUM register 148.

  The arithmetic units 102, 104, and 106 and the input / output data are connected by a bus 150a, a bus 150b, and a bus 150c. Each of the bus 150a, the bus 150b, and the bus 150c transfers 32-bit data. Here, the input / output data includes input data RGI from the I / O register set 300, output data RGO to the I / O register set 300, read data MRE from the main RAM 25, and write data MWR to the main RAM 25. Point to.

  As data sent to the bus 150a and the bus 150b, the data RGI stored in the I / O register set 300, the read data MRE from the main RAM 25, and the read data MRE from the main RAM 25 are converted by the Vector 10 format conversion unit 114. There are four types of data VCT and data BUC output from the bus 150c. This point will be described in detail.

  The MUX 112a receives the data REI from the I / O register set 300, the data MRE from the main RAM 25, and the data VCT from the Vector10 format conversion unit 114, and selects one of them according to the control signal from the control unit 200. Output to the MUX 110a.

  The MUX 110a receives the selection data from the MUX 112a and the data BUC from the bus 150c, selects one of them according to the control signal from the control unit 200, and outputs it to the type conversion unit 108a. The type conversion unit 108a performs type conversion, which will be described in detail later, on the selection data received from the MUX 110a in accordance with the control signal from the control unit 200, and sends the result data to the bus 150a.

  On the other hand, the MUX 112b receives the data REI from the I / O register set 300, the data MRE from the main RAM 25, and the data VCT from the Vector10 format conversion unit 114, and in accordance with a control signal from the control unit 200, one of them is received. Select and output to MUX 110b.

  The MUX 110b receives the selection data from the MUX 112b and the data BUC from the bus 150c, selects one of them according to the control signal from the control unit 200, and outputs it to the type conversion unit 108b. The type conversion unit 108b performs type conversion described in detail later on the selection data received from the MUX 110b in accordance with the control signal from the control unit 200, and sends the result data to the bus 150b.

  Details of the Vector 10 format conversion unit 114 will be described. The Vector 10 format conversion unit 114 extracts members X, Y, and Z from 32-bit Vector 10 format data (see FIG. 13) input as read data MRE from the main RAM 25, and in accordance with a control signal from the control unit 200. , X, Y, and Z are output as data VCT to the MUXs 112a and 112b. However, before outputting each member X, Y, and Z, the Vector 10 format conversion unit 114 performs an expansion conversion from 1 to 8 times on each member X, Y, and Z according to the value of the member Scale. Apply. Therefore, the output data VCT is data after enlargement conversion.

  Details of the type conversion unit 108a will be described. Since the type conversion unit 108b performs the same type conversion as the type conversion unit 108a, the description thereof is omitted.

  The type conversion unit 108a performs any one of the following type conversions [1] to [13] in accordance with a control signal from the control unit 200. In the description of type conversions [1] to [13], “IN” is an input value, “OUT” is an output value, symbol “=” is assigned, “n ()” is n bits of (), and symbol “{ ,} ”Represents bit concatenation. For example, “4 (0b0)” is “0” for 4 bits, that is, “0b0000”.

Type conversion [1] is zero extension from the lower 8 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {24 (0b0), IN [7: 0]}

Type conversion [2] is sign extension from the lower 8 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {24 (IN [7]), IN [7: 0]}

Type conversion [3] is zero extension from lower 16 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {16 (0b0), IN [15: 0]}

Type conversion [4] is sign extension from lower 16 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {16 (IN [15]), IN [15: 0]}

In the type conversion [5], 1-bit “0” is concatenated to the LSB side of the lower 16 bits and zero-extended to 32 bits, and is represented by the following equation.
OUT [31: 0] = {15 (0b0), IN [15: 0], 0b0}

In the type conversion [6], 1-bit “0” is concatenated to the lower 16-bit LSB side and sign-extended to 32 bits, and is represented by the following equation.
OUT [31: 0] = {15 (IN [15]), IN [15: 0], 0b0}

The type conversion [7] is to add 16 bits of MSB (sign bit) in 32 bits to the lower 16 bits, and is represented by the following equation.
OUT [31: 0] = {16 (IN [31]), IN [15: 0]}

In the type conversion [8], 1-bit “0” is concatenated to the upper 16-bit LSB side and zero-extended to 32 bits, and is represented by the following equation.
OUT [31: 0] = {15 (0b0), IN [31:16], 0b0}

In the type conversion [9], 1-bit “0” is concatenated to the LSB side of the upper 16 bits and the sign is extended to 32 bits, and is represented by the following equation.
OUT [31: 0] = {15 (IN [31]), IN [31:16], 0b0}

Type conversion [10] is zero extension from upper 16 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {16 (0b0), IN [31:16]}

Type conversion [11] is a sign extension from upper 16 bits to 32 bits, and is represented by the following equation.
OUT [31: 0] = {16 (IN [31]), IN [31:16]}

The type conversion [12] connects 16 bits “0” to the LSB side of the upper 16 bits, and is represented by the following equation.
OUT [31: 0] = {IN [31:16]), 16 (0b0)}

Type conversion [13] does not perform type conversion (remaining 32 bits), and is represented by the following equation.
OUT [31: 0] = IN [31: 0]

  Now, the division unit 102 divides the 32-bit dividend by the 32-bit divisor and outputs a 32-bit quotient. The specific configuration is as follows.

  The dividend register 116 takes in the 32-bit data sent to the bus 150a and holds it as a dividend which is an input value for division. The divisor register 118 takes in the 32-bit data sent to the bus 150b and holds it as a divisor that is an input value for division. The 32-bit divider 120 divides the dividend held in the dividend register 116 by the divisor held in the divisor register 118 and outputs a 32-bit quotient. However, the remainder is not output. In the present embodiment, the divider 120 always performs unsigned division, but it is also possible to perform signed division. The quotient register 122 takes in the quotient output from the 32-bit divider 120 and outputs it to the additional arithmetic unit 106. The value held by the dividend register 116 is also output to the additional arithmetic unit 106.

  A specific configuration of the product-sum operation unit 104 is as follows. The multiplicand adjustment unit 124 performs a process such as logical inversion (bit inversion), arithmetic inversion, and / or look-ahead carry addition of the multiplicand according to the control signal from the control unit 200 and the sign of the multiplicand received from the bus 150a. . The multiplicand register 126 holds the multiplicand (16 bits) output from the multiplicand adjustment unit 124.

  Here, arithmetic inversion refers to calculating a value obtained by inverting the sign of an input value by obtaining a 2's complement.

  The multiplier adjustment unit 128 performs processing such as logical inversion (bit inversion) of multiplier, arithmetic inversion, and / or addition of look-ahead carry according to the control signal from the control unit 200 and the sign of the multiplier received from the bus 150b. . The multiplier register 130 holds the multiplier (16 bits) output from the multiplier adjustment unit 128.

  The 16-bit multiplier 132 multiplies the 16-bit multiplicand held in the multiplicand register 126 by the 16-bit multiplier held in the multiplier register 130, and outputs a 32-bit product. In principle, the multiplier 132 performs only unsigned multiplication. However, the multiplier 132 performs multiplication even if one or both of the multiplier and the multiplicand are signed values through the processing by the multiplicand adjustment unit 124, the multiplier adjustment unit 128, and the product adjustment unit 134. Can do.

  The product adjustment unit 134 performs arithmetic inversion of the product output from the multiplier 132 according to the sign of the multiplier and multiplicand. The product register 136 holds the 33-bit product output from the product adjustment unit 134.

  The bit extension shifter 138 performs any one of the following conversions [1] to [5] in accordance with a control signal from the control unit 200. In the conversions [1] to [5], “IN” is an input value, “OUT” is an output value, the symbol “=” is assigned, “n ()” is n bits of (), and the symbol “{,}”. Represents the concatenation of bits.

The conversion [1] is obtained by concatenating 16-bit “0” on the LSB side and sign-extending to 65 bits, and is represented by the following equation.
OUT [64: 0] = {16 (IN [32]), IN [32: 0], 16 (0b0)}

Conversion [2] is a concatenation of 32-bit “0” s on the LSB side and is expressed by the following equation.
OUT [64: 0] = {IN [32: 0], 32 (0b0)}

Conversion [3] takes the upper 31 bits out of 32 bits and sign-extends them to 65 bits, and is expressed by the following equation.
OUT [64: 0] = {33 (IN [32]), IN [32: 1])}

Conversion [4] takes the lower 31 bits out of 32 bits and zero-extends them to 65 bits, and is expressed by the following equation.
OUT [64: 0] = {34 (0b0), IN [30: 0]}

Conversion [5] is for sign extension to 65 bits and is expressed by the following equation.
OUT [64: 0] = {32 (IN [32]), IN [32: 0]}

  On the other hand, the register 140 holds 32-bit data transmitted to the bus 150b. The bit extension unit 142 performs any of the following conversions [1] to [3] according to the control signal from the control unit 200. In the conversions [1] to [3], “IN” is an input value, “OUT” is an output value, the symbol “=” is assigned, “n ()” is n bits of (), and the symbol “{,}”. Represents the concatenation of bits.

Conversion [1] is a sign extension to 65 bits, and is expressed by the following equation.
OUT [64: 0] = {33 (IN [31]), IN [31: 0]}

Conversion [2] takes the lower 31 bits out of 32 bits and sign-extends them to 65 bits, and is expressed by the following equation.
OUT [64: 0] = {34 (0b0), IN [30: 0]}

Conversion [3] is zero-extended to 65 bits and is expressed by the following equation.
OUT [64: 0] = {33 (0b0), IN [31: 0]}

  The MUX 144 selects either 65-bit data output from the bit expansion unit 142 or 65-bit data held in the SUM register 148 in accordance with a control signal from the control unit 200, and an adder To 146.

  The 65-bit adder 146 adds the 65-bit data output from the bit extension shifter 138 and the 65-bit data output from the MUX 144, and outputs a 65-bit sum. The SUM register 148 holds the 65-bit sum output from the 65-bit adder 146.

  As described above, the product-sum operation unit 104 is roughly divided into a multiplier 132 that obtains a 32-bit product from multiplication of a 16-bit multiplicand and a 16-bit multiplier, and an addition that obtains the sum of 65-bit data. 146. Using this configuration, 32-bit × 32-bit multiplication can be divided into four 16-bit × 16-bit multiplications and executed.

  In accordance with each command, the additional arithmetic unit 106 receives data stored in the quotient register 122, data stored in the SUM register 148, data RGI stored in the I / O register set 300, and data from the main RAM 25. The following additional operations are performed using the read data MRE and data from the dividend register 116 as input values. In the following, “SUM” indicates the value of the SUM register 148, the symbol “{,}” is a bit concatenation, the symbol “=” is an assignment, the symbol “==” is an equal sign, and the symbol “^” is an exclusive logic. Represents the sum.

  The additional arithmetic unit 106 sets output value = SUM [47:16] for the command “MatrixMulti”. However, when a bit different from the value of bit 47 (sign bit) is included in bit 48 or more of “SUM”, a signed saturation operation is performed.

  The additional arithmetic unit 106 sets output value = SUM [31: 0] for the command “Affine” and the command “Trans”. However, when a bit different from the value of bit 31 (sign bit) is included in bit 32 or more of “SUM”, a signed saturation operation is performed.

  The additional arithmetic unit 106 sets output value = SUM [46:31] for the command “Pproj”. However, when a bit different from the value of bit 46 (sign bit) is included in bit 47 or more of “SUM”, a signed saturation operation is performed. When the output value is smaller than the value of the register “ZNear” of the I / O register set 300 or larger than the value of the register “ZFar”, the clipping flag is set.

  For the command “View”, the additional arithmetic unit 106 sets output value = SUM [15: 0] + (value of the register “ViewportOffsetX” or value of the register “ViewportOffsetY”). However, if the output value exceeds a predetermined maximum value (X component is “2047”, Y component is “1023”), the output value is saturated to the maximum value and a clipping flag is set.

  For the command “Dot”, the additional arithmetic unit 106 outputs bit = {SUM [33] (member S1), bit 15 of the register GR12 (stores the Z component of the normal vector) of the I / O register set 300. (Member S2B), 1 bit “0”, absolute value bits [29:25] (Member Dvalue)} of the SUM register 148 (= 8-bit Dot structure).

  The additional arithmetic unit 106 performs the following processing for the command “Bright-P”. Here, (Condition 1) is (Double-sided polygon (Face == 1) and (S1 ^ S2B == 1)) or (Single-sided polygon (Face == 0) and (S1 == 0)). When (Condition 1) is false, the diffused light component = SUM [4: 0] is set. When (Condition 1) is true, the diffused light component = 0 is set as follows. That is, the additional arithmetic unit 106 sets output value (lightness) = diffuse light component + ambient light component (register “Ambient”) + 1. However, when the above addition result exceeds the maximum value “0b11111”, it is saturated to the maximum value.

  For the command “Ccalc”, the additional arithmetic unit 106 calculates the brightness by the same process as the command “Bright-P”. That is, output value = {“B” × lightness, “G” × lightness, “R” × lightness}. “R”, “G”, and “B” are bits [4: 0], [9: 5], and [14:10] of the read data, respectively.

  If any clipping flag is set for the command “Cull”, the additional arithmetic unit 106 sets the output value to the maximum value.

  The additional arithmetic unit 106 sets an output value = √ (32 bits held in the dividend register 116) for the command “Sqrt”.

  For the command “Wcalc (part of the CWD command)”, the additional arithmetic unit 106 sets the output value = the quotient bits [7: 0] when the quotient bits [31: 8] == 0. If the quotient bits [31: 8] are not 0, the output value is 0xFF.

  The additional arithmetic unit 106 logically shifts SUM [32: 1] to the command “Dcalc (part of the CWD command)” according to the value of the register “DepthBias” (zero shift-in). DEP [31: 0] is generated. In this case, the values from “0x0” to “0xF” are used as exponent parts according to the “1” position having the largest weight in DEP [32: 9]. Also, in accordance with the position “1” having the highest weight in DEP [32: 9], consecutive 8 bits following “1” are extracted from SUM [23: 1] and used as a mantissa part. Then, output value = {exponent part (4 bits), mantissa part (8 bits)}.

  The additional arithmetic unit 106 processes the command “APV” in combination with the command “Affine”, the command “Pproj”, and the command “View”.

  For the command “CWD”, the additional arithmetic unit 106 performs processing of a combination of the command “Cull”, the command “Wcalc”, and the command “Dcalc”.

  The additional arithmetic unit 106 processes the command “TDBP” in combination with the command “Trans”, the command “Dot”, and the command “Bright-P”.

  The additional arithmetic unit 106 performs a combination process of the command “Trans” and the command “Dot” for the command “TD”.

  In addition to the processing according to each command as described above, the additional operation unit 106 outputs the state of the result flag (carry flag, overflow flag, sign flag, and divide-by-zero flag) of each operation to the I / O register set 300. To do.

  The data output from the additional arithmetic unit 106 is sent to the bus 150c. The data sent to the bus 150c is sent to the bus 150a or the bus 150b and used as an input value for the next calculation or output to the load / store unit 400 as write data MWR to the main RAM 25.

  As described above, in the present embodiment, processing by a plurality of single commands (hereinafter referred to as “single commands”) can be executed with one command (hereinafter referred to as “composite commands”). That is, composite commands “APV”, “CWD”, “TDBP”, and “TD” are prepared. For this reason, the number of times the command is issued can be reduced, and the processing load on the CPU 5 issuing the command and the overhead of the system are reduced. In addition, since an intermediate value (that is, an output value of a single command) generated in the process of the composite command is not written to the main RAM 25 but is held in the registers GR0 to GR15 in the GE 17, a memory necessary for executing the command The area can be reduced and the bus bandwidth required for memory access can be reduced.

  In the present embodiment, the number of bits of each matrix element as the calculation target data is optimized and stored in the main RAM 25 and the registers GR0 to GR15. Before the calculation, the type conversion units 108a and 108b The optimized operation target data is aligned to the maximum size by zero extension or sign extension. Therefore, it is possible to save a memory area and a register area for storing operation target data. Note that the accuracy and expressible range of each matrix element as the calculation target data are not necessarily uniform, but the data types after conversion by the type conversion units 108a and 108b are uniformly arranged due to the convenience of the arithmetic circuit and the like. .

  When the input command is for instructing execution of a predetermined matrix operation, for example, in the case of the command “Affine”, the control unit 200 does not convert the type conversion unit 108a and the predetermined element in the input matrix. 108b controls the input data to perform type conversion, and for the elements other than the predetermined elements in the input matrix, the type conversion units 108a and 108b output the input data as it is without performing type conversion. To control.

  Further, in the present embodiment, the Vector 10 format conversion unit 114 extracts members X, Y, and Z from the Vector 10 format data (see FIG. 13), and as data VCT in units of X, Y, and Z members. , Output to MUX 112a and 112b. However, before outputting each member X, Y, and Z, the Vector 10 format conversion unit 114 performs an expansion conversion from 1 to 8 times on each member X, Y, and Z according to the value of the member Scale. Apply. Since the execution unit 100 processes the enlarged and converted data in this way, a plurality of expressible ranges (FIG. 5) can be obtained by changing the setting of the scale factor while keeping the size of the data to be actually subjected to computation constant. 10 (b)) can be supported. Thereby, it is possible to save a memory area and a register area for storing operation target data.

  Furthermore, in this embodiment, the polygon is defined by one depth value (that is, it does not have a depth value for each vertex), but the command “CWD” and (Equation 34) are used for the Z-axis of three vertices. The polygon depth value can be calculated from the addition result of the components. In this case, the GE 17 converts the addition result into a 12-bit floating point number format, adds the value of the conversion result and the initial depth value stored in the member “Depth” of the polygon structure instance, and adds the result. The result is written back to the member “Depth” (see (Expression 35)). The depth initial value functions as a bias for the depth value, thereby enabling expression that intentionally increases or decreases the drawing priority of polygons. Also, by expressing the depth value in a floating-point number format, a wide range of coordinate space can be covered with a small number of bits. In addition, the depth value can be expressed with high accuracy in a region close to the viewpoint and with coarse accuracy in a far region, and can be expressed in accordance with the accuracy required for rendering three-dimensional graphics with a depth value of a small number of bits.

  The register “DepthBias” sets the bias of the exponent part of the depth value of the polygon (see (Expression 34)). Since the CPU 5 can freely access this register, the depth value can be optimized according to the degree of dispersion of a plurality of polygons in the three-dimensional space. That is, even if the depth value has a limited accuracy, the arrangement order of the polygons in the depth direction can be expressed correctly, so that the memory usage can be saved.

  Further, in the present embodiment, in the command “Pproj” (or “APV” including “Pproj”) and the command “Cull”, at least one of the Z coordinates of the three vertices of the polygon is not within the range of the view volume VV. As for the polygon, when “0” is set in the field “InvalidStructureRemove” of the register “GECommand”, a value outside the drawing range is set to the coordinates of the three vertices to prevent drawing (referred to as first culling). .) Thereby, the load of drawing processing can be reduced.

  On the other hand, the command “Pproj” (or “APV” including “Pproj”) and the command “Cull” are used for a polygon in which at least one of the Z coordinates of the three vertices of the polygon is not within the range of the view volume VV. When “1” is set in the field “InvalidStructureRemove” of “GECommand”, the polygon structure instance is removed from the polygon structure array (referred to as second culling). As a result, the memory usage can be saved and the drawing processing load can be reduced.

  As a process for a polygon in which at least one of the Z coordinates of the three vertices of the polygon is not within the range of the view volume VV, either the first culling or the second culling is set by setting a value in the field “InvalidStructureRemove” of the register “GECommand”. Can be selected. Therefore, the CPU 5 can select the first culling when it is necessary to refer to and prepare the output result, and otherwise the second culling can be selected to save the memory.

  The CPU 5 can freely set the size of the view volume VV by accessing the registers “ZNear” and “ZFar”. Therefore, the CPU 5 can freely control the range of the three-dimensional space to be drawn.

  Further, in the present embodiment, the command “Cull” uses the vertex coordinates after projection to the two-dimensional orthogonal coordinate system, not the three-dimensional orthogonal coordinate system, to determine the front and back of the polygon by the vector cross product operation for back surface culling. This greatly reduces the amount of computation.

  Further, in the present embodiment, the command “Cull” is set to “0” in the field “InvalidStructureRemove” of the register “GECommand” for the polygon that is determined that the back surface appears in the front / back determination of the polygon. In this case, a value outside the drawing range is set to the coordinates of the three vertices so as not to be drawn (first culling). Thereby, the load of drawing processing can be reduced.

  On the other hand, the command “Cull” indicates that the polygon structure that has been determined that the reverse side appears in the front / back determination of the polygon, if “1” is set in the field “InvalidStructureRemove” of the register “GECommand”. Remove the instance from the polygon structure array (second culling). As a result, the memory usage can be saved and the drawing processing load can be reduced.

  As a process for the polygon that is determined to have the back surface appearing, either the first culling or the second culling can be selected by setting a value in the field “InvalidStructureRemove” of the register “GECommand”. Therefore, the CPU 5 can select the first culling when it is necessary to refer to and prepare the output result, and otherwise the second culling can be selected to save the memory.

  Furthermore, according to the present embodiment, the command “View” adds the offsets “offx” and “offy” to the X component and Y component of each vertex coordinate of the polygon after perspective projection conversion, and the addition result It is determined whether or not the vertex coordinates composed of the X component and the Y component are within a predetermined range. In this way, it is possible to calculate whether the polygon after offset addition is within a predetermined range by using the vertex coordinates after projection to the two-dimensional orthogonal coordinate system instead of the three-dimensional orthogonal coordinate system. The amount is greatly reduced.

  When the command “Cull” determines that the polygon after the offset addition is outside the predetermined range, if “0” is set in the field “InvalidStructureRemove” of the register “GECommand”, the command 3 A value outside the drawing range is set to the coordinates of the vertex to prevent drawing (first culling). Thereby, the load of drawing processing can be reduced.

  On the other hand, when the command “Cull” determines that the polygon after the offset addition is outside the predetermined range, if “1” is set in the field “InvalidStructureRemove” of the register “GECommand”, the polygon structure Remove the instance from the polygon structure array (second culling). As a result, the memory usage can be saved and the drawing processing load can be reduced.

  As processing when the polygon after offset addition is outside the predetermined range, either the first culling or the second culling can be selected by setting a value in the field “InvalidStructureRemove” of the register “GECommand”. Therefore, the CPU 5 can select the first culling when it is necessary to refer to and prepare the output result, and otherwise the second culling can be selected to save the memory.

  The offsets “offx” and “offy” can be set to arbitrary values by the CPU 5 accessing the register “ViewportOffsetX” and the register “ViewportOffsetY”, respectively. In this way, by allowing the CPU 5 to change the offset added to the coordinates after projection onto the two-dimensional coordinate system, the viewport can be set at an arbitrary position in the display screen.

  In addition, this invention is not restricted to said embodiment, It is possible to implement in a various aspect in the range which does not deviate from the summary.

It is a block diagram which shows the internal structure of the multimedia processor 1 by embodiment of this invention. 2 is a flowchart showing an outline of a flow of graphics processing by the multimedia processor 1 of FIG. 1. It is a figure which shows an example of the coordinate conversion flow in this Embodiment. It is a flowchart which shows the flow of the vertex coordinate conversion process of the polygon by GE17 of FIG. It is a flowchart which shows the flow of the lighting process with respect to the polygon in texture mapping mode. It is a flowchart which shows the flow of the lighting process with respect to the polygon in Gouraud shading mode. (A) It is an illustration figure of the surface of a polygon. (B) It is an illustration figure of the back surface of a polygon. It is explanatory drawing of view volume clipping. (A) It is an illustration figure of the texture mapping which gave perspective collect. (B) It is an illustration figure of the texture mapping which has not performed perspective collect. It is a block diagram which shows the internal structure of GE17 of FIG. FIG. 11 is an explanatory diagram of various registers included in the I / O register set 300 of FIG. 10. (A) It is a figure which shows the structure of a Matrix32 arrangement | sequence. (B) It is a figure which shows the structure of the element of the Matrix32 arrangement | sequence of Fig.12 (a). (A) It is a figure which shows the structure of Vector10 structure. (B) It is explanatory drawing of the member of Vector10 structure. (C) It is a figure which shows the structure of member "X"-"Z" of the Vector10 structure. (A) It is a figure which shows the structure of Vector16 structure. (B) It is explanatory drawing of the member of Vector16 structure. (C) The structure of the member “Z” of the Vector16 structure. (D) It is a figure which shows the structure of member "X" of a Vector16 structure, and "Y". (A) It is a figure which shows the structure of Vector32 structure. (B) It is explanatory drawing of the member of Vector32 structure. (A) It is a figure which shows the structure of a Dot structure. (B) It is explanatory drawing of the member of a Dot structure. It is a figure which shows the structure of the polygon structure (GE input format) of texture mapping mode. It is explanatory drawing of the member of the polygon structure (GE input format) of texture mapping mode. It is a figure which shows the structure of the polygon structure (GE input format) of a Gouraud shading mode. It is explanatory drawing of the member of the polygon structure (GE input format) of Gouraud shading mode. It is a block diagram which shows the internal structure of the execution unit 100 of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Multimedia processor, 3 ... External memory interface, 4 ... DMAC, 5 ... CPU, 7 ... CPU local RAM, 9 ... RPU, 11 ... Color palette RAM, 13 ... SPU, 15 ... SPU local RAM, 17 ... GE, 19 ... YSU, 21 ... external interface block, 23 ... main RAM access arbiter, 25 ... main RAM, 27 ... I / O bus, 29 ... video DAC, 31 ... audio DAC block, 51 ... external bus, 50 ... external memory, DESCRIPTION OF SYMBOLS 100 ... Execution unit, 102 ... Division unit, 104 ... Product-sum operation unit, 106 ... Additional operation unit, 108a, 108b ... Type conversion unit, 114 ... Vector10 format conversion unit, 200 ... Control unit, 300 ... I / O register set , 400 ... Load / Store Uni Door.

Claims (22)

An arithmetic processing device for processing geometric operations,
Execution means for performing geometric operations;
Control means for interpreting a command input from the outside and controlling the execution means to cause the execution means to execute processing according to the input command;
Data holding means for holding calculation target data used in the geometric calculation and / or calculation result data which is a result of the geometric calculation;
A plurality of types of the commands are prepared,
The execution means receives the calculation object data from an external memory of the arithmetic processing unit and / or the data holding means according to the command belonging to the first group among the plurality of types of commands, and performs geometric calculation. Execute, and output the operation result data to the external memory,
Of the plurality of types of commands, the command belonging to the second group is an instruction for instructing to execute a predetermined combination of different commands belonging to the first group,
The execution means holds the external memory and / or the data when executing the first command among the commands included in the predetermined combination in response to the command belonging to the second group. The calculation target data is received from the means, the geometric calculation is performed, and when executing the command other than the first command, the calculation target data is received from the data holding means, and the geometric calculation is performed.
After executing the command other than the last command among the commands included in the predetermined combination, the calculation result data is output to the data holding unit, and after executing the last command, the calculation result is output. An arithmetic processing unit that outputs data to the external memory and / or the data holding means. An arithmetic processing device for processing geometric operations,
Execution means for performing geometric operations;
Control means for interpreting a command input from the outside and controlling the execution means to cause the execution means to execute processing according to the input command;
Data holding means for holding calculation target data used in the geometric calculation and / or calculation result data which is a result of the geometric calculation;
The execution means includes
According to the control from the control means, the input data is output as it is or converted into a predetermined data type and output,
Calculation means for performing calculation using data output from the type conversion means,
The control means reads the calculation target data from an external memory of the arithmetic processing unit and / or the data holding means, inputs the data to the type conversion means, and outputs the data output from the type conversion means to the calculation means The arithmetic processing unit controls the execution unit to write data output from the arithmetic unit to the memory and / or the data holding unit as the arithmetic result data.   When the input command is for instructing execution of a predetermined matrix operation, the control means converts the data input by the type conversion means to the predetermined data type for a predetermined element in the input matrix. The execution means is controlled so as to convert the data into the input matrix, and for the elements other than the predetermined element in the input matrix, the type conversion means does not convert the input data into the predetermined data type as it is. The arithmetic processing apparatus according to claim 2, wherein the execution means is controlled to output the data.   The arithmetic processing apparatus according to claim 2 or 3, wherein the conversion of the predetermined data type performed by the type conversion means is zero extension and / or sign extension. An arithmetic processing device for processing geometric operations,
Execution means for performing geometric operations;
Data holding means for holding calculation target data used in the geometric calculation and / or calculation result data which is a result of the geometric calculation;
The execution means includes
Numerical value extraction means for receiving data including a plurality of numerical values and one magnification, selecting one of the plurality of numerical values, performing multiplication with the magnification, and outputting a multiplication result;
Calculation means for performing an operation using the multiplication result output by the numerical value extraction means,
The execution unit reads the calculation target data from a memory external to the arithmetic processing unit and / or the data holding unit, inputs the data to the numerical value extraction unit, and outputs the multiplication result output from the numerical value extraction unit to the calculation An arithmetic processing apparatus that inputs data to the means and writes data output from the arithmetic means to the memory and / or the data holding means as the arithmetic result data. An arithmetic processing device for processing geometric operations,
A plurality of vertex coordinates defining a polygonal graphic element in a three-dimensional orthogonal coordinate system as input, a coordinate conversion means for performing coordinate conversion of each vertex coordinate;
An arithmetic processing unit, comprising: a total calculation unit that calculates a total of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion, and outputs the calculated total as a depth value of the polygonal graphic element. An arithmetic processing device for processing geometric operations,
A plurality of vertex coordinates defining a polygonal graphic element in a three-dimensional orthogonal coordinate system as input, a coordinate conversion means for performing coordinate conversion of each vertex coordinate;
A sum total calculating means for calculating a sum of predetermined coordinate axis components of the plurality of vertices after the coordinate transformation;
An initial value of the total value and the depth value of the polygonal graphic element as input, an addition means for adding the total and the initial value, and outputting the addition result as a depth value of the polygonal graphic element; Arithmetic processing device provided.   The arithmetic processing unit according to claim 6 or 7, wherein the sum calculation means converts the sum into a floating point number format and outputs the result. Bias holding means for holding a bias value of the exponent part of the sum in a floating-point number format;
The arithmetic processing apparatus according to claim 8, wherein the bias holding unit is accessible from outside the arithmetic processing apparatus and can be read and written from the outside.   A culling means for setting a value outside the drawing range to all the vertex coordinates of the polygonal graphic element when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range. The arithmetic processing device according to claim 6 or 7, further comprising:   A culling means for removing data defining the polygonal graphic element from the drawing data string when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range. The arithmetic processing apparatus of Claim 6 or 7 provided. When at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within a predetermined range, a value outside the drawing range may be set for all the vertex coordinates of the polygonal graphic element. A first culling means capable of;
When at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate conversion is not within the predetermined range, the data defining the polygonal graphic element can be removed from the drawing data string. A second culling means;
The first culling means or the second culling means as means for executing processing when at least one of the plurality of predetermined coordinate axis components of the plurality of vertices after the coordinate transformation is not within the predetermined range. The arithmetic processing apparatus according to claim 6, further comprising selection means for selecting any of the above. A threshold holding means for holding a threshold for setting the predetermined range;
13. The arithmetic processing apparatus according to claim 10, wherein the threshold value holding unit is accessible from outside the arithmetic processing apparatus and can be read and written from the outside. An arithmetic processing device for processing geometric operations,
In the 3D Cartesian coordinate system, each vertex coordinate of a polygonal graphic element defined with the vertex arrangement order representing the clockwise surface and the counterclockwise surface as the back is projected onto the 2D Cartesian coordinate system Projecting means,
Selecting means for selecting a first vertex coordinate, a second vertex coordinate, and a third vertex coordinate from all the projected vertex coordinates;
First vector calculating means for calculating a first vector by subtracting the first vertex coordinates from the second vertex coordinates;
Second vector calculating means for calculating a second vector by subtracting the first vertex coordinates from the third vertex coordinates;
Cross product calculation means for performing cross product calculation of the first vector and the second vector;
An arithmetic processing unit comprising: a determination unit that determines whether a front or back surface of the polygonal graphic element appears in the two-dimensional orthogonal coordinate system based on a sign of a result of the outer product operation.   The arithmetic processing apparatus according to claim 14, further comprising a culling unit that sets a value outside a drawing range to all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element that is determined that the back surface appears.   The arithmetic processing unit according to claim 14, further comprising a culling unit that removes data defining the polygonal graphic element that is determined to have the back surface from the drawing data sequence. A first culling means capable of setting a value outside the drawing range to all vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element determined to have the back surface appear;
Second culling means capable of removing data defining the polygonal graphic element determined to appear the back surface from the drawing data sequence;
The selection means for selecting either the first culling means or the second culling means as means for executing processing when it is determined that the back surface appears. Arithmetic processing unit. An arithmetic processing device for processing geometric operations,
Projection means for projecting each vertex coordinate of a polygonal graphic element defined in the three-dimensional orthogonal coordinate system to the two-dimensional orthogonal coordinate system;
Adding means for adding a predetermined value to each of the coordinate axis components of the projected vertex coordinates;
And a determination unit that determines whether or not a vertex coordinate composed of a coordinate axis component as a result of the addition is within a predetermined range.   A value outside the drawing range is set to all the vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element including the vertex where the vertex coordinate consisting of the coordinate axis component as a result of the addition is determined to be outside the predetermined range. The arithmetic processing device according to claim 18, further comprising culling means.   19. A culling unit that removes data defining a polygonal graphic element including a vertex whose vertex coordinate, which is a coordinate axis component as a result of the addition, is determined to be out of a predetermined range, from the drawing data string. Arithmetic processing unit. A value outside the drawing range is set to all the vertex coordinates in the two-dimensional orthogonal coordinate system of the polygonal graphic element including the vertex where the vertex coordinate consisting of the coordinate axis component as a result of the addition is determined to be outside the predetermined range. A first culling means capable of:
Second culling means capable of removing, from the drawing data string, data defining the polygonal graphic element including a vertex whose vertex coordinate consisting of the coordinate axis component as a result of the addition is determined to be outside a predetermined range; ,
Selection for selecting either the first culling means or the second culling means as means for executing processing when it is determined that the vertex coordinate composed of the coordinate axis component as a result of the addition is out of a predetermined range The arithmetic processing apparatus according to claim 18, further comprising means. A predetermined value holding means for holding the predetermined value used by the adding means;
The arithmetic processing unit according to claim 18, wherein the predetermined value holding unit is accessible from outside the arithmetic processing unit, and can be read and written from the outside.

Images