JP3146058B2 - Parallel processing type processor system and control method of parallel processing type processor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processing type processor system for executing instructions at a parallel level.
More specifically, the present invention relates to a function for controlling trap processing and stall processing in a parallel processing type processor system.

[0002]

2. Description of the Related Art In recent years, a CPU called a super scalar processor or VLIW capable of parallel processing at a machine language instruction level has been developed and realized as a VLSI chip in order to meet a growing demand for a high-speed personal computer. I have. In such a parallel processing CPU, the RISC instruction is used as a basic instruction set, and a plurality of instructions are simultaneously fetched and executed, thereby improving the processing performance. In particular, the super scalar processor is an RI that performs sequential processing at the conventional instruction level.
It has an architecture that realizes SC and can maintain compatibility at the user program level, and is highly expected by computer users.

A processor system capable of performing parallel processing at an instruction level employing such a conventional trap control method has a configuration as shown in FIG.

The configuration shown in FIG. 19 realizes a processor system capable of executing parallel processing at the instruction level, and includes an F stage (fetch), a D stage (decode), an E stage (execution), and an M stage (memory). Access) and W stage (register write back), each of which has five pipeline stages, and each instruction is one word long (32 bits).

As shown in FIG. 19, this processor system has an instruction memory 1 for storing instructions;
At the stage, four instructions of a four-word boundary are fetched from the instruction memory 1 at the same time, and at the D stage, the instruction supply lines 20, 21, 22 and 2
An instruction issuing unit 2 for supplying an executable instruction via an instruction supply line 3; an arithmetic logic unit (ALU0 and ALU1) 3
A floating point adder (FADD) 5 for performing floating point addition and subtraction at the E stage according to the instruction supplied from the instruction supply line 22; and performing floating point multiplication and division at the E stage according to the instruction supplied from the instruction supply line 23. A floating point multiplier (FMUL) 6 to perform; according to the outputs of ALU03 and ALU14,
A memory access unit (MA0 and MA0) that performs memory access processing on the 2-port data memory 25 in the M stage
MA1) 7 and 8; according to the output of FADD5 and FMUL6
Floating-point exception check unit (EC) for checking exceptions in floating-point calculations at each M stage
1 and EC2) 9 and 10; MA0, MA1 at W stage
8, EC1 9 and EC2 10, four write ports for receiving the outputs, and the E stage with operand data supply lines 12 to
And a multiport register file 11 having 12 ports consisting of 8 read ports for supplying operand data to ALU03, ALU14, FADD5, and FMUL6 via an interface 19.

In the configuration of FIG. 19, MA07 and MA07
MA1 8 causes an arithmetic exception trap, such as a page fault or overflow, and EC19 and EC2
10 causes a floating point operation exception trap.

To cope with such an exception trap, the processor system further includes a trap cause register 30 for storing the cause of the trap and a trap for storing the address of the instruction causing the trap. MA0 7, MA18, EC sent via the address register 32 and the trap request signal lines 43 to 46
In response to the trap cause from 19 and EC2 10, the trap signal is asserted on the trap signal lines 34-38 in response to the input to the trap cause register 30 and the trap address register 32 via the signal lines 40 and 42 as appropriate. And a trap control unit 33 for generating the trap.

The trap signal on the trap signal line 34 is sent to the instruction issuing unit 2, ALU03 and ALU14,
On the other hand, the trap signals on the trap signal lines 35 to 38 are sent to MA0 7, MA1 8, EC1 9 and EC2 10, respectively. In response to a trap signal from the trap control unit 33, an execution invalidation flag is set in each unit to abort the subsequent instruction processing in the pipeline stage, while the instruction issuing unit 2 relates to a predetermined trap processing routine. Instruction fetch is started, and in this trap processing routine, the trap cause and the trap address stored in the trap cause register 30 and the trap address register 32 are used.

More specifically, the trap control unit 33
Has a configuration as shown in FIG. That is, the trap control unit 33 further includes an M stage program counter (MPC) 51 for storing a common part of the word address obtained by removing the lower two bits of the address of the instruction currently executed in the M stage;
M stage subprogram counters (submpc1, submpc2, submpc3) for storing the individual parts of the word address indicated by the lower two bits of the address of the instruction currently executed by MA0 7, MA1 8, EC1 9 and EC2 10.
And submpc4) 53, 54, 55 and 56; the smallest entry among the M-stage subprogram counters 53 to 56 is combined with the entry of the MPC 51 and the trap address 4 to be supplied to the trap address register 32.
2 is output as an output 47 for generating 2 and the M-stage subprogram counter 53-
A trap data generation unit 57 that outputs a trap cause sent via one of the trap request signal lines 43 to 46 corresponding to 56 as a trap cause 40 supplied to the trap cause register 30 is provided.

The trap signal on the trap signal line 34 is one of the trap request signal lines 43 to 46.
, Is asserted when a trap cause is received, and each of the trap signals 35 to 38 is set to a trap request signal line 43 to 46.
And the corresponding one of the M-stage subprogram counters 53 to 56 receives the trap request from one of the M-stage subprogram counters 35 to 56 that have generated the trap request.
Asserted when it has an entry that is greater than or equal to an entry in one of 56.

FIG. 21 is a diagram showing an example of a program executed by the processor system of FIG.
2 is a pipeline processing by the processor system of FIG. 19 using the above-described conventional trap control method.
21 shows the progress of a page fault caused by the "load" instruction when the program of FIG. 21 is executed, and the hatched portion indicates the aborted instruction. As shown in FIG. 22, in the conventional trap control, when a trap occurs due to execution of an (n + 2) th “load” instruction while program execution is in progress, an instruction having an instruction number greater than or equal to n + 2 is executed. Only aborted.

[0012]

However, in such a conventional trap control method, a page fault is detected by the MA18 at the C + 3 cycle, and a trap request is indicated via the trap request line 44. The trap signals on the trap signal lines 35-38 are not determined until the entries in the M-stage subprogram counters 53-56 are compared with each other to determine which is greater, and such a comparison process is performed. There is a problem that the clock frequency is reduced because the cycle time is considerably long.

The RISC requires a configuration having a simple data path and a simple control circuit.
Although the data path of a superscalar processor having an ISC data path is not so complicated, the control circuit of the superscalar processor is very complicated because it requires instruction supply control and the like. In particular, without the support of software such as an OS, it is impossible to continue processing, and the hardware for processing a so-called exception case becomes very complicated, and the design of such hardware becomes very complicated. However, there is a problem that such hardware often becomes a critical path in the realization of a superscalar processor.

The present invention has been made to solve such problems of the prior art, and has a trap and stall control function capable of processing without increasing the cycle time and preventing a decrease in clock frequency in the system. It is an object of the present invention to provide a parallel processing type processor system, such as a superscalar processor, which incorporates a processor.

[Configuration of the Invention]

[0016]

In order to solve the above-mentioned problems, a parallel processing type processor system according to the present invention comprises N (N is an integer) arithmetic units for simultaneously executing a plurality of instructions, and the N arithmetic units. Instruction supply means for supplying an instruction to be executed; and M (N ≧ M, M is an integer) instructions are simultaneously supplied from the instruction supply means to the N operation units, and at least one of the M instructions When a processing exception occurs in the execution of one instruction, the N instruction is executed so as to abort the processing of the M instructions supplied to the N arithmetic units at the same time.
And trap control means for controlling the number of arithmetic units.

Further, in the control method of the parallel processing type processor system according to the present invention, a step of simultaneously supplying M (N ≧ M) instructions to N arithmetic units, and at least one instruction among the M instructions And controlling the N arithmetic units so as to abort all the processing of the M instructions supplied to the N arithmetic units when a processing exception occurs in the execution. And

[0018]

According to the present invention, when a processing exception occurs during the execution of one or more instructions among the M instructions simultaneously supplied to the N arithmetic units by the instruction supply means, the M simultaneously supplied instructions are output. Means for aborting the execution of all of the instructions, if at least one exception occurs during the processing of the M instructions supplied to the computing unit at the same time, all M instructions are aborted and the OS By dispatching to the processing routine, the hardware for exception handling is simplified.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a parallel processing type processor system according to the present invention will be described in detail with reference to FIGS.

The configuration shown in FIG. 1 realizes a processor system capable of performing parallel processing at an instruction level, and includes an F stage (fetch), a D stage (decode), an E stage (execution), and an M stage ( There are five pipeline stages, a memory access) and a W stage (register write back), and each instruction is one word long (32 bits).

In the first embodiment, as shown in FIG. 1, a processor system includes an instruction memory 101 for storing instructions and four instructions of a 4-word boundary at the F stage from the instruction memory 101 at the same time. And
Instruction issuance to supply executable instructions via instruction supply lines 120, 121, 122 and 123 at E stage, taking into account data and control dependencies among the four fetched instructions at D stage Unit 102
Arithmetic logic units (ALU0 and ALU1) for executing arithmetic logic operations and memory address calculations in the E stage in accordance with the instructions supplied from the instruction supply lines 120 and 121
103 and 104; a floating point adder (FADD) 105 for performing floating point addition and subtraction at the E stage according to the instruction supplied from the instruction supply line 122; and floating point multiplication and division at the E stage according to the instruction supplied from the instruction supply line 123 Floating point multiplier (FMUL) 106 for performing ALU0103
And the memory access units (MA0 and MA1) 107 and 1 for performing a memory access process on the 2-port data memory 125 in the M stage according to the output of the ALU 1104
08; a floating-point exception check unit (EC1) for performing an exception check in the floating-point calculation in each M stage according to the output of the FADD 105 and the FMUL 106
And EC2) 109 and 110; MA0 10 at W stage
7, four write ports for receiving outputs of MA1 108, EC1 109 and EC2 110, and ALU0103 and ALU1 via operand data supply lines 112 to 119 in the E stage.
12 comprising eight read ports 104 for supplying operand data to 104, FADD 105 and FMUL 106
Multi-port register file 111 having three ports
And

In the configuration shown in FIG. 1, an arithmetic operation exception trap such as a page fault or an overflow is generated by MA0 107 and MA1 108, and EC1 10
9 and EC2 110 cause a floating point operation exception trap.

To deal with such an exception trap, the processor system further includes a trap cause register 130 for storing the cause of the trap occurrence; An abort address register 131 for storing an address of an instruction having the same; a trap address register 132 for storing an address of an instruction causing a trap; and trap request signal lines 143 to 146.
MA0 107, MA1 108, EC1 10 sent via
9 and the trap cause from EC2 110 and asserts a trap signal accordingly via trap signal line 134, while trap cause register 130, abort address register 131, and trap signal via signal lines 140, 141 and 142. A trap control unit 133 for appropriately generating an input to the address register 132.

The trap signal on the trap signal line 134 is transmitted to the instruction issuing unit 102, ALU0103, ALU110.
4, FADD105, FMUL106, MA0107, MA110
8, sent to EC1 109 and EC2 110, respectively. In response to a trap signal from the trap control unit 133, an execution invalidation flag is set in each unit, and the instruction processing is aborted in a subsequent pipeline stage, while the instruction issuing unit 102 executes an instruction related to a predetermined trap processing routine. Fetching is started, and in this trap processing routine, the trap cause, abort address, and trap address stored in the trap cause register 130, the abort address register 131, and the trap address register 132, respectively, are used.

More specifically, the trap control unit 13
3 has a configuration as shown in FIG. That is, the trap control unit 133 further includes an M stage program counter 1 (MPC) 151 for storing a common part of a word address obtained by removing the lower two bits of the address of the instruction currently executed in the M stage; To generate the abort address indicated by the lower two bits of the address of the instruction having the smallest address among the instructions currently executed and supplied to the abort address register 131 in combination with the entry of the MPC 151. M stage program counter 2 (mpc) 1 for storing an individual part of a word address
52; MA0 at the M stage, MA1 108, EC1 1
09 and M stage subprogram counters (submpc1, submpc2, submpc3 and submpc4) 1 for storing the individual parts of the word address indicated by the lower two bits of the address of the instruction currently being executed by EC2 110.
53, 154, 155, and 156; the smallest entry among the M stage subprogram counters 153 to 156 is combined with the entry of the MPC 151 to provide the trap address 1 supplied to the trap address register 132.
M-stage subprogram counter 1 with the smallest entry, output as output 147 to generate
Trap request signal lines 143-1 corresponding to 53-156
The trap cause sent via one of the trap causes 14 is provided to trap cause register 130.
Trap data generation unit 157 that outputs as 0
The trap cause signal lines 143 to 146
And a trap signal generation unit 158 that generates a trap signal asserted when received from any one of the trap signal lines 134.

FIG. 3 shows the progress of the pipeline processing in the processor system of FIG. 1 when a page fault occurs by the "load" instruction when the program of FIG. 21 is executed. Indicates an aborted instruction. As shown in FIG. 3, in the first embodiment shown in FIG. 1, n + 2
When a trap is generated by execution of the "load" instruction, all the instructions fetched at the same time as the (n + 2) th instruction causing the trap and having instruction numbers n to n + 3 are aborted. Compared to the conventional case shown in FIG. 22, the number of instructions to be aborted is smaller in the conventional case, so that the conventional case may seem to be more efficient. Since the conventional case requires time to determine an appropriate trap signal, the conventional case has a longer cycle time than the first embodiment, and in fact, the first embodiment has higher efficiency. Become.

More specifically, in the pipeline processing shown in FIG. 3, all of the n-th, n + 1-th, n + 2-th and n + 3th instructions enter the M stage in cycle C + 3. An M-stage process for the n-th “fadd” process is performed in EC1 109, an M-stage process for the (n + 1) -th “add” process is performed in MA0 107, and the n + 2-th “load” process M1 processing of MA1 108
, And an M stage process for the (n + 3) th “fmul” process is performed in the EC2 110. In this cycle C + 3, when a page fault is detected at MA1 108, MA1 108 notifies trap control unit 133 via trap request signal line 144 that a page fault trap has occurred. Here, in this cycle C + 3, the MPC 151
The word address excluding the lower 2 bits of the (th) to (n + 3) th instructions is stored, and mpc 152 indicates the lower 2 bits of the nth instruction having the lowest address among the instructions currently being executed in the M stage. Stores the word address,
In this case this is zero. On the other hand, submpc1 153, subm
pc2 154, submpc3 155 and submpc4 156 are MA
0, 107, MA1 108, EC1 109, and EC2 110 store word addresses indicating the lower 2 bits of the (n + 1) th, n + 2th, nth, and n + 3th instructions currently being executed. ing.

The trap signal generation unit 158 asserts a trap signal on the trap signal line 134 when any of the trap request signal lines 143 to 146 has a trap request. The asserted trap signal on the trap signal line 134 is sent to the instruction issuing unit 102, ALU0
103, ALU1104, MA0107, MA1108, FADD1
05, FMUL 106, EC1 109 and EC2 110, so that the processing in these units is aborted and at the same time the instruction issuing unit 102 starts fetching instructions for a predetermined trap processing routine.

Here, the trap data generating unit 15
7 detects a trap request on the trap request signal line 144, the submpc corresponding to the trap request signal line 144
2 154 entries are output on signal line 147 which is combined with the MPC 151 entry to generate a trap address 142, in this case the address of the n + 2th instruction, The address is stored in the trap address register 13 via the trap address signal line 142.
2 is stored.

On the other hand, the entry of the MPC 151 is changed to the mpc 152
Abort address 141 is obtained by combining with the above entry, and the abort address n in this case is n.
The address of the instruction is the abort address signal line 141
Through the abort address register 131.

Further, submpc1 153, subm which stores the minimum address in the M stage program counter associated with the trap request signal line which is currently issuing a trap request.
The signal on one of the trap request signal lines 143 to 146 corresponding to one of pc2 154, submpc3 155 and submpc4 156 is output to the trap cause signal line 140 and stored in the trap cause register 130. In this case, since the trap request is issued only from the trap request signal line 144, the signal of the trap request signal line 144 is output to the trap cause signal line 140 and the trap cause register 1
30 will be stored.

Here, the case where all the n-th to (n + 3) -th instructions are fetched at the same time has been described. However, there is a case where the entry of mpc is not 0 due to data dependency between the four instructions. It is possible. When two or more trap requests are detected on the trap request signal lines 143 to 146, submpc1 153, submpc2 154, submpc
Of the 3 155 and submpc 4 156, the entry that stores the lowest address among the instructions currently executed in the M stage is output to the signal line 147.

In this embodiment, since the instruction causing the trap and the instruction to be aborted are different, the abort address register 131 and the trap address register 1
Both 32 are required.

In this embodiment, at least one of the trap request signal lines 143 to 146 is provided.
Since the trap signal is asserted as soon as there is one trap request, the entry on the trap signal line can be determined very quickly. On the other hand, trap cause register 1
30 and the trap address 14 stored in the trap address register 132
2 is an M stage subprogram counter 153 to 15
Since these are determined as a result of comparing the entries in 6, these cannot be determined much later. However, generally speaking, in order to abort the memory access, the entry in the trap signal line needs to be determined quickly, but the trap data stored in the register may be determined much later. In, there is no need to increase the cycle time of the processor system.

Therefore, according to the first embodiment, a parallel processing type processor system such as a super scalar processor incorporating a trap control function capable of functioning without increasing the cycle time so as to prevent a decrease in the clock frequency in the system is provided. Can be provided.

Next, a second embodiment of the parallel processing type processor system according to the present invention will be described in detail with reference to FIGS.

The second embodiment is an application of the first embodiment described above, and incorporates a stall control function in addition to the trap control function of the first embodiment for the following reasons.

That is, by modifying the system of the first embodiment,
As shown in FIG. 4, when the system further includes a main memory 161 and an I / O device 162 connected to the instruction cache memory 101A and the two-port data cache memory 125A via a bus line, trap control is performed. Trouble may occur only with the function. The cause of the trouble here is that the I / O device 162 typically includes a plurality of I / O registers mapped to memory addresses.
It is. Access to such an I / O register is based on I
This is done by the same instruction as the memory access instruction that specifies the address of the / O register, and the cache is not normally used for this purpose. The I / O registers are used to set commands and parameters to the I / O device
Used to indicate the status of the register to the processor. For example, in response to an access for reading the status of the I / O device 162, the status register is erased when the status of the I / O device 162 is read by the processor. There is an I / O register that changes the internal state of the I / O register in such a way that the I / O register changes.

When such an I / O device 162 is used, the system having only the trap control function of the above-described first embodiment encounters the following problems. That is, in this system, two access units 107 and 108 are provided for a two-port data cache memory 125A that can execute two memory access instructions simultaneously. Therefore, in the memory access units 107 and 108, two I / Os
The O access instruction may arrive at the M stage at the same time. However, since there is only one bus line 1601 for the purpose of I / O access, it is impossible to process two I / O access instructions simultaneously. As a result, the processing of the first one of the two I / O access instructions must be completed on the I / O device 162 side before the processing of the second I / O access instruction starts.

In such a situation, the second I / O
An exception such as a bus error may occur in the processing of the access instruction. In such a case, if the system
If only the trap control function of the embodiment is used, both I / O access instructions will be aborted. Therefore, when the original program is executed again after performing the appropriate trap processing routine, even though the first I / O access instruction is considered to have been completed on the I / O device 162 side, this is repeated. Will be executed. In this case, the first I / O access instruction happens to be
For an instruction that reads the status register, since the status register has already been read once before the trap occurred, the contents of this status register have already been erased and will no longer be available when the first I / O access instruction is executed again. Trouble arises because it is no longer correct.

The above-mentioned trouble is basically caused by the fact that a request for use of the same operation resource which cannot be detected in the D stage may compete in a subsequent pipeline stage. Therefore, if the D stage can detect that these two memory access instructions are actually two I / O access instructions, avoid trouble by not supplying these two memory access instructions to the processor at the same time. However, on the other hand, it is required to use a special instruction only for the I / O access instruction.

In the configuration of the second embodiment shown in FIG. 4, this problem is solved as follows by such a special I / O.
The problem is solved without using the O access instruction.

First, in the second embodiment,
When an instruction is to be supplied to ALU0103 and ALU1104 at the same time, instruction issuance unit 102A causes instruction supply to ALU0103 and ALU1104 so that the instruction having the smaller address to be executed first is supplied to ALU0103. Control. Therefore, the memory access instruction
When it reaches MA0 107 and MA1 108 at the same time,
0 107 will always have a memory access instruction to be executed first.

Second, in the configuration of FIG. 4, the stall request signals are MA0 107, MA1 108, EC1 109 and EC2 110.
To stall request signal lines 170, 71, 72 and 173
Further includes a stall control unit 163, each of which is supplied via
all1 signal 180, stall2 signal 181 and stallv1 signal 1
82 is the instruction issuing unit 102A, ALU0103, ALU11
04, FADD105, FMUL106, MA0107, MA1 10
8, output to EC1 109, EC2 110 and trap control unit 133 to perform appropriate stall control as described below.

The stall1 signal 180 is composed of MA0 107 and MA1 1
08, a stall request from any of EC1 109 and EC2 110, and a stall2 signal 181
Are MA0 107, MA1 108, EC1 109 and EC2 11
Asserted when there is a stall request from any of the STAs, while the stallv1 signal 182 indicates that
1 Lower 2 of the address of the instruction currently being executed at 108
Indicates a bit.

In accordance with the values of these stall1, stall2 and stallv1 signals 180-182, the pipeline processing in this system is controlled as follows.

(1) Pipeline <103, 107> of ALU0103 and MA0107: (a) M stage and W stage: If stall2 signal 181 is negated, pipeline processing is performed regardless of stall1 signal 180.

(B) E stage: If the stall1 signal 180 is negated, pipeline processing is performed.

(2) Pipeline <104, 108> of ALU 1104 and MA 1 108: If stall 1 signal 180 is negated, pipeline processing is performed.

(3) Pipeline <105, 109> of FADD 105 and EC1 109 and FMUL 106 and EC2 11
0 pipeline <106, 110>: (a) M stage and W stage: If stall1 signal 180 is negated, pipeline processing is performed regardless of stall1 signal 180.

The pipeline processing also includes the stall1 signal 180
Is asserted, stall2 signal is negated, and stal
The lv1 signal 182 is a submpc3155 and submpc4 156 that store the lower two bits of the instruction currently being processed by the M stage in EC1 109 and EC2 110, respectively.
Is performed when a value greater than each of the values is indicated.

(B) E stage: If the stall1 signal 180 is negated, pipeline processing is performed.

In the second embodiment, mpc 15
The values stored in 2 are stall1, stall2 and stallv1
It is determined as follows according to the values of the signals 180 to 182. That is, when stall1 signal 180 is not asserted,
The mpc 152 is loaded with the lowest address in the instruction executed in the E stage, and when both the stall1 signal 180 and the stall2 signal 181 are asserted, the mpc 152 maintains the previous value, but the stall1 signal 180 Is asserted, but the stall2 signal 181 is not asserted, the mpc 152 is loaded with the value indicated by the stallv1 signal 182.

Therefore, in this second embodiment, MA1 108
If there is a stall request only from the pipeline <10
3, 107> is completed, and only when the address of the instruction currently being processed is smaller than the address of the instruction in MA1 108, pipelines <105, 109> and <10
6, 110> is completed.

As a result, when the first and second I / O access instructions arrive at MA0 107 and MA1 108 at the same time, MA1 108 outputs a stall request to stall control unit 163, but MA0 107 takes one clock cycle. The stall request is not output unless it is impossible to complete the I / O access processing within the period. And EC1 1
09 and EC2 110 also do not output a stall request, st
Only the all1 signal 180 is asserted and the stall2 signal 182
Is not asserted. In such cases, the pipeline <
303, 107> are processed, and the mpc 152 has
The value of the stallv1 signal 182 is loaded, and the state of the system becomes a state where the execution of the instruction before the second I / O access instruction is completed.

Therefore, even when an exception occurs for the second I / O access instruction, the first I / O access instruction is not executed again. On the other hand, pipeline <104,
108> and the processing of the pipeline for instructions having addresses greater than the second I / O access instruction are stalled until the stall1 signal 180 becomes negated.

When MA0 107 outputs a stall request because it is impossible to complete the I / O access processing within one clock cycle, the first I / O access instruction is completed and stall2 signal 181 is negated. , The stall1 and stall2 signals 182 are asserted, so that all pipelines are stalled.

FIG. 6 shows the progress of the pipeline processing in the processor system of FIG. 4 when a bus error occurs at the (n + 2) th "load" instruction when the program of FIG. 5 is executed. . As shown in FIG. 6, in the second embodiment of FIG. 4, when the stall request is generated by the execution of the (n + 2) th instruction in the cycle C + 3, the n-th “fad” performed in EC1 109 is performed.
The M-stage processing for the “d” processing and the M-stage processing for the (n + 1) -th “add” processing performed in MA0 107 end in the next cycle C + 4.
M-stage processing for n + 2th "load" operation and
The M-stage processing for the n + 3rd “fmul” operation on EC2 110 is stalled in the next cycle C + 4 and does not end until the next cycle C + 5. On the other hand, all subsequent instructions having addresses larger than the (n + 2) th instruction are also stalled in cycle C + 4.

Here, after the processing of the instruction is stalled because the possibility of an exception occurring during the execution of the instruction cannot be denied, if the exception actually occurs during the execution of the instruction, the processing of the instruction is aborted. You. Otherwise, processing of the instruction is resumed because no exception actually occurred during instruction execution.

Therefore, according to the second embodiment, a parallel processing type such as a super scalar processor incorporating a trap and stall control function capable of functioning without increasing the cycle time so as to prevent a decrease in the clock frequency in the system. A processor system can be provided.

Next, a third embodiment of the parallel processing type processor system according to the present invention will be described in detail with reference to FIG.

The third embodiment is a generalization of the stall control function of the second embodiment in a more general setting.

In the third embodiment, as shown in FIG. 7, the processor system includes an instruction cache memory (I-cache) 201 for storing instructions and an F-stage.
At the same time, four instructions of a 4-word boundary are fetched from the I-cache 201 at the same time, and the data dependency and the control dependency between the four fetched instructions are considered in the D stage.
Instruction supply lines 220, 221, 222 and 22 at stage
An instruction issuance unit 202 for supplying an executable instruction via the instruction supply line 3; and an arithmetic operation unit (ALU0 and ALU) for executing an arithmetic and logic operation and a memory address calculation in the E stage according to the instruction supplied from the instruction supply lines 220 and 221.
1) 203 and 204; an integer multiplier / divider 205 for performing an integer multiplication / division in the E stage according to a command from ALU0203 and ALU1204; and ALU0203 and ALU120.
A data cache memory (D-cache) 206 for storing data to be accessed from the memory 4;
A floating-point adder (FADD) 20 for performing floating-point addition and subtraction at the E stage in accordance with an instruction supplied from
7; E in accordance with the instruction supplied from the instruction supply line 223
A floating point multiplier (FMUL) 208 for performing floating point multiplication in the stage; a floating point divider (FDIV) 209 for performing floating point division in the E stage in accordance with a command from the FMUL 208;
ALU020: an instruction address generation unit 210 for specifying an instruction issued by the ALU020; a control unit 211 for performing trap control and stall control described later;
3. An integer register file 212 for storing the output of the ALU 1204; and a floating-point register file 213 for storing the output of the FADD 207 and the FMUL 208.

As in the second embodiment of FIG. 4, the processor system of FIG. 7 further includes an I-cache 201 and a D-ca
main memory 214 for storing data cached in che 206; I / O device 215 including I / O registers; main memory 214 and I / O device 215
Bus line 21 for connecting to I-cache 201 and D-cache
6.

In addition, the processor system of FIG.
Further, a predecoder 217 provided between the I-cache 201 and the bus line 216; and a register scoreboard circuit 218 connected to the instruction issuing unit 202 are incorporated. These will be described in detail below.

First, the trap and stall control processing in the third embodiment will be described.

In general, a parallel processing type processor system has a mechanism for avoiding the occurrence of conflicting requests for the same resource during execution of a machine language instruction, and retains the correctness of the execution order between machine language instructions. You need to have a mechanism. Here, the validity of the execution order means the consistency of the data dependency and the control dependency.

In order to maintain the consistency of the data dependency, the execution order is changed from D → S relation, S → D relation, and D → D relation.
→ It is necessary to maintain one of the D relationships. Where D
The → S relationship indicates that the resource storing the result of the instruction to be executed first is the same as the resource from which the source data used for the instruction to be executed later is read. S →
The D relation indicates that the resource for storing the result of the instruction to be executed first is the same as the resource for storing the result of the instruction to be executed later. The D → D relationship indicates that the resource from which the source data used for the instruction to be executed first is read is the same as the resource from which the source data used for the instruction to be executed later is read. In the third embodiment shown in FIG. 7, the data storage resources exist in two forms, the register and the memory, and it is necessary to maintain the consistency of the data dependency between them.

The control dependency is a relationship between a previous branch instruction and a subsequent instruction. For a branch instruction in a conventional VLIW processor, the consistency of the control dependency is maintained by a compiler. However, in the parallel processing type processor system of the third embodiment, since it is necessary to provide object compatibility of the user program, it is necessary to realize the consistency of the control dependency relationship by hardware.

In the third embodiment, the processor system fetches four instructions of a four-word boundary at the same time, and issues instructions which can be issued simultaneously in an in-order order among the four instructions to each arithmetic unit. hand,
Instruction execution is completed in an in-order order.

In the third embodiment, the hardware for avoiding the occurrence of conflicting requests using the same resources and maintaining the consistency of the data dependency and the control dependency includes two mechanisms. In. The first part is an instruction issuing mechanism implemented by the instruction issuing unit 202, and the second part is the control unit 211.
This is a stall mechanism realized by:

To implement the instruction issuance mechanism, the instruction issuance unit 202 is provided with a predecoder 217 for detecting occurrence of conflicting requests using the same resource, which is used when refilling the cache. (Or instruction fetch for cache-through instruction fetch)
Resources used for the four instructions fetched at the same time,
The instruction having the lowest address among the instructions fetched at the same time is marked as having a conflict. The instruction issuing unit 202 also has a D → S relation and a D →
Register scoreboard circuit 21 for detecting D relationship
8 to avoid conflicts marked by the predecoder 217,
By maintaining the D → S and D → D relationships in the data dependency and the control dependency detected by step 8, the instruction issuance processing in the D stage can be performed in an in-order order. The S → D relationship is maintained by reading out the source register and issuing instructions in an in-order order and completing the execution in the in-order order.

Furthermore, in the third embodiment, since two memory access instructions can be executed at the same time, the consistency of the memory resource competition as well as the data dependency of the memory resource is maintained. There is a need. Since the instruction issuing unit 202 performs processing before the D stage, the instruction issuing unit 202 performs processing on the assumption that these relationships do not exist, and it is possible to accurately confirm whether or not these relationships exist. Can not. The existence of these relationships cannot be determined exactly until the M stage, and although it is possible to determine the possibility of the existence of the relationship, the instruction supply process is over-controlled based on such a possibility. Doing so will severely limit performance.

In the stall mechanism, execution completion is kept in an in-order order, and control is performed in cases other than those already considered by the instruction issuing mechanism and when the instruction issuing processing is too fast to keep up with the instruction fetch processing. I do.

In the execution completion in the in-order order, the execution completion of the instruction based on the basic principle that the instructions issued simultaneously from the D stage are completed simultaneously is achieved. However, if the memory access processing by the memory access instruction X executed in the M stage by the ALU 1204 cannot be completed within one cycle time, the second
As in the embodiment, regardless of the stall request by the instruction X, the execution of the instruction having the address smaller than that of the memory access instruction X is completed, and the number of the mpc equal to the number of the executed instruction is completed.
Is updated. This function is called a group function in the execution completion stage. In the third embodiment, ALU02
03 and the ALU 1204 simultaneously execute an instruction, the instruction issuing unit 202 performs control such that the ALU 0203 always executes an instruction having a smaller address.
In-order execution completion is guaranteed. The control by the instruction issuing unit 202 can prevent a deadlock in the M stage due to a conflicting request regarding the use of memory resources that cannot be detected in the D stage.

The control for completing the pipeline processing only for an instruction having an address smaller than the instruction issuing the stall request is performed in other situations, for example,
The same applies when the M-stage processing in the ALU0203 cannot be completed in one cycle, or when a stall request is asserted because the possibility of trapping an instruction executed in the E2 stage of the FADD207 or FMUL208 cannot be denied. It is possible to apply to.

The instruction issuing unit 202 does not consider the occurrence of competing requests for the use of the same resource or the data dependency as far as the memory (including the cache memory) is concerned. The processor system of the third embodiment is
Like the RISC, it employs a so-called "load, store" architecture, so to avoid conflicting requests for the use of the same resources and to ensure that data dependencies are maintained, "load" and "store" It is sufficient to consider only the instructions. ALU0203 for D-cache 206
There is a dedicated port for ALU1204 and ALU1203.
And as long as only one of the ALUs 1204 is accessing the D-cache 206, no resource contention occurs. Therefore,
When the "load" and "store" instructions access the external memory simultaneously, a data dependency will exist only if the two instructions are trying to access the same address.

The memory resource conflict is solved by the instruction group function in the execution completion stage. Data dependencies for the memory include “read after write”, “write after read”, and “write after write”, and the consistency is maintained on the cache memory side.

Next, the stall control in the third embodiment of FIG. 7 will be described in detail with reference to FIGS.

In the third embodiment, the case where a stall occurs can be summarized as follows.

M0busy M1busy Imis (I-cache miss) FRbusy (FPUFA register write conflict) FAexch (FADD exception check) FMexch (FMUL exception check) FDexch (FMUL exception check) Fstall (forced stall) The conditions under which the stall request signal is asserted are as follows.

M0busy, M1busy: These types of stall request signals correspond to memory access processing (cache and I
/ O) is performed in the Mth stage in the t th cycle, and this memory access
Asserted when it cannot complete during the tth cycle.

Imis: This type of stall request signal is:
Asserted when there is a new instruction fetch request but the instruction fetch is unsuccessful. FIGS. 8 to 12 show an example in which a stall is caused by the Imis stall request. Here, the Imis stall request signal is actually asserted when the instruction is not fetched into the instruction register one clock cycle after fpc is loaded with a new value and "fpcen" is asserted.

FIG. 8 shows a case where a stall occurs due to an instruction cache miss during instruction fetch.

FIG. 9 shows that after a stall due to an instruction cache miss at the time of instruction fetch, another stall request occurs in another part of the system, and the stall due to the instruction cache miss precedes another stall in another part. FIG.

FIG. 10 shows a case in which a stall due to an instruction cache miss occurs simultaneously with another stall in another part of the system, and another stall in the other part is resolved earlier than a stall due to the instruction cache miss. Is shown.

FIG. 11 shows a case where a stall due to an instruction cache miss at the time of instruction fetch occurs at a jump destination of a jump instruction.

FIG. 12 shows a case where a jump occurs during a cache refill operation associated with a stall due to an instruction cache miss.

FRbusy: This type of stall request signal is generated when the FDIV 209 is in the E2 stage of the pipeline and
UL208 is also asserted when in this E2 stage, FD
By stalling pipeline processing other than IV for one cycle, contention of writing to the floating-point register file 213 between the FMUL 208 and the FDIV 209 is avoided.

FAexch: In the E1 stage of FADD207, when the possibility of trap occurrence cannot be denied, FADD2
The pipeline processing at 07 changes from the normal F1 type to the F2 type. In this case, the execution end stage in FADD207 is M
This FAexch stall request signal is used to delay the execution completion stage of other units during the E2 and E3 stages of FADD207 so that all units reach the execution completion stage at the same time as the M stage of FADD207. Stall the processing of other units by asserting. FIG. 13 shows a situation in which a stall occurs due to such a FAexch stall request signal. Here, the processing of the “Iadd” and “fmul” instructions fetched simultaneously with the “fadd” instruction and the fetch in the next cycle are performed. The processing of the "fadd", "Iadd" and "fmul" instructions is stalled between the E2 and E3 stages of the processing of the "fadd" instruction.

FMexch: In the E1 stage of FMUL 208, if the possibility of trap occurrence cannot be denied, FMUL2
The pipeline processing at 08 changes from the normal F1 type to the F2 type. In this case, the execution completion stage in the FMUL 208 becomes the M stage, so that the execution completion stage of the other units is delayed by two cycles, and
In order to reach the execution completion stage at the same time as the M stage 8, the processing of other units is stalled by asserting the FMexch stall request signal.

FDexch: In the E1 stage of FDIV209, if the possibility of occurrence of a trap cannot be denied, FDIV2
The pipeline processing at 09 changes from the normal D1 type to the D2 type. In this case, the execution completion stage of the FDIV 209 becomes the M stage, so the execution completion stage of the other units is changed to the M stage.
Stall the processing of other units by asserting this FDexch stall request signal to delay until the FDIV 209 has passed the E3 stage so that all units reach the execution complete stage at the same time as the M stage of the FDIV 209. . FIG. 14 shows a case where a stall occurs due to such an FDexch stall request signal, and the instruction “iad” fetched simultaneously with the “fdiv” instruction
The processing of “d” and “fadd” is stalled until the instruction “fdiv” passes through the E3 stage.

Fstall: This type of stall request signal is externally asserted before the execution completion stage to lock all pipeline processing except for processing such as cache miss recovery.

FIGS. 15 to 17 show examples of timing charts of stall control in the third embodiment.

In the timing chart of FIG.
In the Nth cycle, a cache miss is detected in the M stage of ALU0 203, and the M0busy signal is asserted, while the cache miss recovery process starts. On the other hand, since the possibility of occurrence of a trap cannot be denied for FMUL 208, the FMexch signal is asserted and stall1
The signal and stall2 signal are asserted. .

In the (N + 2) th cycle, ALU020
While the cache miss recovery process continues for FM3, the FMexch signal is negated because FMUL 208 did not generate an exception. However, execution of FMUL 208 cannot be completed because the stall1 and stall2 signals are still asserted.

In the N + 4th cycle, ALU020
The M0busy signal is negated because the cache miss recovery process for 3 can be completed during this cycle. Therefore, the stall1 signal and the stall2 signal are negated, so that execution in all other units can be completed.

Finally, in the (N + 5) th cycle, the execution of all instructions has been completed.

In the timing chart of FIG.
The address of the instruction in each processing unit is ALU0203 <AL
It is assumed that U1204 and FMUL208 <ALU1204 <FADD207. In this case, a cache miss is detected in the M stage of the ALU 1204 in the Nth cycle, and the M1busy signal is asserted, while the cache miss recovery process starts. On the other hand, since the possibility of trap occurrence cannot be denied for FMUL 208, FMexch
The signal is asserted, and the stall1 and stall2 signals are asserted.

In the (N + 2) th cycle, ALU120
While the cache miss recovery process continues for FM4, the FMexch signal is negated because FMUL 208 did not cause an exception. At this point, the stall2 signal is negated and the execution in ALU0203 and FMUL208 can be completed, but the stall1 signal is still asserted,
Execution of DD 207 cannot be completed.

In the N + 4th cycle, ALU120
Since the cache miss recovery process for 4 can be completed during this cycle, the M1busy signal is negated. Therefore, the stall1 signal is negated, so that the FADD207
Can be completed.

Finally, in the (N + 5) th cycle, all instructions have been executed.

In the timing chart of FIG.
In the Nth cycle, a cache miss is detected at the M stage of the ALU 1204, and while the M1busy signal is asserted, the cache miss recovery process starts.
On the other hand, since the possibility of trap occurrence cannot be denied for the FMUL 208, the FMexch signal is asserted, and the stall1 signal and the stall2 signal are asserted.

In the (N + 2) th cycle, ALU 120
4, the cache miss recovery process is completed, and M1bu
The sy signal is negated, and the FMexch signal is negated in the same N + 2th cycle or the previous N + 1th cycle because FMUL 208 did not raise an exception.
At this point, the stall1 signal and the stall2 signal are also negated, so that execution of all instructions can be completed.

In the third embodiment, the stall1 signal, stal
The table shown in FIG. 18 summarizes the processing of each pipeline in each processing stage according to the stall control processing using the l2 signal and the FRbusy signal.

In the third embodiment, after the processing of an instruction is stalled on the assumption that the possibility of occurrence of an exception cannot be denied in the execution of the instruction, the processing of the instruction is stopped when the exception actually occurs during the execution of the instruction. The instruction is aborted or otherwise returned when no exception actually occurred in the execution of the instruction. In FIG. 18, BU indicates a branch unit provided in each processing unit of the processor system.

Therefore, according to the third embodiment, a parallel processing such as a super scalar processor incorporating a trap and stall control function capable of processing without increasing the cycle time so as to prevent a decrease in the clock frequency of the system is prevented. It is possible to provide a type processor system.

[0108]

As described above, the parallel processing computer of the present invention is capable of high-speed trap and stall control processing without increasing the cycle time. In a processor system, trap and stall control can be performed more efficiently without lowering the system clock frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a parallel processing type processor system according to the present invention.

FIG. 2 is a block diagram of a trap control unit in the parallel processing type processor system of FIG. 1;

FIG. 3 is a diagram showing the progress of pipeline processing in the parallel processing type processor system of FIG. 1 when a trap request occurs during execution of the program of FIG. 21;

FIG. 4 is a block diagram of a second embodiment of the parallel processing type processor system according to the present invention.

FIG. 5 is a diagram illustrating an example of a program executed by the parallel processing type processor system of FIG. 4;

6 is a diagram showing a progress state of pipeline processing in the parallel processing type processor system of FIG. 4 when a trap request occurs during execution of the program of FIG. 5;

FIG. 7 is a block diagram of a third embodiment of a parallel processing type processor system according to the present invention.

8 is a diagram illustrating an example of a stall due to an instruction cache miss in the parallel processing type processor system of FIG. 7;

9 is a timing chart showing another example of a stall due to an instruction cache miss in the parallel processing type processor system of FIG. 7;

10 is a timing chart showing another example of a stall due to an instruction cache miss in the parallel processing type processor system of FIG. 7;

11 is a timing chart showing another example of a stall due to an instruction cache miss in the parallel processing type processor system of FIG. 7;

12 is a timing chart showing another example of a stall due to an instruction cache miss in the parallel processing type processor system of FIG. 7;

13 is a timing chart showing an example of a stall by FAexch in the parallel processing type processor system of FIG. 7;

14 is a timing chart showing an example of a stall by FDexch in the parallel processing type processor system of FIG. 7;

FIG. 15 is a timing chart showing an example of a stall control process in the parallel processing type processor system of FIG. 7;

FIG. 16 is a timing chart showing another example of the stall control process in the parallel processing type processor system of FIG. 7;

FIG. 17 is a timing chart showing another example of the stall control process in the parallel processing type processor system of FIG. 7;

18 is a table summarizing the processing modes of each pipeline for stall control processing in the parallel processing type processor system of FIG. 7;

FIG. 19 is a block diagram of a parallel processing type processor system using a conventional trap control method.

20 is a block diagram of a trap control unit in the conventional parallel processing processor system of FIG.

FIG. 21 is a diagram illustrating an example of a program executed by the parallel processing type processor system.

22 is a diagram showing the progress of pipeline processing in the parallel processing type processor system of FIG. 19 when a trap request occurs during execution of the program of FIG. 21.

[Explanation of symbols]

 101 Instruction Memory 101A Instruction Cache Memory 102 Instruction Issuing Unit 102A Instruction Issuing Unit 103 Arithmetic and Logic Operation Unit 104 Arithmetic and Logic Operation Unit 105 Floating Point Adder 106 Floating Point Multiplier 107 Memory Access Unit 108 Memory Access Unit 109 Floating Point Exception Check Unit 110 Floating point exception check unit 111 Multi-port register file 125 2-port data memory 125A 2-port data cache memory 130 Trap cause register 131 Abort address register 132 Trap address register 133 Trap control unit 151 M stage program counter 1 152 M stage program counter 2 153 M stage subprogram counter 1 4 M stage subprogram counter 155 M stage subprogram counter 156 M stage subprogram counter 157 Trap data generation unit 158 Trap signal generation unit 160 Bus line 161 Main memory 162 I / O device 163 Stall control unit 201 Instruction cache memory 202 Instruction issuance Unit 203 Arithmetic / Logic Operation Unit 204 Arithmetic / Logic Operation Unit 205 Integer Multiplier / Divider 206 2-Port Data Cache Memory 207 Floating Point Adder 208 Floating Point Multiplier 209 Floating Point Divider 210 Instruction Address Generation Unit 211 Control Unit 212 Integer Register File 213 Floating point register file 214 Main memory 215 I / O device 216 Bus line 217 Re-decoder 218 Register scoreboard circuit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Joji Takeda 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Research Institute, Ltd. (56) References JP-A-4-247523 (JP, A) JP-A Heisei 4-218841 (JP, A) JP-A-5-53806 (JP, A) JP-A-5-20070 (JP, A) JP-A-4-353929 (JP, A) JP-A-4-308930 (JP, A) A) Japanese Patent Application Laid-Open No. 4-308929 (JP, A) Tetsuya Hara, et al., "Configuration and Processing of Improved Superscalar Processor Based on SIMP (Single Instruction Flow / Multiple Pipeline)", Electronic Information Communication Technical Report of the Society, Vol. 90, no. 144, The Institute of Electronics, Information and Communication Engineers, July 20, 1990, p. 103-108 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 9/38

Claims (7)

(57) [Claims] 1. A method for simultaneously executing a plurality of sequences of instructions.
(N is a positive integer) instruction execution means, instruction supply means for supplying instructions simultaneously executed by the N instruction execution means, and M (N ≧ M, M is a positive integer) instructions The instruction supply means simultaneously supplies the instruction execution means to the N instruction execution means, and when a processing exception occurs in the execution of at least one of the M instructions in one clock cycle, the N instruction execution is performed in the one clock cycle. Sending the abort signal to all of the N instruction execution means so that the simultaneous processing of the M instructions supplied to the N instruction execution means is aborted in the one clock cycle. An instruction level parallel processing type processor system, comprising: trap control means for controlling execution means. 2. An abort address storage means for storing an address of an instruction having the smallest address among the M instructions whose processing has been aborted by said trap control means; and said processing among said M instructions. 2. The instruction level parallel processing type processor system according to claim 1, further comprising: trap address storage means for storing an address of an instruction which caused the exception. 3. The method according to claim 1, wherein the N instruction executing means includes K instructions (M ≧ M).
K, where K is an integer) ordered arithmetic means having equivalent functions, wherein the instruction supply means is J pieces (K ≧ J> 1,
(J is an integer) so that the instructions in the J instructions earlier in the order are provided to the arithmetic means earlier in the K arithmetic means. The instruction level parallel processing type processor system according to claim 1, wherein said processor is supplied to said K arithmetic means. 4. When the possibility of occurrence of a processing exception in the execution of the I-th instruction among the J instructions cannot be denied, the latter of the J instructions after the I-th instruction. So as to stall the processing of instructions in order.
Stall means to stall part of the processing of the instructions
The instruction level parallel processing type processor system according to claim 3, further comprising: 5. When not be ruled out the possibility that the processing exception occurs in the execution of the M instruction, the M
And further execution after the execution of the M instructions.
That process stalls, said upon the occurrence of M processing <br/> management exception actually when an instruction has been executed, the M number of instruction execution of
Abort further processing after line and execute the M instructions
2. The instruction-level parallel processor according to claim 1, further comprising: a stall control unit that restarts further processing after the execution of the M instructions when a processing exception does not actually occur. Processing type processor system. 6. A means for handling the processing exception, and means for simultaneously restarting the M instructions aborted by the trap control means after handling the processing exception. The instruction level parallel processing type processor system according to claim 1, wherein 7. A method for controlling an instruction level parallel processing type processor system, comprising: M (N ≧ M, M) of a plurality of sequences simultaneously executed by N (N is a positive integer) instruction execution means of the system. And M instructions are simultaneously supplied to the N instruction execution means, and are processed in at least one instruction execution of the M instructions in one clock cycle. When an exception occurs, an abort signal is sent to all of the N instruction execution means during the one clock cycle, thereby processing all of the M instructions supplied to the N instruction execution means simultaneously. N so that it aborts during one clock cycle
Controlling a plurality of instruction execution means. A method for controlling an instruction level parallel processing type processor system, comprising: