JPH0855034A - Arithmetic processor and interrupt processing system using the processor - Google Patents

Abstract

PURPOSE:To reduce interruption overheads without complicating hardware configuration even when the number of tasks to be processed is increased. CONSTITUTION:This arithmetic processor 1 is provided with two sets of register groups 3 and 4 for storing a pointer, a status and the other data required for internal operations. When one of the register groups 3 or 4 is accessible from the inside (in use), the other register group 4 or 3 is accessible from the outside (unused) and the two sets of the register groups 3 and 4 are switched corresponding to switching signals SW from the outside. An external processor 2 is provided with a memory 6 for saving the contents of the register groups 3 and 4 in the inside, returns the contents of the register group stored in the memory 6 and required for the task to be activated next to the unused register group 3 or 4 at the time of an interruption processing, then, supplies the switching signals SW to the arithmetic processor 1 and switches the register groups 3 and 4. Then, the contents of the unused register group 4 or 3 after changeover are saved in the memory 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (DSP) for executing multitask processing.
The present invention relates to a suitable arithmetic processor and an interrupt processing system using the same.

[0002]

2. Description of the Related Art A multiple parallel operation for executing a plurality of different applications in a multitask process using a single DSP is executed by a time division multiplex system, and a task is switched by an interrupt process. At that time, saving and restoring the interrupted task and the program counter value of the interrupted task, the status, and the register stored values such as the accumulator is an unavoidable overhead in this kind of operation. Therefore, JP-A-2
-110739 has a plurality of task sets such as program counter values and flags for each task, and by switching between these task sets when switching tasks, interrupt overhead such as saving and restoring register values is reduced. A central processing unit for multitasking is disclosed.

[0003]

However, in the above-described conventional multi-task central processing unit, the number of registers increases in proportion to the number of tasks to be switched and the number of divisions for pipeline processing, which complicates the hardware configuration. To do. The present invention has been made in view of such problems, and an arithmetic processor capable of reducing the interrupt overhead without complicating the hardware configuration even if the number of tasks to be processed increases. An object is to provide an interrupt processing system using this.

[0004]

The arithmetic processor according to the present invention is a program storage means for storing a program, a data storage means for storing data, and a control for controlling each part according to the program stored in the program storage means. Means, arithmetic means for performing predetermined arithmetic processing on the data stored in the data storage means under the control of the control means, and a group of registers for storing pointers, status and other data necessary for the operation of these respective parts. In the arithmetic processor provided, the register group is made up of two sets of register groups of the same configuration, one of which is connected to each of the units so that it can be accessed from the respective units, and the other of which is connected to the outside from the outside in accordance with an interrupt process. In accordance with a switching signal supplied from the above, a group of registers accessible from each unit and an access from the outside are provided. Characterized by comprising a register switching means for switching the scan capable registers.

Further, the interrupt processing system according to the present invention is provided with two sets of registers for storing pointers, status and other data necessary for internal operation, and one register group is connected so as to be accessible from the inside. , While the other register group is connected to be accessible from outside,
An arithmetic processor having register switching means for switching these two sets of registers in accordance with a switching signal from the outside;
A storage means for saving the contents of the register group is provided inside, and a register group accessible from the outside of the arithmetic processor at the time of interrupt processing is used for a task to be started next stored in the storage means. After the necessary contents of the register group are restored, the switching signal is supplied to the arithmetic processor to switch the register group, and the contents of the register group accessible from the outside after the switching are saved in the storage means. And a control means.

[0006]

According to the present invention, two sets of register groups for storing pointers and the like are provided, and while one register group is being used for internal operation, the other register group is accessible to the outside. Therefore, it is possible to externally access the unused register group for restoration and saving. For this reason, the contents of the register group of the task to be activated next may be restored in advance, or the contents of the register group of the task activated previously may be saved while other tasks are activated. , It is possible to reduce the interrupt overhead associated with task switching. Moreover, according to the present invention, even if the number of tasks increases or the number of divisions of the instruction cycle due to the pipeline processing increases, the number of register groups to be used is sufficient to be two, so that the hardware configuration becomes complicated. There is no such thing.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a multitask system according to an embodiment of the present invention. This system includes an arithmetic processor 1 and an external processor 2. The arithmetic processor 1 is, for example, a signal processor including an arithmetic unit inside such as a DSP, and internally has a program counter, a loop counter, a status register, a write / read pointer, and internal registers such as an arithmetic unit, a memory, and a decoder. Here, these are collectively referred to as a register group. In the arithmetic processor 1 of this system, such a register group has REGA3 and REG.
Two sets of B4 are provided. REGA3 and REGB4
Have the same configuration, and when one is in use and accessible from the inside, the other is unused and connected so that it can be accessed from the outside. These are switched by a switching signal SW from the outside.

The external processor 2 comprises an external controller 5, a memory 6 and an interrupt processing acceptance section 7. The external controller 5 operates in accordance with the interrupt request from the outside received by the interrupt processing reception unit 7
For the task switching, or according to the multiple execution processing program stored in the memory 6, scheduling for task switching and interrupt processing. At the time of interrupt processing, the external controller 5 uses the unused register group (R
The register value stored in the EGA 3 or REGB 4) is stored in the memory 6, and the register value of the task to be activated next is read from the memory 6 and the unused register group (RE
It is stored in GA3 or REGB4). Interrupt processing acceptance section 7
Is composed of an analog and digital interface such as RS-232C and SCSI, a data reception buffer and the like, and receives an interrupt request from an external device.

FIG. 2 is a detailed block diagram showing an example of the arithmetic processor 1. The internal bus 11 has a program memory 12 for storing an arithmetic processing program and a data memory 13 for storing coefficients and signal data necessary for arithmetic processing.
Are connected to a multiplier 14 and an arithmetic logic unit (ALU) 15 that form an arithmetic unit. The instruction codes stored in the program memory 12 are read one by one by the program counter (PC) 16, stored in the instruction register (IR) 17, and then supplied to the decoder 18 for decoding. As a result, each unit is controlled by the control signal. Data memory 1
The read address and the write address of No. 3 are designated by the read pointer (RP) 19 and the write pointer (WP) 20, respectively.

Data such as a coefficient given to the multiplier 14 is read from the data memory 13 and stored in the multiplication register (MR) 21 via the internal bus 11. The stored data and the operand supplied from the program memory 12 via the internal bus 11 are multiplexed by the multiplexer (M
UX) 22 and is selectively supplied to one of the multipliers 14, and signal processing data and the like are supplied to the other of the multipliers 14. One of the output of the multiplier 14 and the data provided via the internal bus 11 is selected by the multiplexer (MUX) 23 and provided as one input of the ALU 15, and the output of the ALU 15 or the internal bus 1
The data on 1 is provided as the other input of ALU 15. The output of ALU15 is the accumulator (ACC) 2
Stored in 4. The status information determined by the calculation result of the ALU 15 is the status register (SR) 2
Stored in 5. The number of times of loop processing is held in the loop counter (LC) 26. In addition, the arithmetic processor 1 is provided with an auxiliary register 27 and an auxiliary register dedicated arithmetic unit (ARAU) 28. Further, the stack 29 stores the value of the program counter when branch processing or the like occurs in the same task.

In the above configuration, the program counter 16, read pointer 19, write pointer 20, multiplication register 21, accumulator, status register 2
5, the loop counter 26, the holding register 27, the stack 29, and the like hold the contents that must be saved and restored when switching tasks. The arithmetic processor 1 is provided with two sets of these respective register groups, which are switched by the switching signal SW.

FIG. 3 is a diagram showing a concrete configuration example of one set of registers among these register groups and switching means therefor. The registers 31 and 32 are one of a group of registers such as the program counter 16 described above, and selection circuits 33, 34, 35 and 36 are provided on the input end side and the output end side thereof, respectively. The selection circuit 33 selects which of the registers 31 and 32 to output the data from the inside, and the selection circuit 34 selects which of the registers 31 and 32 to output the data from the outside. The selection circuit 35 selects which of the registers 31 and 32 to output the data to inside, and the selection circuit 36 selects which of the registers 31 and 32 to output the data to outside. The inverter 37 inverts the control signal supplied to the selection circuits 33 and 35 and the control signal supplied to the selection circuits 34 and 36. When the switching signal SW is "0", the control signal supplied to the selection circuits 33 and 35 is "1" and the control signal supplied to the selection circuits 34 and 35 is "0". From the outside, and the register 32 can be accessed from the outside. When the switching signal SW is "1", the control signal supplied to the selection circuits 33 and 35 is "0", and the control signal supplied to the selection circuits 34 and 35 is "1". And the register 31 can be accessed from the outside.

In the system described above, the possible states of the activated task are as follows, for example, as shown in FIG.
There are four types, RUN, WAIT, READY, and SUSPEND. The RUN makes a transition to WAIT when it waits for an event from this state while the task is executing. READY is a state in which the task can transit to the execution state at any time in the standby state. This state can also be entered when the event wait is completed from WAIT. SUSP
END is a state in which the task is stopped, and it is not possible to immediately shift from this state to the execution state. This state is also transitioned to when it is forcibly canceled from READY and WAIT.

FIG. 5 is a flow chart showing an outline of processing executed by the external controller 5 when an event occurs. When an event from an external interrupt or multiple execution process occurs, the external controller 5 activates this process and first refers to the internal execution queue etc. and the status of all tasks (WAIT, READY, etc.). To determine the priority order of all tasks (S1). Next, it is determined whether or not the event that has occurred requires switching of tasks (S
2) If the task switching is not necessary, the process is terminated. If the task switching is necessary, the contents of the register of the task to be activated next is read from the memory 6 and set in an unused register group (REGA3 or REGB4). Write it (S
3). Then, the timing of task switching is determined (S
4) Simultaneously with the task switching, the switching signal SW is inverted to switch the register group (S5). Finally, the contents of the newly unused register group are stored in a predetermined storage location of the memory 6. As a result, the arithmetic processor 1 can instantly switch the tasks, and does not need to detect even the switching of the tasks.

In the above processing, the contents of the next task are restored to the unused register group, and then the task switching is executed, and the contents of the newly unused register group are stored in the external memory. Although it was saved, the contents of the unused register group are saved to the external memory before the task switching,
The contents of the register group of the task to be activated next may be restored from the external memory to switch the task. Also, the external controller 5 determines whether the task to be switched next is the previously activated task, and if it is the previously activated task, destroys the contents of the previous register group in the unused register group. The register group may be switched immediately without performing the operation of returning from the memory because it remains without being restored.

[0016]

As described above, according to the present invention,
Two sets of registers that store pointers and the like are provided, and while one register group is being used for internal operation, the other unused register group is accessed for restoration and saving from the outside. Since it is possible to restore the contents of the register group of the task to be started next,
By performing processing such as saving the contents of the register group of the task that was previously activated during activation by another task, it is possible to reduce the interrupt overhead associated with task switching. Moreover, according to the present invention, even if the number of tasks increases or the number of divisions of the instruction cycle due to the pipeline processing increases, the number of register groups to be used is sufficient to be two, so that the hardware configuration becomes complicated. It has the effect of never happening.

[Brief description of drawings]

FIG. 1 is a block diagram of a multitasking system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing contents of an arithmetic processor in the system.

FIG. 3 is a block diagram showing a configuration of each register and its switching means in the arithmetic processor.

FIG. 4 is a state transition diagram for explaining a state of a task activated in the system.

FIG. 5 is a flowchart showing interrupt processing when an event occurs in the system.

[Explanation of symbols]

1 ... Arithmetic processor, 2 ... External processor, 3, 4 ... Register group, 5 ... External controller, 6 ... Memory, 7 ... Interrupt processing acceptance unit.

[Procedure amendment]

[Submission date] August 18, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (2)

[Claims] 1. A program storage means for storing a program, a data storage means for storing data, a control means for controlling each part according to the program stored in the program storage means, and the data controlled by the control means. In an arithmetic processor provided with arithmetic means for performing a predetermined arithmetic processing on data stored in the storage means, and a register group for storing pointers, status and other data necessary for the operation of each of these parts, wherein the register group is One of the groups is composed of two sets of registers of the same configuration, one of which is connected to be accessible from each section and the other of which is accessible from the outside. Register switching for switching between accessible register groups and externally accessible register groups An arithmetic processor comprising a conversion means. 2. A set of two registers for storing pointers, statuses and other data necessary for internal operation is provided, one register group is connected to be accessible from the inside, and the other register group is accessible from the outside. And an arithmetic processor provided with register switching means for switching these two sets of register groups in accordance with a switching signal from the outside, and a storage means for internally saving the contents of the register groups. Further, after the contents of the register group necessary for the task to be activated next stored in the storage means are restored to the register group accessible from the outside of the arithmetic processor, the switching signal is supplied to the arithmetic processor. Then, the register group is switched, and the contents of the register group accessible from the outside after switching are stored in the memory. Interrupt processing system characterized by comprising an external control means for saving the.