JPH02110739A - Central processing unit for multi-task - Google Patents

Abstract

PURPOSE:To decrease the loss of a time due to an interrupting processing when the multi-task processing is carried out by switching so that a task set corresponding to the task in which a CPU is presently executed can be selected by a task register and can be operated based on an arithmetic unit. CONSTITUTION:A task set 7a is composed of a program counter 1a, an accumulator 2a, a register 3a and a flag register 4a, the same number of the task sets 7a as the program is prepared and at the time of executing one program, one set is used. Each time three programs A to C are switched for a certain constant time and for a T time, task sets 7a to 7c corresponding to respective programs A to C are selected by a task register 5, switching is executed so as to operate based on the arithmetic unit and the action is repeated until respective programs are completed. Thus, at the time of being the multi-task processing, the time loss at the time of changing the program can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a multitasking central processing unit that executes a plurality of programs by one arithmetic unit at apparently higher speeds.

"Conventional technology" Conventionally, a time division method (
time sharing system). This is a method in which the execution time of the central processing unit (CPU) is divided into small parts, and multiple programs are executed in sequence little by little, so that the execution time is apparently exceeded.

FIGS. 3(a) and 3(b) are a conceptual diagram of a program structure in a conventional main storage device and a conceptual diagram of program execution, respectively.

First, upon execution of the program, a task set consisting of a progera l-counter, an accumulator, a register, and a flag register in the CPU is initialized. This initialization sets the program counter to n. Then, CP
Program A is n by U. Executed from address (3rd
(See figure (b)).

Then, one hour later, an interrupt is automatically applied to the cPU at time P1. In this case, the CPU executes to the end the instruction that was in the middle of execution when the interrupt occurred. Next, the CPU performs processing necessary for multitasking. That is, first, the contents of the task set are saved to a predetermined area within the main memory.

Then, if program B was previously executed,
The contents of the task set necessary for executing program B are read from a predetermined area in the main memory.

Here, since program B has never been executed, the program counter indicates the start address of program I3, and program B is executed from address n3. Then, one hour later, the CPU is again interrupted at time P2, and the contents of the program counter are saved to a predetermined area in the main storage device, as in the case of the previous interruption.

Also, each content of the task set for program C is
It is returned to the predetermined area of the PU (see FIG. 3 (b)).

After completing the above interrupt processing, the CPU executes program C from address n8 in the same way as program B.

Then, when an interrupt occurs again at time P3, the CPU
interrupt processing is executed. In this case, since program Δ has already been executed once, program A
The contents of the task set saved in the previous interrupt processing are read and returned to a predetermined area within the CPU. At this time, since the program counter indicates the address next to the address that ended last time, for example, address 01, program A is executed from address n1 following the last time. Then, one hour later, at time P4, the CPU is again interrupted, and the CPU performs the interrupt processing. Through this process, as in Section 2, the contents of the previously saved task set corresponding to program B are restored, and program B is executed by the CPU from address 04 (Figure 3 (a)).
reference).

As described above, execution of programs by the CPU, hourly interrupts, and interrupt processing are repeated until each program A to C is completed.

``Problem to be solved by the invention'' By the way, in the conventional multitasking method described above, interrupt processing is performed every time the program executed by the CPU is changed, resulting in time loss, and the apparent problem is that the upper CPU There was a problem that the execution speed was slow.

The present invention was made in view of the problems mentioned above, and an object of the present invention is to provide a central processing unit for multitasking that reduces time loss due to interrupt processing during multitasking and does not reduce the execution speed of the CPU. It is said that

"Means for Solving the Problem" In order to solve these problems, the present invention provides a program counter, an accumulator, a flag register representing the state of the operation result, and temporary storage of data necessary for the operation. Provide multiple task sets with registers,
The present invention is characterized by comprising a task register that indicates a currently executing task and selects the task set corresponding to the task.

"Operation" The task register indicates which task is currently being executed by the CPU, and the task set consisting of the program counter, accumulator, register, and flag register corresponding to this task is selected by the task register, and the task register is used to control the processing unit. A switch is made to operate as usual.

"Embodiments" Examples of the present invention will be described with reference to the following drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, 1a is a program counter,
2a is an accumulator, and 3a is a register for assisting the accumulator 2a, which temporarily stores data used in calculations, data indicating addresses of the main storage device, and calculation results. 4a is a flag register representing the state of the operation result of the accumulator 2a. These program counter la, accumulator 2 a % register 3 a, and flag register 4 a constitute a task set 7 a. The same number of task sets 7a as programs are prepared, and one set is used when one program is executed. In this embodiment, three programs A, B, and C are to be executed (see FIG. 2(a)), and task sets 7a, 7b, and 7c are prepared for each program. Reference numeral 5 denotes a task register that indicates a task currently being executed by the CPU and selects a task set corresponding to the program of that task. A selection signal SEL is supplied from the task register 5 to each set of program counter, accumulator, register, and flag register in order to select one task set. Further, 6 is an internal data bus within the CPU for transmitting and receiving data between each of the task sets 7a, 7b, and 7c and the arithmetic unit.

Next, the operation of this embodiment with the above configuration will be explained.

First, upon execution of the program, task sets 7a, 7b, 7c and task register 5 in the CPU are initialized. In this initialization, the task set 7a is selected by the task register 5, and the CPU operates based on the contents of this task set 7a. That is, the program counter 1a is initialized to n. Since the addresses where the instructions are stored are sequentially specified from the beginning, program A is n. Executed from address. Accumulator 2 is used for temporary storage of data and calculation results during execution, display of flags, etc.
a, register 3a and flag register 4a are used. One hour later, the CPU is interrupted at time P5, and the task register 5 selects task set 7b. Further, the contents of each of the tasks 1-7a that have been selected so far are held at the time of the interrupt, for example, Adr, n, in the program counter 1a until they are selected again.

Next, in the newly selected group B, like the group A, the program counter 1b sequentially indicates the addresses where instructions are stored starting from the start address of program B, so program B is executed from address 03. . In addition, an accumulator 2 is used for temporary storage of data being executed and calculation results.
b, register 3b and flag register 4b are used. Then, one hour later, the CPU is again interrupted at time P6, and the task register 5 selects task SEF l-7c. In addition, the contents of each task set 7b that has been operating under the arithmetic unit until now are the same as the task set h7a until the next selection, for example, the contents of the program counter 1.
Ad r, nt is held in b.

Then, like programs A and B, program C is executed by the CPU from address 08, and an accumulator 2C, a register 3c, and a flag register 4c are used to temporarily store the data being executed and the results of calculations. Then, the CPU is again interrupted at time P7, execution of program C is interrupted, and task set 7a is selected by task register 5. Also, task set 7c
The contents of are held until the next task register 5 is selected.

The program counter 1a of the task set 7a selected by the task register 5 again contains the start address Adr of the program A to be executed next.

n, is retained. Further, the contents of the accumulator 2a, the register 3a, and the flag register 4a at the time when the execution is interrupted are stored, similarly to the program counter 1a. Therefore, program A is executed from address n5, continuing from the previous program. Similarly, when an interrupt occurs, task set 7b is selected by task register 5, and program B is executed from address 04 according to the address held in program counter 2b.

As shown in ``2'' below, each time the three programs Δ, B and C are switched every hour for a certain period of time, the task sets 7a, 7b and 7 corresponding to each program A to C are changed.
c is selected by the task register 5, and switching is performed to operate under the arithmetic unit. This operation is repeated until each program is finished.

"Effects of the Invention" As explained above, according to the present invention, when performing multi-task processing, it is possible to reduce time loss when changing programs, and to
This provides the advantage of being able to efficiently execute programs without reducing the execution speed of the PU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
Figures 2 (a) and (b) are a conceptual diagram of the program structure in the main memory and a conceptual diagram of program execution, and Figure 3 (
(a) and (b) are a conceptual diagram of a program configuration in a conventional main storage device and a conceptual diagram of program execution, respectively. 1a~IC...Program counter, 2a~2
C...Accumulator, 3a-3c...
・Registers, 4a to 4C...Flag register, 5
...Task register, 6...CPU internal data bus, 7a to 7C...Task set, SEL...
...Selection signal.

Claims (1)

[Claims] A plurality of task sets each having a program counter, an accumulator, a flag register representing the state of the operation result, and a register for temporarily storing data necessary for the operation are provided to indicate the currently executing task and correspond to the task. A multitasking central processing unit comprising: a task register for selecting the task set.