JPH0821027B2 - Microcomputer with built-in A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention converts an analog input signal into a digital value.
The present invention relates to a microcomputer including an A / D conversion device.

[Conventional technology]

Nowadays, microcomputers have been highly integrated due to the progress of LSI technology, and various kinds of peripheral hardware have been mounted on one chip.

Among them, the A / D converter is indispensable in fields such as automobile control and AC servo control, and the demand for a microcomputer with a built-in A / D converter is extremely high. The conventional technique will be described below with reference to FIG.

The microcomputer 060 is a central processing unit (hereinafter CPU
080), an A / D conversion device 600, and an internal bus 090 for exchanging data between the CPU 080 and the A / D conversion device 600.

The CPU 080 performs a read / write operation of data with respect to the A / D conversion device 600 by executing a program, and also performs a process of receiving an interrupt signal 170 from the A / D conversion device.

The A / D converter 600 is an analog multiplexer (hereinafter abbreviated as multiplexer) that selects one of the signals from the input terminals 110 to 117 and the input terminals 110 to 117 for inputting an analog signal and transmits it to the A / D converter. ) 120, A / D converter 130 for A / D converting the output signal of the multiplexer 120, A / D conversion result storage register (hereinafter abbreviated as register) 140 to 147 for storing the conversion result of the A / D converter 130, A / D conversion operation control unit (hereinafter abbreviated as operation control unit) 650 that controls the operation of A / D conversion, interrupt signal line for requesting interrupt processing to CPU080 when a predetermined A / D conversion operation is completed 170, input terminal designation signal line 19 that designates the input terminal selected for the multiplexer 120
0, address specification signal line 195 for selecting one of registers 140 to 147, operation specification register 1 for controlling operation specification of A / D conversion
51, pin specification register 1 that specifies the input terminal to be converted
It consists of 53.

The multiplexer 120 selects the input terminal designated by the operation control unit 650 and transmits the analog input signal to the A / D converter 130.

The A / D converter 130 performs A / D conversion on the analog signal output from the multiplexer 120.

The registers 140 to 147 store the conversion result of the A / D converter 130 in the register designated by the addressing signal line 195 output from the operation control unit 650.

Further, any of the registers 140 to 147 can be read from the CPU 080.

The operation control unit 650 has an operation specification register 151 that specifies an A / D conversion operation, and a terminal specification register 153 that specifies an input terminal to be converted.

The above-mentioned operation designation register 151 and pin designation register 153
Are accessible from the CPU080.

The operation control unit 650 specifies the input signal to be selected for the multiplexer 120 by the operation specifying register 151 and the terminal specifying register 153, and the A / D for the registers 140 to 147.
Specify the register that stores the conversion result.

Next, the relationship between the operation of the A / D converter 600 and the operation control unit 650, the operation designation register 151, and the terminal designation register 153 will be described in detail.

Normally, an A / D converter corresponds to two cases: one analog input terminal continues A / D conversion and a plurality of analog input terminals sequentially A / D converted. It is common to perform two operations.

The operation designation register 151 functions as a register for switching this operation.

(1) When the operation designation register 151 is "0", the A / D converter 600 continues A / D converting the single analog input terminal designated by the terminal designation register 153.

Regarding the correspondence between the value of the terminal designation register 153 and the terminal, the value of the terminal designation register 153 directly corresponds to the terminal number. That is, if the terminal designation register 153 is "5", the input terminal 115,
If the terminal designation register 153 is "7", the input terminal 117 is designated. The A / D conversion result is registered in the register corresponding to the analog input terminal (for example, if the analog input terminal is 110, register 14
0, if the analog input terminal is 115, store it in register 145).

The interrupt signal line 170 is activated (“1”) every time one A / D conversion is completed. This allows registers 140-1
Request to take the A / D conversion result in 47 to CPU080,
The A / D conversion operation is started again and the above operation is repeated.

(2) When the operation designation register 151 is “1”, the A / D conversion device 600 performs the operation of sequentially A / D converting all analog input terminals. In this case, the pin designation register 15
3 is invalid.

Specifically, the A / D converter 600 has an analog input terminal 11
0 is converted, the conversion result is stored in the register 140, then the analog input terminal 111 is converted, the conversion result is stored in the register 141, and the same conversion is performed thereafter.
When the conversion of 117 is completed, the interrupt signal line 170 is activated (“1”).

After that, the A / D conversion operation is started again from the analog input terminal 110 and repeated.

Next, the operation of the entire A / D converter will be described together with the instruction execution of the CPU.

Normally, A / D conversion for various controls is performed by sequentially A / D converting each input terminal and making the latest A / D conversion result of each input terminal normally readable, and A / D conversion of a specific pin may be performed based on the timing of occurrence,
Both are used mixedly.

To explain using this example, the CPU080 first sets each input terminal 110 so that it can read the latest state of the terminal.
"1" is set in the operation designation register 151 in order to sequentially perform the A / D conversion of to 117. By this operation designation, the A / D conversion device 600 can hold the latest A / D conversion values of the input terminals 110 to 117 in the registers 140 to 147.

The A / D converter 600 activates the interrupt signal 170 every eight A / D conversion ends and requests the CPU080 to perform interrupt processing. However, since there is no particular processing required, the interrupt is masked on the CPU080 side. I'll do it. (Not shown in FIG. 5) Next, in order for the CPU080 to know the state of the specific terminal at the time of the subroutine call by the A / D conversion subroutine call while the program is being executed, the CPU080 sets “0” in the operation designation register 151. Is set and the number of the input terminal to be converted is set in the terminal designation register 153, and the A / D conversion device shifts to the operation of A / D converting one analog input terminal.

The A / D converter 600 outputs an interrupt signal 170 every time one conversion is completed.
In this case, the CPU080 does not mask the interrupt, and fetches the A / D conversion result to the CPU080 every time the interrupt signal 170 becomes active (“1”).
After performing the necessary number of A / D conversions, set the operation specification register 151 to "1" again to switch the operation to the A / D conversion of each of the input terminals 110 to 117 described above and mask the interrupt at the same time. To do.

The above operation is executed every time the A / D conversion subroutine call in the program.

[Problems to be Solved by the Invention]

Conventional A / D converters need to switch operations according to CPU instructions when performing both A / D conversion of specific pins and sequential A / D conversion of all pins. Masking and unmasking are required.

Since this operation is attached every time the A / D conversion operation is switched, if the switching of the A / D conversion operation occurs frequently, the number of instruction executions for the operation switching operation described above will increase, and the control of the CPU that should originally execute it will increase. As a result, the ratio of effective processing to the execution of the program is reduced, and the performance of the entire control device is degraded.

[Means for solving the problem]

The present invention provides a central processing unit, a plurality of analog input terminals, an analog input selection means for selecting one of the plurality of analog input terminals, and an analog value of the analog input terminal selected by the analog input selection means. A / D converter that converts to a digital value, multiple A / D conversion result storage registers that store the conversion results of the A / D converter, and one of multiple A / D conversion result storage registers A / D conversion result storage destination specifying means and A / D converter that requests the A / D converter to start A / D conversion
Specify D conversion start request means and conversion operation of A / D converter
Based on the designations of the A / D conversion operation designation register and the A / D conversion operation designation register, by sequentially selecting a plurality of analog input terminals by the analog input selection means, the analog inputs from the plurality of analog input terminals are selected. The operation of sequentially performing A / D conversion by the A / D converter and selectively selecting one of the plurality of analog input terminals by the A / D converter.
It has an A / D conversion operation control means for switching the operation of / D conversion by the A / D conversion activation request means.

Furthermore, according to the present invention, the A / D converter is provided with a plurality of A's that request the start of A / D conversion corresponding to a plurality of analog input terminals.
A / D conversion start request means, and A / D conversion start for selecting one of the plurality of A / D conversion start requests from the plurality of A / D conversion start request means based on a predetermined priority. It has a request judgment means.

Furthermore, in the present invention, the priority designation register rewritable by the central processing unit and the priority designation register for the plurality of A / D conversion requests from the plurality of A / D conversion start request means are designated by the priority designation register. Part 1 based on priority
It has an A / D conversion start request determination means for selecting one of them.

Therefore, after the A / D conversion operation of a specific pin is completed, the A / D conversion operation can be switched by having a function that automatically shifts to the A / D conversion operation of the input pins sequentially without depending on the CPU instruction execution. CPU overhead for can be reduced.

External A / D corresponding to each analog input terminal
With respect to the A / D conversion request for each analog input terminal generated by the conversion request signal line, a request with a higher priority is always issued based on a predetermined priority without depending on the CPU instruction execution. By having the function of accepting and activating A / D conversion, A / D for the input terminal of higher importance is always selected from all the input terminals only by an external request.
The conversion can be performed preferentially.

External A / D corresponding to each analog input terminal
For the A / D conversion request for each analog input terminal generated by the conversion request signal line, the priority can be reprogrammed as needed during execution, and the request with higher priority can be rewritten. With the function to receive and activate A / D conversion, A / D conversion is preferentially executed for all the input pins with high importance specified by the CPU from all input pins, only by an external request. it can.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the present invention in which a microcomputer 010 includes a CPU080, an A / D conversion device 100, and the CPU080 and A.
Internal bus 090 for exchanging data with the A / D converter 100
Consists of

The CPU 080 performs a data read / write operation with respect to the A / D conversion device 100 by executing a program, and also performs a process of receiving an interrupt signal 170 from the A / D conversion device.

The A / D converter 100 includes input terminals 110 to 117 for inputting analog signals, a multiplexer 120, and a multiplexer 1.
A / D converter 130 and A / D converter 13 for A / D converting 20 output signals
Registers 140 to 147 that store the conversion result of 0, an operation control unit 150 that controls the operation of the A / D conversion, and a request to start the A / D conversion
A / D conversion request signal line 160, an interrupt signal line 170 for requesting interrupt processing to the CPU 080 when a predetermined A / D conversion operation is completed, and an input terminal designation for designating an input terminal to be selected for the multiplexer 120 Signal line 190, register 140-
Write "1" to the address signal line 195 that selects one of 147, the operation specification registers 151 and 152 that control A / D conversion, the terminal specification register 153 that specifies the input terminal to be converted, and the operation specification register 152. A write detection circuit (hereinafter abbreviated as a detection circuit) 180 for detecting an operation, and a signal line (hereinafter abbreviated as a converted signal line) 185 indicating that "1" is written in the operation control register 152 are comprised.

 Next, each part of the A / D conversion device 100 will be described.

The multiplexer 120 selects the input terminal designated by the operation control unit 150 and transmits the analog input signal to the A / D converter 130.

The A / D converter 130 performs A / D conversion on the analog signal output from the multiplexer 120.

The registers 140 to 147 store the conversion result in the A / D converter 130 in the register designated by the addressing signal line 195 output from the operation control unit 150.

Further, any of the registers 140 to 147 can be read from the CPU 080.

The operation control unit 150 has two operation specifying registers 151 and 152 for specifying an A / D conversion operation and a terminal specifying register 153 for specifying an input terminal to be converted. The operation specifying registers 151 and 152 and the terminal specifying register 153 are the CPU080. It is accessible from.

The operation control unit 150 specifies the input signal to be selected for the multiplexer 120 by the operation specifying register 151 and the terminal specifying register 153, and specifies the registers for storing the A / D conversion results for the registers 140 to 147.

Further, the A / D conversion request signal line 160 gives the operation control section 150 switching timing of the A / D conversion operation.

The terminal designation register 153 is a register that designates an input terminal to be converted when A / D-converting a single terminal, and the value of the terminal designation register 153 directly designates the input terminal.

That is, if the terminal designation register 153 is "3", the input terminal 113 is designated, and if the terminal designation register 153 is "6", the input terminal 116 is designated.

When the detection circuit 180 detects the operation of writing “1” in the operation control register 152, it activates the conversion signal line 185 (“1”) to the operation control unit 150.
Tell 52 that "1" has been written.

Next, the relationship between the operation of the A / D conversion device 100 and the operation control unit 150, the operation designation registers 151 and 152, the terminal designation register 153, the A / D conversion request signal line 160, and the conversion signal line 185 will be described in detail.

Normally, an A / D converter corresponds to two cases: one analog input terminal continues A / D conversion and a plurality of analog input terminals sequentially A / D converted. It is common to perform two operations.

The operation designation registers 151 and 152 function as registers for switching this operation. The relationship between the value of the operation specification register and the A / D conversion operation will be described below.

(1) When the operation specification register 152 is “0” and the operation specification register 151 is “0”, the A / D conversion device 100 continues to operate the single analog input terminal specified by the terminal specification register 153 as described above. Continue to / D conversion. The A / D conversion result is stored in the register corresponding to the analog input terminal (for example, the analog input terminal 114 to register 14
Store in 4).

The interrupt signal line 170 is activated (“1”) every time one A / D conversion is completed. This allows registers 140-1
Request to take the A / D conversion result in 47 to CPU080,
The A / D conversion operation is started again and the above operation is repeated.

(2) When the operation specification register 152 is “0” and the operation specification register 151 is “1”, the A / D conversion device 100 performs an operation of sequentially A / D converting all analog input terminals. , Pin specification register 15
3 is invalid.

Specifically, the analog input terminal 110 is converted, the conversion result is stored in the register 140, and then the analog input terminal 111 is converted.
Is converted, the conversion result is stored in the register 141, the conversion is performed in the same manner, and when the conversion of the analog input terminal 117 is completed, the interrupt signal line 170 is activated (“1”).

After that, the A / D conversion operation is started again from the analog input terminal 110 and repeated.

(3) When the operation designation register 152 is "1" Regardless of the value of the operation designation register 151, the operation designation register 152 is controlled by the write operation.

That is, when the CPU 080 performs the operation of writing "1" to the operation designation register 152, the detection circuit 180 detects that "1" has been written and activates the conversion signal line 185 ("1"). To

As a result, the A / D conversion device 100 causes the terminal designation register 15
Performs A / D conversion once for the input terminal specified in 3.

Furthermore, when the A / D conversion result is learned in the example of (1) and stored in any one of the registers 140 to 147 corresponding to the input terminal, the interrupt signal 170 is activated (“1”).
Request 080 to retrieve the conversion result.

 Next, the operation shifts to A / D conversion of all input terminals.

However, in the operation of A / D converting all the input terminals, the interrupt signal 170 is not activated (“1”).

Further, when the operation control unit 150 receives an A / D conversion request from the outside by the A / D conversion request signal 160, the A / D conversion device 10
For 0, the operation started by the CPU080 by writing "1" in the operation designation register 152, that is, when the CPU080 writes "1" in the operation designation register 152, the detection circuit 1
The conversion signal line 185 is activated ("1") by detecting that "1" has been written in 80, whereby the A / D conversion device 100 causes the input terminal designated by the terminal designation register 153. of
The same operation as that of performing A / D conversion once is performed.

That is, the A / D conversion device 100 performs A / D conversion of the input terminal designated by the terminal designation register 153 when the A / D conversion request signal 160 becomes active (“1”), and again when one conversion is completed. Move to A / D conversion operation for all input terminals.

Next, the operation of the entire A / D conversion device of the present invention will be described.

If the CPU080 only wants to execute A / D conversion of a specific terminal, it may set “0” in the operation specification register 152 and “0” in the operation specification register 152, and similarly, A / D conversion of a plurality of input terminals. When it is desired to execute D conversion, "0" may be set in the operation designation register 152 and "1" may be set in the operation designation register 151.

When it is desired to perform both the operations described above, "1" may be set in the operation designation register 152.

For example, if the CPU080 knows the state of a specific pin at the time of a subroutine call by executing an A / D conversion subroutine call while executing a program, simply write "1" to the operation command register 152 to perform A / D conversion. The device 100 performs A / D conversion of the input terminals designated by the terminal designation register 153, and then shifts to A / D conversion of all input terminals.

Therefore, the CPU 080 only needs to write the operation specification register 152 only once, and then the A / D conversion device 100 performs the operation of A / D converting the single analog input terminal specified by the terminal specification register 153. It is possible to shift to the operation of A / D converting the input terminal.

Moreover, it is not necessary to perform the operation of masking and unmasking the interrupt signal accompanying this series of operations.

Further, by the A / D conversion request signal line 160, the above operation can be performed in synchronization with the change of the external event without depending on the instruction execution of the CPU 080. In this case, the CPU simply displays the A / D conversion result. Only take action.

Next, a second embodiment of the present invention will be described with reference to FIG. Microcomputer 020 has CPU080, A
It comprises an / D converter 200 and an internal bus 090 for exchanging data between the CPU 080 and the A / D converter 200.

The CPU 080 performs a data read / write operation with respect to the A / D conversion device 200 by executing a program, and also receives an interrupt signal 170 from the A / D conversion device.

The A / D converter 200 includes input terminals 110 to 117 for inputting analog signals, a multiplexer 120, and a multiplexer 1.
A / D converter 130 and A / D converter 13 for A / D converting 20 output signals
Registers 140 to 147 that store the conversion result of 0, an operation control unit 250 that controls the operation of A / D conversion, and a request to start the A / D conversion
A / D conversion request signal line 160, an interrupt signal line 170 for requesting interrupt processing to the CPU 080 when a predetermined A / D conversion operation is completed, and an input terminal designation for designating an input terminal to be selected for the multiplexer 120 Signal line 190, register 140-
Address designation signal line 195 for selecting one of 147, operation designation registers 151, 152 for controlling A / D conversion, terminal designation register 153 for designating an input terminal to be converted, and operation designation register 152 set to "1". A write detection circuit (hereinafter abbreviated as a detection circuit) 180 for detecting a writing operation, and a signal line (hereinafter abbreviated as a converted signal) 185 indicating that "1" is written in the operation control register 152.

 Next, each part of the A / D conversion device 200 will be described.

Multiplexer 120, A / D converter 130, registers 140 to 147,
The operations of the interrupt signal line 170, the input signal designating line 190, and the address signal line designating 195 are the same as those in the first embodiment, and the description thereof is omitted here.

In the following, the operation designation registers 151 and 15 in this embodiment will be described.
The operation relationship between the value of 2, the terminal designation register 153, and the A / D converter 200 will be described.

(1) When the operation specification register 152 is "0" and the operation specification register 151 is "0", (2) When the operation specification register 152 is "0" and the operation specification register 151 is "1", (3) Operation When the designation register 152 is “1” and the operation designation register 151 is “0”, the above case is (1) in the first embodiment,
The description is omitted because it is the same as (2) and (3).

(4) When the operation specification register 152 is “1” and the operation specification register 151 is “1”, at this time, in the A / D converter 200, the CPU080 writes the operation specification register 152 with “1”. Then, the detection circuit 180 detects that "1" has been written, and the conversion signal line 1
Make 85 active (“1”).

As a result, the A / D conversion device 200 causes the terminal designation register 15
When the A / D conversion of the input terminal designated by 3 is performed four times and the conversion result is stored in the registers 140 to 143, the interrupt signal 170 is activated (“1” and the CPU080 is requested to receive the conversion result four times. .

After that, the A / D converter 200 sequentially inputs / outputs the input terminals 114 to 117.
The operation proceeds to conversion, and the conversion result is stored in registers 144 to 147.
To be stored.

However, in the operation of A / D converting the input terminals 114 to 117, the interrupt signal 170 is not activated (“1”).

Further, when the operation control unit 250 receives an A / D conversion request from the outside by the A / D conversion request signal 160, the A / D conversion device 200
On the other hand, when the CPU starts an operation by writing “1” in the operation specifying register 152, that is, when the CPU 080 writes “1” in the operation specifying register 152, the detection circuit 180
Detects that the "1" has been written, activates the conversion signal line 185 ("1"), and thereby the A / D converter 200
Performs an operation similar to the operation of performing A / D conversion of the input terminal designated by the terminal designation register 153 four times.

That is, when the A / D conversion request signal 160 becomes active (“1”), the A / D conversion device 200 returns to the above (3) or (4).
The operation of.

Next, the operation of the entire A / D conversion device of the present invention will be described.

When the CPU080 only wants to execute A / D conversion of a specific terminal, it may set “0” in the operation designation register 152 and “0” in the operation designation register 151, as in the first embodiment.
Similarly, if you want to execute only A / D conversion for multiple input terminals, set the operation specification register 152 to "0" and the operation specification register 151.
Set “1” to. Further, when it is desired to perform both the operations described above, "1" may be set in the operation designation register 152 and "0" may be set in the operation designation register 151.

For example, when CPU080 knows the state of a specific pin at the time of subroutine call by executing A / D conversion subroutine call while executing the program, the error of analog value of input pin,
Multiple A / D conversion results may be averaged to remove the effects of noise.

At this time, the CPU 080 may set "1" to both the operation designation registers 151 and 152.

The A / D conversion apparatus 200 only performs the A / D conversion of the input terminal designated by the terminal designation register four times after setting the operation designation registers 151 and 152, and then performs the A / D conversion of the plurality of input terminals.
Move to conversion operation.

Therefore, the CPU080 has only one operation specification register 151,15.
With only 2 write operations, the A / D converter causes one analog input terminal to A / D convert four times, and then shifts to the operation of A / D converting multiple input terminals. ， No need to unmask.

Similarly, the A / D conversion request signal line 160
It is also possible to perform the above operations in synchronization with changes in external events, without depending on the U080 command execution. In this case, the CPU simply takes the A / D conversion result.

Next, a third embodiment of the present invention will be described with reference to FIG. Microcomputer 030, CPU080, A
It is composed of an / D converter 300 and an internal bus 090 for exchanging data between the CPU 080 and the A / D converter 300.

The CPU 080 performs a data read / write operation with respect to the A / D conversion device 300 by executing a program, and also performs a process of receiving an interrupt signal 170 from the A / D conversion device.

The A / D conversion device 300 includes input terminals 110 to 117 for inputting analog signals, a multiplexer 120, and a multiplexer 1.
A / D converter 130 and A / D converter 13 for A / D converting 20 output signals
Registers 140 to 147 that store the conversion result of 0, an operation control unit 350 that controls the operation of A / D conversion, an A / D conversion request signal line 160 that requests the start of A / D conversion for the input terminals 110 to 117. ~ 1
67, an interrupt signal line 170 for requesting interrupt processing to the CPU 080 when a predetermined A / D conversion operation is completed, an input terminal designation signal line 190 for designating an input terminal to be selected for the multiplexer 120, and a register 140 to Address designation signal line 195 for selecting one of 147, operation designation registers 151, 152 for controlling A / D conversion, terminal designation register 153 for designating an input terminal to be converted, and operation designation register 152 set to "1". A write detection circuit (hereinafter abbreviated as detection circuit) 180 for detecting a writing operation, and a signal line (hereinafter abbreviated as conversion signal line) indicating that "1" is written in the operation control register 152 18
Composed of 5.

 Next, each part of the A / D conversion device 300 will be described.

Multiplexer 120, A / D converter 130, registers 140-14
7, the operation of the interrupt signal line 170, the input signal designation line 190, the address designation signal line 195, the detection circuit 180, the conversion signal line 185,
Since it is the same as the first embodiment, the description thereof is omitted here.

The operation control unit 350 has operation specifying registers 151 and 152 and a terminal specifying register 153.
1, 152 can be accessed from the CPU 080, the terminal designation register 153 can be accessed from the CPU 080, and can be written by the operation control unit 350.

The value of the pin designation register 153 directly designates the input pin. For example, if the pin designation register 153 is "3".
If so, specify input terminal 113 and set terminal specification register 153 to "6".
Then, the input terminal 116 is designated.

A / D conversion request signal lines 160 to 167 are signals that request the operation control unit 350 to perform A / D conversion on the input terminals 110 to 117, and correspond to the analog signal input terminals 110 to 117, respectively. There is.

For example, the A / D conversion request signal line 163 makes a conversion request for the input terminal 113, and the A / D conversion request signal line 166 makes a conversion request for the input terminal 116.

Further, the operation control unit 350 writes the value of the input terminal corresponding to the request in the terminal designation register 153 in response to the A / D conversion request from the A / D conversion request signal lines 160 to 167, and the A / D conversion device.
CPU 300 is caused to perform the same operation as the operation in which CPU 080 writes "1" to operation designation register 152.

For example, when the A / D conversion request signal 162 is input to the operation control unit 350, the operation control unit 350 causes the terminal designation register 153 to indicate “2”.
When the A / D conversion request signal 165 is input, “5” is written in the pin designation register 153.

Simultaneously with the above operation, the operation control unit 350 activates the A / D conversion of the input terminal corresponding to the value of the terminal designation register 153.

In the following, the operation designation registers 151 and 15 in this embodiment will be described.
Value of 2, A / D conversion request signal lines 160-167 and pin specification register
An operational relationship between the 153 and the A / D conversion device 300 will be described.

(1) When the operation specification register 152 is “0” and the operation specification register 151 is “0”, the A / D conversion device 300 continues the single analog input terminal specified by the above-mentioned terminal specification register 153 to A Continue to / D conversion. In this case, the inputs of the A / D conversion request signal lines 160 to 167 are ignored.

Since the basic operation at this time is the same as the operation in the case of (1) of the first embodiment, description thereof will be omitted.

(2) When the operation specification register 152 is “0” and the operation specification register 151 is “1”, the A / D conversion device 300 performs the operation of sequentially A / D converting all analog input terminals. , Pin specification register 15
3 is invalid. Therefore, the states of the A / D conversion request signal lines 160 to 167 are not affected.

Since the basic operation at this time is the same as the operation in the case of (2) of the first embodiment, description thereof will be omitted.

(3) When the operation specification register 152 is "1" and the operation specification register 151 is "0", the CPU 080 first writes the value of the input terminal to be A / D converted into the terminal specification register 153 in advance. .

Then, the CPU080 sets the operation designation register 152 to "1".
When the write operation is performed, the detection circuit 180 detects that "1" has been written and activates the conversion signal line 185 ("1").
To

As a result, the A / D conversion device 300 performs A / D conversion once on the input terminal designated by the CPU 080 writing to the terminal designation register 153.

Further, when the A / D conversion result is stored in any one of the registers 140 to 147 corresponding to the input terminal after the A / D conversion is completed,
CPU080 with interrupt signal 170 active (“1”)
Request to receive the conversion result.

 Next, the operation shifts to A / D conversion of all input terminals.

However, in the operation of A / D converting all the input terminals, the interrupt signal 170 remains inactive (“0”).

Further, as for the A / D conversion request signal lines 160 to 167, only the A / D conversion request signal line corresponding to the input terminal designated by the terminal designation register 153 is permitted to be accepted. When the A / D conversion request signal line corresponding to the specified input terminal becomes active (“1”), an A / D conversion request for that input terminal is made. For the D converter 300, an operation started by the CPU 080 writing “1” to the operation designation register 152, that is, when the CPU 080 writes “1” to the operation designation register 152, the detection circuit 180 outputs “1”. It is detected that "" has been written, and the conversion signal line 185 is activated ("1"), whereby the A / D conversion device 300 causes the terminal designation register 153
Performs the same operation as performing the A / D conversion once on the input terminal specified by.

That is, when the A / D conversion request signal corresponding to the input terminal designated by the terminal designation register 153 becomes active (“1”), the A / D conversion device 300 makes A / D of the input terminal designated by the terminal designation register 153. D conversion is performed, and when one conversion is completed, the operation shifts to A / D conversion of all input terminals again. afterwards,
Acceptable by the pin specification register 153 A
The above operation is repeated every time the / D conversion request signal line becomes active.

(4) When the operation specification register 152 is "1" and the operation specification register 152 is "1", the CPU080 first writes the value of the input terminal to be A / D converted into the terminal specification register 153 in advance. .

Then, the CPU080 sets the operation designation register 152 to "1".
Is performed, the detection circuit 180 detects that "1" has been written, and activates the conversion signal line 185 ("1").

As a result, the A / D conversion device 300 operates in the pin designation register 15
Performs A / D conversion once for the input terminal specified in 3.

In addition, the A / D conversion result is sent to the register 1 corresponding to the input terminal.
When stored in one of 40 to 147, interrupt signal 1
70 is activated (“1”) and CPU080 is requested to receive the conversion result.

At this time, the CPU 080 first reads the contents of the pin designation register 153 and identifies the input terminal of the A / D conversion performed immediately before to know the storage position of the conversion result and read the conversion result.

 Next, the operation shifts to A / D conversion of all input terminals.

However, in the operation of A / D converting all the input terminals, the interrupt signal line 170 remains inactive (“0”).

In addition, the A / D conversion request signal lines 160 to 167 are all permitted to be accepted by the operation control unit 350, and the A / D conversion request signal line becomes active (“1”) to an external input terminal. If a request for A / D conversion is made, the operation control unit 350
Writes the value of the input terminal for which A / D conversion is requested to the terminal designation register 153.

For example, if the input terminal 115 is requested for A / D conversion, the value "5" is set, and if the input terminal 117 is requested for A / D conversion, the value "7" is set. Is written in the pin designation register 153.

Further, in synchronization with the above operation, the operation started by the CPU080 writing "1" to the operation designation register 152 in the A / D converter 300, that is, the CPU080 writes "1" to the operation designation register 152. Is written, the detection circuit 180 turns to "1".
Is detected and the conversion signal line 185 is activated (“1”), whereby the A / D conversion device 300 performs A / D conversion of the input terminal specified by the terminal specification register 153 once. The same operation as that of performing is performed, and A / D conversion is started for the input terminal indicated by the terminal designation register 153 in which the value of the input terminal for which A / D conversion is requested is written.

After one A / D conversion, the operation shifts to A / D conversion of all input terminals.

That is, when any A / D conversion request signal line becomes active (“1”), the A / D conversion device 300 causes the operation control unit 350 that receives this request to specify the value of the requested input terminal as a terminal. Writing to the register 153, A / D conversion of the input terminal designated by the terminal designation register 153 is performed, and when one conversion is completed, the operation shifts to the A / D conversion of all the input terminals again.

After that, the above operation is repeated every time any one of the A / D conversion request signal lines 160 to 167 becomes active.

Finally, the operation of the entire A / D conversion device of this embodiment will be described.

The CPU080 sets (1) “0” to the operation specification register 152 and “0” to the operation specification register 151 when only performing the operation of A / D converting the input terminal specified by the terminal specification register 153. .

(2) To perform only the operation of sequentially A / D converting a plurality of input terminals, set "0" in the operation designation register 152 and "1" in the operation designation register 151.

(3) I want to perform both the A / D conversion operation of a specific input terminal specified by the pin specification register 153 according to the A / D conversion request from inside / outside and the operation of sequentially A / D converting all the input terminals. In this case, the operation designation register 152 is set to "1" and the operation designation register 151 is set to "0".

(4) The CPU080 performs A / D conversion on a specific input terminal specified in the terminal specification register 153 or an input terminal for which A / D conversion is requested by a plurality of external A / D conversion request signal lines. When it is desired to sequentially perform A / D conversion operations on the input terminals, set "1" in the operation designation register 152 and "1" in the operation designation register 151.

Next, a fourth embodiment of the present invention will be described with reference to FIG. Microcomputer 040 has CPU080 and A
It comprises an / D converter 400 and an internal bus 090 for exchanging data between the CPU 080 and the A / D converter 400.

The CPU 080 performs a data read / write operation with respect to the A / D conversion device 400 by executing the program, and also performs a process of receiving an interrupt signal 170 from the A / D conversion device 400.

The A / D conversion device 400 includes input terminals 110 to 117 for inputting analog signals, a multiplexer 120, and a multiplexer 1.
A / D converter 130 and A / D converter 13 for A / D converting 20 output signals
Registers 140 to 147 that store the conversion result of 0, an operation control unit 450 that controls the operation of A / D conversion, and an A / D conversion request signal line 160 that requests the start of A / D conversion for the input terminals 110 to 117. ~ 1
67, an interrupt signal line 170 for requesting interrupt processing to the CPU 080 when a predetermined A / D conversion operation is completed, an input terminal designation signal line 190 for designating an input terminal to be selected for the multiplexer 120, and a register 140 to Address designation signal line 195 for selecting one of 147, operation designation registers 151, 152 for controlling A / D conversion, terminal designation register 153 for designating an input terminal to be converted, A / D conversion request signal line 160 to 1
A / D to be preferentially accepted among A / D conversion requests by 67
A priority determination circuit (hereinafter abbreviated as a determination circuit) 154 for determining a conversion request, a determination result signal (hereinafter abbreviated as a determination signal) 155 as a result of the determination by the determination circuit 154, a terminal designation register 1
A content display signal (hereinafter abbreviated as display signal) 156 for displaying the contents of 53 on the determination circuit 154, a write detection circuit (hereinafter abbreviated as detection circuit) 180 for detecting the operation of writing "1" to the operation designation register 152, operation The control register 152 includes a signal line (hereinafter, referred to as a conversion signal line) 185 indicating that "1" is written.

 Next, each part of the A / D converter 400 will be described.

Multiplexer 120, A / D converter 130, registers 140-14
The operations of 7, the interrupt signal line 170, the input signal designation line 190, the address signal line 195, the detection circuit 180, and the conversion signal line 185 are the same as those in the first embodiment, and thus the description thereof is omitted here.

A / D conversion request signal lines 160 to 167 are signal lines that request the operation control unit 450 to perform A / D conversion of the input terminals 110 to 117,
Each corresponds to an analog signal input terminal 110-117.

For example, the A / D conversion request signal line 163 makes a conversion request for the input terminal 113, and the A / D conversion request signal line 166 makes a conversion request for the input terminal 116.

The operation control unit 450 has operation designation registers 151 and 152, a terminal designation register 153, and a determination circuit 154.

The operation designation registers 151 and 152 can be accessed by the CPU 080, the terminal designation register 153 can be accessed by the CPU 080, and the operation control unit 450 can also write them.

The value of the pin designation register 153 directly designates the input pin. For example, if the pin designation register 153 is "3".
If so, specify input terminal 113 and set terminal specification register 153 to "6".
Then, the input terminal 116 is designated.

The determination circuit 154 uses the A / D conversion request signal lines 160 to 167 to simultaneously request A / D conversion for different input terminals, or for a certain input terminal activated by an A / D conversion request. If a new A / D conversion request is made for another input pin during execution of the A / D conversion of, the A / D conversion request to be accepted from those A / D conversion requests is input in advance for each input pin. Judgment is made based on the priority order defined in 1. and the result is transmitted to the terminal designation register 153 as a judgment signal 155.

In order to simplify the explanation, in the present embodiment, the priority order of A / D conversion is that the A / D conversion request signal line 160 has the lowest priority, 161, ..., 1.
I will explain the case where the priority becomes higher in the order of 67,
The setting of the priority order in the present invention is not limited to this case.

Further, in order to describe the operation of the determination circuit 154, it is assumed that the numerical values “0” to “7” are assigned to the A / D conversion request signal lines 160 to 167 and the input terminals 110 to 117 are represented.

In the above case, the determination circuit 154 determines the priority order based on the values of the input terminals corresponding to the plurality of A / D conversion request signal lines that have made the request, and the A / D that received the result. The value of the input terminal corresponding to the conversion request is determined by the judgment signal 155
Is written in the pin designation register 153 as

In the above case, the value of the input terminal for which the A / D conversion request is made is compared with the value of the display signal 156 indicating the content of the terminal designation register 153, and a) a new A / D conversion is performed. When the value of the input terminal for which the request is made is larger than the value of the display signal 156, that is, the priority is higher, the value of the input terminal is output as the determination signal 155 and written to the terminal designation register 153, b) When the value of the input terminal for which A / D conversion is requested is smaller than the value of the display signal 156, that is, when the priority is lower, the value of the display signal 156 is output as the determination signal 155, but the terminal designation register 153 Do not write to.

In both cases, the respective operations are performed together.

Specifically, regarding the input terminal 115 by the A / D conversion request signal line 165, when the A / D conversion is being performed for the input terminal 113 by the A / D conversion request by the A / D conversion request signal 163. When the request for A / D conversion of and the request for A / D conversion for the input terminal 116 by the A / D conversion request signal line 166 are made at the same time, the value “5” of the input terminal 115 and the value of the input terminal 116 Value "6"
And the value “3” of the display signal 156 indicating the content of the terminal designation register 153 are compared, and the A / D conversion request for the input terminal 116 having a larger value, that is, the higher priority is accepted, and the determination result The value "6" is output as the determination signal 155 that is, and this is written in the terminal designation register 153.

Further, the operation control unit 450, when the determination circuit 154 rewrites the terminal designation register 153, the A / D conversion device 40.
For 0, the CPU 080 performs the same operation as the operation started by writing “1” to the operation designation register 152.

In the following, in the embodiment, A / D conversion request signal lines 160 to 16
7, operation designation registers 151, 152 in the operation control unit 450,
The operation relationship between the terminal designation register 153 and the A / D conversion device 400 will be described.

(1) When the operation specification register 152 is "0" and the operation specification register 151 is "0", (2) When the operation specification register 152 is "0" and the operation specification register 151 is "1", (3) Operation When the designation register 152 is "1" and the operation designation register 151 is "0", the determination circuit 154 of the operation control unit 450 does not operate at this time, and therefore the basic operation is the same as in (1) of the first embodiment. , (2)
Since the operation is the same as that in the case (2) of the third embodiment, the description thereof will be omitted.

(4) When the operation specification register 152 is "1" and the operation specification register 151 is "1", at this time, the CPU080 sets the operation specification register 152 to "1".
Is performed, the detection circuit 180 detects that "1" has been written, and activates the conversion signal line 185 ("1").

Further, the CPU 080 writes all the A / D conversion requests in the terminal designation register 153 by writing the value “0” indicating the input terminal 110 having the lowest priority.

As a result, the A / D conversion device 400 performs the A / D conversion of the input terminal 110 once.

Further, when the A / D conversion result is stored in the register 140 corresponding to the input terminal, the interrupt signal 170 is activated (“1”), and the CPU 080 is requested to take the conversion result.

 Next, the operation shifts to A / D conversion of all input terminals.

However, in the operation of A / D converting all the input terminals, the interrupt signal line 170 remains inactive (“0”).

In addition, the A / D conversion request signal lines 160 to 167 are all permitted to be accepted by the operation control unit 450, and in this state, when an external A / D conversion request is made to an arbitrary input terminal. The operation control unit 450 uses the determination circuit 154 to
When accepting the request is judged from the value of the input terminal for which the A / D conversion was requested, and when accepting the request,
The value of the input pin corresponding to the request is set to the pin specification register 15
3 is written, and in synchronization with this, an operation started by the CPU 080 writing “1” to the operation designation register 152 in the A / D conversion device 400, that is, the CPU 080 sends “1” to the operation designation register 152. When 1 "is written, the detection circuit 180 detects that" 1 "has been written and activates the conversion signal line 185 (" 1 "), whereby the A / D conversion device 400 causes the pin designation register 153. Performs the same operation as performing the A / D conversion of the input terminal specified in step 1 once, activates the A / D conversion of the requested input terminal, and if the request is not accepted, A No change is applied to the / D converter 400.

Then, after one A / D conversion, the A / D conversion device 400 is shifted to the operation of sequentially A / D converting all the input terminals.

When the CPU080 performs A / D conversion on a specific pin in response to an A / D conversion request from the outside, after the conversion is completed, the contents of the pin designation register 153 are first read and the A / D conversion performed immediately before is performed. By knowing the input terminal for D conversion, the read position from the conversion result storage registers 140 to 147, that is, the addressing signal line 195 is determined, and the conversion result is read.

After that, any one of the A / D conversion request signal lines 160 to 167 is activated, and the above operation is repeated each time an A / D conversion request is made.

Finally, the operation of the entire A / D conversion device of this embodiment will be described.

The CPU080 sets (1) “0” to the operation specification register 152 and “0” to the operation specification register 151 when only performing the operation of A / D converting the input terminal specified by the terminal specification register 153. .

(2) To perform only the operation of sequentially A / D converting a plurality of input terminals, set "0" in the operation designation register 152 and "1" in the operation designation register 151.

(3) I want to perform both the A / D conversion operation of a specific input terminal specified by the pin specification register 153 according to the A / D conversion request from inside / outside and the operation of sequentially A / D converting all the input terminals. In this case, the operation designation register 152 is set to "1" and the operation designation register 151 is set to "0".

(4) A specific input terminal specified by the CPU080 in the terminal specification register 153 or an input corresponding to an A / D conversion request selected from a plurality of external A / D conversion requests based on a specified priority. When you want to perform the A / D conversion operation for a pin and the A / D conversion operation for all input pins in sequence, set the operation specification register 152 to "1" and the operation specification register 151 to "1". .

Next, a fifth embodiment of the present invention will be described with reference to FIG. Microcomputer 050 has CPU080 and A
It comprises an / D converter 500 and an internal bus 090 for exchanging data between the CPU 080 and the A / D converter 500.

The CPU 080 performs a data read / write operation with respect to the A / D conversion device 500 by executing a program, and also performs a process of receiving an interrupt signal 170 from the A / D conversion device 500.

The A / D conversion device 500 includes input terminals 110 to 117 for inputting an analog signal, a multiplexer 120, and a multiplexer 1.
A / D converter 130 and A / D converter 13 for A / D converting 20 output signals
Registers 140 to 147 that store the conversion result of 0, an operation control unit 550 that controls the operation of A / D conversion, an A / D conversion request signal line 160 that requests the start of A / D conversion for the input terminals 110 to 117. ~ 1
67, an interrupt signal line 170 for requesting interrupt processing to the CPU 080 when a predetermined A / D conversion operation is completed, an input terminal designation signal line 190 for designating an input terminal to be selected for the multiplexer 120, and registers 14 to Address designation signal line 195 for selecting one of 147, operation designation registers 151, 152 for controlling A / D conversion, terminal designation register 153 for designating an input terminal to be converted, A / D conversion request signal line 160 to 167
Priority specification register 158 that specifies the priority order for accepting A / D conversion requests by the A / D conversion request by the A / D conversion request lines 160 to 167. Rank judgment circuit (hereinafter abbreviated as judgment circuit)
154, a determination result signal (hereinafter abbreviated as a determination signal) 155 which is a result of the determination by the determination circuit 154, a content display signal (hereinafter abbreviated as a display signal) 156 for displaying the contents of the terminal designation register 153 on the determination circuit 154, and a priority order. A content display signal (hereinafter abbreviated as display signal) 157 for displaying the contents of the designated register 158 on the determination circuit 154, and a write detection circuit (hereinafter abbreviated as detection circuit) 180 for detecting the operation of writing "1" to the operation designation register 152. , A signal line (hereinafter abbreviated as a conversion signal line) 185 indicating that “1” is written in the operation control register 152.

 Next, each part of the A / D conversion device 500 will be described.

Multiplexer 120, A / D converter 130, registers 140-14
The operations of 7, the interrupt signal line 170, the input signal designation line 190, the address signal line 195, the detection circuit 180, and the conversion signal line 185 are the same as those in the first embodiment, and thus the description thereof is omitted here.

A / D conversion request signal lines 160 to 167 are signal lines that request the operation control unit 550 to perform A / D conversion of the input terminals 110 to 117,
Each corresponds to an analog signal input terminal 110-117.

For example, the A / D conversion request signal line 163 makes a conversion request for the input terminal 113, and the A / D conversion request signal line 166 makes a conversion request for the input terminal 116.

The operation control unit 550 has operation specifying registers 151 and 152, a terminal specifying register 153, a priority specifying register 158, and a determination circuit 154.

Operation specification registers 151, 152, priority specification register 158
Can be accessed from CPU080, and pin specification register 15
3 can be accessed by the CPU 080 and can be written by the operation control unit 550.

The value of the pin designation register 153 directly designates the input pin. For example, if the pin designation register 153 is "3".
If so, specify input terminal 113 and set terminal specification register 153 to "6".
Then, the input terminal 116 is designated.

As described in the third and fourth embodiments, by setting "1" in the operation designation register 152 and "1" in the operation designation register 151, the operation of A / D converting a specific input terminal and all inputs In the case where the operation of sequentially performing A / D conversion on the terminals is also executed, the determination circuit 154 determines that the A / D conversion request signal lines 160 to 167 simultaneously make A / D conversion requests for different input terminals. Or if a new A / D conversion request is made for another input pin while the A / D conversion is being performed for one input pin that was activated by the A / D conversion request, those A Priority designation register 1 from among / D conversion requests
Based on the priority designated by 58, the input terminal having the higher priority is determined, and as a result, the value of the input terminal having the higher priority is transmitted to the terminal designation register 153 as the determination signal 155.

In the above case, the determination circuit 154 determines the priority order of the values of the input terminals corresponding to the plurality of A / D conversion request signal lines that have made the request based on the priority order specified in the priority order specification register 158. The value of the input terminal having a higher priority than the result of the determination is written as the determination signal 155 in the terminal designation register 153.

In the above case, the value of the input terminal for which the A / D conversion request is made and the value of the display signal 156 indicating the contents of the terminal designation register 153 are set to the priority designated by the priority designation register 158. Based on which, the higher priority is determined, and a) From the input terminal newly requested for A / D conversion,
When the input terminal indicated by the display signal 156 has a lower priority designated by the priority designation register 158, the value of the input terminal is output as the determination signal 155 and written in the terminal designation register 153, b). From the input terminal for which a new A / D conversion request was made,
When the input terminal indicated by the display signal 156 has a higher priority designated by the priority designation register 158, the value of the display signal 156 is output as the determination signal 155, but the terminal designation register 153 is not written. Do not do.

In both cases, the respective operations are performed together.

Specifically, in the priority designation register 158, the input terminal 110 as the highest priority input terminal, the input terminal 111 as the second highest priority input terminal, the input terminal 115 as the third highest priority input terminal, The input terminal 112 is the fourth highest priority input terminal, the input terminal 116 is the fifth highest priority input terminal, the input terminal 114 is the sixth highest priority input terminal, and the seventh highest priority input terminal. Is designated as the input terminal 113, and the input terminal 117 is designated as the input terminal having the eighth highest priority, and the input terminal is requested by the A / D conversion request signal line 163 for the A / D conversion.
When performing A / D conversion for 113, a request for A / D conversion for the input terminal 115 by the A / D conversion request signal line 165 and a request for input terminal 116 by the A / D conversion request signal line 166 are performed. When the A / D conversion requests are made at the same time, the input terminal 115, the input terminal 116, and the input terminal 113 indicated by the display signal 156 indicating the content of the terminal designation register 153 are set on the basis of the priority designation register 158. It is determined which input terminal has a higher priority, and the A / D conversion request for the input terminal 115 having a higher priority than the result of the determination is accepted.
A value "5" representing the input terminal 115 is output as the judgment signal 155 which is the judgment result, and this is written in the terminal designation register 153.

Further, the operation control unit 550, when the terminal designating register 153 is rewritten by the determination circuit 154, the A / D conversion device 50.
For 0, the CPU 080 performs the same operation as the operation started by writing “1” to the operation designation register 152.

The A / D conversion request signal line 160-
167, operation designation registers 151 and 15 in the operation control unit 550
2, pin specification register 153, priority specification register 158,
The operation relationship between the A / D converter 500 and the A / D converter 500 will be described.

(1) When the operation specification register 152 is "0" and the operation specification register 151 is "0", (2) When the operation specification register 152 is "0" and the operation specification register 151 is "1", (3) Operation When the designation register 152 is "1" and the operation designation register 151 is "0", at this time, the determination circuit 154 of the operation control unit 550 does not operate at all. Therefore, the basic operation is (1) of the first embodiment. , (2)
Since the operation is the same as that in the case (2) of the third embodiment, the description thereof will be omitted.

(4) When the operation specification register 152 is "1" and the operation specification register 151 is "1", at this time, the CPU080 sets the operation specification register 152 to "1".
Is performed, the detection circuit 180 detects that "1" has been written, and activates the conversion signal line 185 ("1").

Further, the CPU 080 writes a value indicating the input terminal having the lowest priority specified by the priority specification register 158 to the terminal specification register 153, so that all the A / D conversion requests can be accepted.

As a result, the A / D conversion device 500 performs the A / D conversion of the input terminal 110 once.

Further, when the A / D conversion result is stored in the register 140 corresponding to the input terminal, the interrupt signal 170 is activated (“1”), and the CPU 080 is requested to take the conversion result.

 Next, the operation shifts to A / D conversion of all input terminals.

However, in the operation of A / D converting all the input terminals, the interrupt signal line 170 remains inactive (“0”).

Also, the A / D conversion request signal lines 160 to 167 are all allowed to be accepted by the operation control unit 550, and in this state, when an external A / D conversion request is made to any input terminal. The operation control unit 550 uses the determination circuit 154 to
If the acceptance of the request is judged from the value of the input terminal for which the A / D conversion was requested, and if the request is accepted,
The value of the input pin corresponding to the request is set to the pin specification register 15
3 is written to the A / D converter 500 in synchronization with this, the CPU 080 writes “1” to the operation designation register 152 to detect that the detection circuit 180 has written “1”. The conversion signal line 185 is activated (“1”) by this, whereby the A / D conversion device 500 performs the same operation as the operation of performing A / D conversion of the input terminal specified by the terminal specification register 153 once. Then, the A / D conversion of the requested input terminal is activated, and when the request is not accepted, the A / D conversion device 500 is not changed.

Then, after one A / D conversion, the A / D converter 500 is caused to shift to an operation of sequentially A / D converting all the input terminals.

When the CPU080 performs A / D conversion on a specific pin in response to an A / D conversion request from the outside, after the conversion is completed, the contents of the pin designation register 153 are first read and the A / D conversion performed immediately before is performed. By knowing the input end of the D conversion, the read position from the conversion result storage registers 140 to 147, that is, the addressing signal line 195 is determined, and the conversion result is read.

After that, any one of the A / D conversion request signal lines 160 to 167 is activated, and the above operation is repeated each time an A / D conversion request is made.

〔The invention's effect〕

As described above, the present invention has a function that the A / D conversion device automatically shifts to the operation of sequentially A / D converting a plurality of input terminals after the A / D conversion of a single input terminal is completed. By having A / D conversion operation of a single input terminal and A / D conversion operation of multiple input terminals in the control program, the operation switching of A / D conversion, masking of interrupt signal, By eliminating various operations such as unmasking the interrupt signal, it is possible to handle complicated A / D conversion operations without reducing the instruction execution efficiency of the CPU.

2. By allocating the A / D conversion request signal line from the outside that activates the switching of A / D conversion operation to each analog input terminal, each input terminal is independent from the outside.
A / D conversion can be executed in synchronization with the A / D conversion request timing, and A / D conversion can be performed at the optimal timing for each input pin.
The conversion process can be executed.

3. When trying to execute A / D conversion for a specific input terminal, which is activated by a request from the outside, for all input terminals, for each input terminal from the outside
Each time A / D conversion is requested, each A / D conversion is
Since the A / D conversion can be executed automatically without the operation of
All inputs to an analog source group that has a timing of an A / D conversion request from the outside, which does not occur due to the operation of, and it is difficult to specify the input terminal to be A / D converted in advance. It is possible to execute A / D conversion processing for terminals.

4. When an A / D conversion request for a specific input terminal is made from the outside at the same time, or while an A / D conversion started by a certain A / D conversion request is being executed, a new A / D conversion When a request is made, it is possible to automatically select the A / D conversion request for the analog input pin with a high priority without the CPU making a judgment regarding acceptance of the request, so that it can be For a particular input terminal of
In response to the A / D conversion request, from all input terminals, the A / D for the analog input terminal with higher importance is always
It is possible to preferentially perform the conversion.

5. When an A / D conversion request for a specific input terminal is made from the outside at the same time, or while an A / D conversion started by a certain A / D conversion request is being executed, a new A / D conversion When a request is made, the CPU can programmatically specify the priority order for accepting the request, and according to the priority order, the function to select the A / D conversion request for the analog input terminal with a high priority is used. In response to the A / D conversion request for a specific input terminal from, the A / D conversion for the more important analog input terminal that the CPU always requests from all input terminals is given priority. It is possible to carry out.

[Brief description of drawings]

 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, FIG. 3 is a block diagram of a third embodiment of the present invention, and FIG. FIG. 6 is a block diagram of a fourth embodiment of the present invention, FIG. 5 is a block diagram of a fifth embodiment of the present invention, and FIG. 6 is a block diagram of a conventional example.

Claims (4)

[Claims] 1. A central processing unit, a plurality of analog input terminals, an A / D converter, an A / D conversion operation designation register, and one of the plurality of analog input terminals are selected and selected. First A / D conversion of analog input by the A / D converter
Operation, the second operation of sequentially selecting the plurality of analog input terminals and causing the A / D converter to perform A / D conversion, and the third operation of performing the second operation. A / D conversion operation control means for selecting and executing one operation from among the operations based on the contents of the A / D conversion operation designation register rewritten by the central processing unit Microcomputer with built-in D converter. 2. The microcomputer with a built-in A / D conversion device according to claim 1, wherein the A / D converter has an A
Further comprising A / D conversion start request means for requesting the start of / D conversion, wherein the A / D conversion operation control means is further based on the A / D conversion start request by the A / D conversion start request means. Three
A microcomputer with a built-in A / D converter characterized by selecting and executing the operation of. 3. A microcomputer with a built-in A / D converter according to claim 1, wherein the A / D converter is provided corresponding to each of the plurality of analog input terminals.
A plurality of A / D conversion activation requesting means for requesting the D converter to start A / D conversion, and one A / D conversion activation requesting means based on a predetermined priority from the plurality of A / D conversion activation requesting means. A / D conversion start request determining means for selecting one of the A / D conversion start request determining means, and the A / D conversion operation control means further corresponds to the A / D conversion start request by the selected A / D conversion start request means. A microcomputer with a built-in A / D conversion device, characterized in that the third operation is selected and executed for an analog input of the analog input terminal corresponding to the selected A / D conversion activation requesting means. 4. The microcomputer with a built-in A / D conversion device according to claim 3, further comprising a priority order specification register for storing information indicating the predetermined priority order, and the priority order specification register. A microcomputer with a built-in A / D converter, wherein the contents can be rewritten by the central processing unit.