JPH10143376A - Information processing device - Google Patents

Abstract

(57) [Summary] An object of the present invention is to execute a plurality of tasks by switching a plurality of register files by interruption, and to reduce the processing overhead for changing the priority of the tasks. SOLUTION: Each register file 100, 200, 30
The interrupt factor field and the interrupt mask field are held in the status registers 101, 201, and 301 in 0, and the task switching by the register file switching means 30 is controlled using the interrupt factor and the interrupt levels 103, 203, and 303.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus for executing a plurality of tasks, and more particularly, to a context switch suitable for hardware, enabling a task corresponding to an interrupt factor without intervening an interrupt handler. The present invention relates to an information processing apparatus that has a high-speed task response by being directly activated.

[0002]

2. Description of the Related Art Conventionally, such an information processing apparatus is known from Japanese Patent Application Laid-Open No. 7-44404. Hereinafter, the information processing apparatus described in this publication will be described as a conventional technique.

This information processing apparatus includes a plurality of register files (context registers), and each of the register files is selected by a task priority register that holds a task priority of a currently executing task. In addition, information on whether each task can be activated is held in the ready register, and the ready register is changed by operating the ready register bit by an external interrupt to change the ready or impossible state of the task. The task priority corresponding to the bit indicating the executable state is determined by the priority encoder and stored in the task priority register, and when the task priority register changes, the task is switched to a register file corresponding to the task priority. .

[0004] Thus, the task scheduling operation is implemented by hardware, and the response of the task is made faster without the intervention of an interrupt handler.

[0005]

However, in the above information processing apparatus, the priority of a task is determined by the bit position of the ready register, and the register file is selected according to the priority. In order to change the priority of the task, it is necessary to change the assignment of the register file to the task, which causes a problem that processing overhead occurs.

An object of the present invention is to solve the above-mentioned problem, and to increase the speed of task response without the intervention of an interrupt handler, and to reduce the processing overhead for changing the priority of tasks. The purpose is to provide.

[0007]

According to a first aspect of the present invention, there is provided an information processing apparatus having a plurality of interrupt factors and interrupt levels, comprising at least a plurality of register files, File 1
Choose one and use the contents of the register file to
An instruction execution unit that executes a plurality of tasks in a time-sharing manner;
An interrupt factor field including a plurality of bits included in each of the plurality of register files and corresponding to at least each of the interrupt factors and indicating whether the task is a task for processing the interrupt factor or not; A plurality of status registers comprising an interrupt mask field for masking the interrupt level for the cause, and the status in the register file where the interrupt level for the interrupt cause is currently selected based on the occurrence of the interrupt cause. If it is higher than the interrupt mask field of the register, scan the bit corresponding to the generated interrupt factor in the interrupt factor field of all the status registers in the plurality of register files and process the interrupt factor. Detects the register file used by the task and An information processing apparatus that includes a register file switch means for switching to the detected register file.

According to the first aspect of the present invention, the task response to the interrupt cause can be made faster, and the task can be scheduled by the interrupt mask. Also has low processing overhead.

Further, according to a second aspect of the present invention, a plurality of processing units which start processing by a processing unit start command and notify completion of execution of the started processing by interruption, and the respective processing units Processing unit activation means for selectively activating the processing unit, and interrupt level designation means for designating an interruption level upon completion of the processing to the processing unit when the processing unit is activated by a processing unit activation instruction. Each of the processing units generates an interrupt level designated by an interrupt level designating means upon completion of execution, and the register file switching means registers a register based on the interrupt factor and the interrupt level generated by the processing unit. 2. The information according to claim 1, wherein file switching is performed. It is a management apparatus.

According to the second aspect of the present invention, the interrupt level at the time of completion of the execution of the processing unit to be started is designated by the processing unit start instruction, and the interrupt level specified at the time of the start of the processing unit at the time of completion of execution of the processing unit is specified. By interrupting, finer scheduling can be enabled.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of an information processing apparatus according to the present invention. FIG. 1 shows only a part related to the present invention for the purpose of explanation, and the information processing apparatus of the present invention additionally includes an instruction fetch unit for performing instruction fetch, an instruction decoder, a sequencer, a register file, and the like. And a data fetch unit for reading and writing data from and to a memory.

In FIG. 1, 100, 200 and 300
Is a register file that functions to hold the execution state of different tasks executed by the information processing apparatus.
1, 201, 301 and n + 1 (n is an integer of 0 or more) general-purpose registers G0 to Gn.

Reference numerals 400, 401 to 40N denote N + 1 (N is an integer of 0 or more) interrupt signals, each of which comprises an interrupt factor and an interrupt level.

The status registers 101, 201 and 301
Are the interrupt mask fields and interrupt signals 400 and 40 of at least the task using the register file.
It comprises an N + 1 bit interrupt factor field corresponding to each of 1 to 40N.

Here, the interrupt factor field includes a plurality of bits corresponding to each of the interrupt factors and indicating whether the task is a task for processing the interrupt factor or not. Also,
The interrupt mask field has a function of masking an interrupt level for an interrupt factor.

Numeral 30 denotes a register file switching means. When the interrupt level for the interrupt factor is higher than the interrupt mask field of the status register in the currently selected register file based on the occurrence of the interrupt factor, a plurality of register file switching means 30 are provided. The bit corresponding to the generated interrupt factor is scanned in the interrupt factor field of all the status registers in the register file to detect the register file used by the task for processing the interrupt factor, and the detected file is switched to the detected register file.

Reference numeral 31 designates a register file to instruct the selection means 10 and 20 which register file among the register files 100, 200 and 300 is to be selected.

Reference numerals 103, 203 and 303 are an interrupt mask field and an interrupt factor field of the status registers 101, 201 and 301, respectively.

In FIG. 1, the information processing apparatus of the present invention
The instruction is executed as follows. The instruction is read from the memory by using the PC (program counter) in the register file specified from the register files 100, 200, and 300 by the register file specification 31 as the instruction address. The read instruction is decoded by an instruction decoder (not shown), and further controlled and executed by a sequencer (not shown).

The registers read out by the instruction to be executed are stored in register files 100, 200 and 3
00, specified by the register file specification 31;
The read data is output to the data buses 21 and 22 by the selecting means 20.

The data buses 21 and 22 are connected to a computing unit (not shown) or a data fetch unit (not shown), and perform an operation or write to a memory according to an instruction to be executed.

Further, the registers to be written in accordance with the instruction to be executed are similarly stored in the register files 100 and 20.
The data bus 11 is designated by the register file designation 31 from 0 and 300, and the data bus 11 is selected by the selection means 10 and written into the register in the selected register file. The data bus 21 is connected to the output of the arithmetic unit or the data read from the memory.

Therefore, three register files 100,
By selecting and using the register file used by the instruction sequence being executed from 200 and 300, it is possible to hold the execution state of the three tasks.

Here, three register files 100,
Switching between 200 and 300 can also be performed by executing an instruction to change the state of the register file switching means 30 as in the past, and the register file switching means 30 determines which register file is to be selected by the instruction. The configuration is also changed.

Therefore, three register files 100,
It has a feature of a conventional information processing apparatus that can execute the three tasks assigned to 200 and 300 while switching at high speed.

Here, the interrupt 40 which is a feature of the present invention is described.
The operation of switching register files according to 0, 401 to 40N will be described.

FIG. 2 is a flowchart showing a register file switching operation by an interrupt.

In FIG. 2, reference numeral 1 denotes an interruption detecting step for detecting occurrence of an interruption. 2 is an interrupt level detecting step for detecting that the level of the generated interrupt is higher than the interrupt mask of the status register of the currently selected register file.

Reference numeral 3 denotes a register file detecting step of scanning the interrupt factor fields of all the status registers and detecting a register file for processing the generated interrupt.

Step 4 is a register file switching step for switching to the detected register file.

In the following, for the sake of specific description, the case where N is 7, that is, the case where there are eight interrupts 400 to 407 is limited. It is clear that this limitation does not limit the invention. Also, there are seven interrupt levels.

Therefore, the status registers 101 and 201
And 301 each have an 8-bit interrupt factor field corresponding to the number of interrupts and a 3-bit interrupt mask field which is the minimum number of bits representing seven levels of interrupt levels. The interrupt factor field corresponds to the interrupt 400 in order from bit 0.

First, it is assumed that each status register is set as shown in (Table 1).

[0035]

[Table 1]

Therefore, the task A using the register file 100 has an interrupt mask of 1 and an interrupt of 4
00 and 402 are set to be processed. Also,
Task B using the register file 200 has an interrupt mask of 2 and is set to process interrupts 403 and 404. Further, the task C using the register file 300 has an interrupt mask of 5, and is set to process interrupts 401, 405 and 407.

For the sake of explanation, the interrupt level is 0
Is the highest order, 6 is the lowest order, and 7 indicates that no interrupt factor has occurred.

Further, register file switching means 3
0 indicates that the register file 200 is selected.
That is, the instruction fetch is performed using the PC in the register file 200, and the execution of the fetched instruction is performed using the register file 200. Since the status register 201 is selected, the current interrupt mask is 2. Therefore, the interrupt level of 0 or 1 is accepted.

In this state, the interrupt factor indicated in the interrupt factor field of the status register 101 in the currently unselected register file 100 indicates that the interrupt processing is to be performed (that is, "1" in the interrupt factor field of the status register 101). Interrupt cause 40 corresponding to the bit of ""
0 and 402) will be described.

(1) Interrupt 402 occurs at level 1 (interrupt 402 indicates 001) (2) Interrupt 402 is higher than interrupt level of status register 201 currently selected (3) Interrupt corresponding to interrupt 402 The cause bits are detected for all the state registers. The interrupt cause bit for the interrupt 402 of the scan state register 101 detects "1". (4) The register file 100 is selected.
The register file 10 to which the task A that processes the interrupt 402 is assigned by the four steps shown in FIG.
Can be switched to zero.

In this example, if the priority of the task A using the register file 100 that processes the interrupt 402 is higher than the priority of the task B using the register file 200, the interrupt mask field of the status register 201 is changed to the interrupt 402. , It is possible to control the priority between tasks.

In the initial state, the status register 2
01 is set to 1 in step (2), the currently selected status register 20
Since the level of the interrupt 402 is not higher than the interrupt mask field of No. 1, the register is not switched. This is because the NO route is selected in step 2 of FIG. In this case, the task A that processes the interrupt 402 is controlled so that the priority of the task A is lower than that of the task B currently being executed.
It is understood that it is possible to control the priority between tasks simply by setting the interrupt mask field of “1” higher than the interrupt level of the interrupt 402.

Therefore, according to the present embodiment, the priority of a task can be controlled, and the priority of a task can be changed by rewriting the interrupt mask field of the status register. It is.

(Embodiment 2) FIG. 3 is a block diagram of an information processing apparatus according to a second embodiment, and in FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 3, reference numeral 1000 denotes an instruction execution unit for executing an instruction. In addition to at least the part of the information processing apparatus shown in FIG. Means 1
020.

The processing unit activation means 1020 selectively activates the processing unit specified by the activation instruction by the activation signal 1021 when the activation instruction of the processing unit is executed.

The interrupt level designating means 1010 is selectively operated by the processing unit starting means 1020.
When starting 0, 1200 to 1N00, the processing unit to be started is notified of the interrupt level at the time of completion of execution by the interrupt level designation 1011.

The N + 1 (N is an integer of 0 or more) processing units 1100, 1200 to 1N00 are activated by the instruction execution unit, and the completion of the processing is notified to the instruction execution unit by interrupts 400, 401 to 40N. Notify.

The interrupt level designating means 1010 provides, for example, in a processing unit start instruction, a field indicating interrupt level information indicating an interrupt level when the processing unit to be started is completed. Specify this field as an interrupt level at execution 10
11 can be performed.

Here, the operation of the present invention will be described. When the instruction execution unit executes a processing unit start instruction requesting the execution processing unit to start, the instruction execution unit sets the processing unit specified by the processing unit start instruction to the processing unit start signal 1.
021, and at the same time, the interrupt level specifying means 1010
Notifies the interrupt level at the completion of the execution of the processing unit through the interrupt level designation 1011. After executing the processing unit activation instruction, the instruction execution unit continues the processing.

Upon completion of the execution, the processing unit that has been started up has an interrupt level designation 1 when the processing unit is started up.
The interrupt level and the interrupt factor designated by 011 are output to an interrupt (any one of 400, 401 to 40N) connecting the processing unit and the instruction execution unit.

Then, the register file switching means 30 which detects the interrupt performs the operation described in the first embodiment, and switches the register as required.

As a result, not only can the interrupt mask field of the status register be changed, but also the interrupt level can be changed by an instruction, so that the task priority can be changed more flexibly.

The number of processing units activated by the processing unit activation instruction may be one or more.

In the above description, the interrupt level specifying means 1010 has been described as notifying the interrupt level to the processing unit to be activated based on the interrupt level field in the processing unit activation instruction. It is also possible to notify the interrupt level to the processing unit to be activated based on the interrupt mask field of the status register in the register file which is selected at the time, whereby the priority of the task can be dynamically determined according to the state of the information processing apparatus. Can be changed to

The processing unit which sets the bit corresponding to the interrupt output by the processing unit to be activated in the interrupt factor field of the status register in the selected register file to "1" by executing the processing unit activation instruction. By providing a start instruction, the number of instructions can be reduced.

[0057]

As described above, according to the present invention, the task switching by register file switching is performed using the interrupt factor and the interrupt level by holding the interrupt factor field and the interrupt mask field in the status register in each register file. By changing the interrupt factor field of the status register during the execution of the task, the task scheduling process can be performed with a small processing overhead.

Further, according to the processing unit start instruction,
Alternatively, based on the interrupt mask field of the status register selected at the time of execution of the processing unit start instruction, specify the interrupt level at the time of completion of execution of the processing unit to be started, and specify the interrupt level specified at the time of completion of execution of the processing unit. By interrupting by level, more detailed scheduling can be made possible.

The processing unit activation instruction sets the bit corresponding to the interruption factor generated by the processing unit activated by the processing unit activation instruction in the interrupt factor field of the selected status register. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing a register file switching operation by an interrupt according to the embodiment;

FIG. 3 is a block diagram of an information processing device according to a second embodiment of the present invention.

[Explanation of symbols]

 30 register file switching means 100, 200, 300 register file 400, 401 to 40N interrupt 1000 instruction execution unit 1100, 1200 to 1N00 processing unit

Claims (5)

[Claims] An information processing apparatus having a plurality of interrupt causes and interrupt levels, comprising at least a plurality of register files, selecting one of the register files, and using the contents of the register file to select a plurality of register files. An instruction execution unit that executes the task in a time-division manner, and whether or not the task is included in each of the plurality of register files and at least corresponds to each of the interrupt causes and processes the interrupt cause. And a plurality of status registers each comprising an interrupt mask field for masking the interrupt level for the interrupt factor, and an interrupt level for the interrupt factor based on the occurrence of the interrupt factor. Is the interrupt of the status register in the register file currently selected If it is higher than the mask field, scan the bit corresponding to the generated interrupt factor in the interrupt factor field of all the status registers in the plurality of register files, and use the task for processing the interrupt factor. An information processing apparatus comprising: a register file switching unit that detects the register file and switches to the detected register file. 2. A plurality of processing units which are activated by a processing unit activation instruction and notify completion of execution of the activated processing by an interrupt, and processing unit activation means for selectively activating each of the processing units. And an interrupt level designating unit for designating an interrupt level at the time of completion of the processing to the processing unit when the processing unit is activated by a processing unit activation instruction. Upon completion, an interrupt level specified by an interrupt level specifying unit is generated, and the register file switching unit performs register file switching based on the interrupt factor generated by the processing unit and the interrupt level. Item 10. The information processing apparatus according to Item 1. 3. An information processing apparatus according to claim 2, wherein said interrupt level specifying means specifies an interrupt level based on interrupt level information in said processing unit activation instruction. 4. The interrupt level specifying means specifies an interrupt level based on information in the interrupt mask field of the status register in the register file selected when the processing unit start instruction is executed. 3. The information processing apparatus according to claim 2, wherein: 5. The execution of the processing unit start instruction generates a processing unit selectively activated by the processing unit start instruction in the interrupt factor field of the status register in the selected register file. 3. The information processing apparatus according to claim 2, wherein a bit corresponding to the interrupt factor is set.