JPH10207717A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain high speed task switching. SOLUTION: A sequencer 55 controls the transfer of data between a context saving memory 3 and a data memory and a register file 1 according to the contents of a present task number register 60, next task number register 57, and previous task number register 61 by a start signal from a CPU, and saves/ restores a context. A new task to be switched at the time of requesting task switching is decided by a task permission flag 56 and the present task number register. The register file is constituted of two pairs of register sets in the same constitution, and switched by a register set A using flag 63. A register writing control part writes a context in the register set to be used by the next task, and a register reading control part 68 reads the register set to be used by the present task.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer that executes a plurality of tasks while switching the tasks.

[0002]

2. Description of the Related Art In recent years, microcomputers have been used in all types of equipment, and have been applied to more complex controls in a wider field with the improvement in processing capability. In embedded applications, advanced functions such as multitask processing are desired so that they can be applied to more complicated controls.

FIG. 14 is an explanatory diagram of a microcomputer having a multitasking function in the first conventional example. In FIG. 1, a CPU 10 includes an operation unit 11 and a register set 12.

The operation unit 11 executes tasks one by one,
The register set 12 holds data necessary for task execution.

[0005] The memory 13 has a context block 14 which is an area for saving a context (data unique to a task, such as data of a register set, contents of a PC, contents of a PSW, which is changed by execution of a task) for each task. In the figure, a context save area for tasks 1 to 3 is shown in the context block 14.

[0006] The tasks in the first conventional example are managed by software (OS). For example, when switching from task 1 to task 2, upon receiving an event indicating task switching (such as a timer interrupt), the OS first saves the context of task 1 from the CPU 10 to the memory 13, and then transfers the context from the memory 13 to the CPU 10. After the context of task 2 is returned, execution of task 2 is started.

As described above, in the first conventional example, since multitasking is realized by software (OS), there is an advantage that the hardware scale can be reduced.

FIG. 15 is an explanatory diagram of a microcomputer having a multitasking function in the second conventional example. Referring to FIG. 1, a CPU 20 includes an operation unit 21, a register file 22, a register set switching unit 23, and a control unit 24.

The arithmetic unit 21 executes tasks one by one,
The register file 22 includes a plurality of register sets that hold data necessary for executing a task.

[0010] The register set switching unit 23 makes the register set corresponding to the currently executed task valid.
Only this valid register set is used for the arithmetic unit 21. The control unit 24 controls task switching.

The memory 25 has a context save area excluding data of a register set. The task in the second conventional example is managed by hardware.
For example, when switching from task 1 to task 2, the control unit 24 causes the register set switching unit 23 to enable the register set corresponding to task 2 upon receiving an event instructing task switching (such as a timer interrupt). In addition to the instruction, the contents of the PC of
The contents of W and the like are saved in the memory 25, and the contents of the PC of the task 2, the contents of the PSW, and the like are returned to the arithmetic unit 21. afterwards,
The operation unit 21 executes the task 2 using the valid register set 2.

As described above, in the second conventional example, since multitasking is realized by hardware, there is an advantage that task switching is fast.

[0013]

However, according to the above conventional example, there is a problem that it is not suitable for multitask management in a microcomputer for embedded use.

According to the first conventional example, the task is switched and the context is saved and restored by software, so that the switching speed is slow, and it is not suitable for a microcomputer which is embedded in a control requiring a real-time property. According to the second conventional example,
Since the same number of register sets as the number of tasks are required, and the task switching is realized by hardware, the hardware scale of the control unit is increased. As a result, the cost is high, and the microcomputer is not suitable for embedded microcomputers.

The present invention has been made in consideration of the above problems, and has as its object to provide a microcomputer that switches tasks at high speed without increasing cost.

[0016]

According to a first aspect of the present invention, there is provided a microcomputer for executing a plurality of tasks while sequentially switching the tasks. A set of at least two or more registers to be used, a first memory for holding context data of tasks not being executed,
A second memory used by U for data processing, and register switching means for switching the register set when context data of a task to be executed next is returned to the register set from the first memory and the second memory. A register connected to the register set, the first memory, and the second memory, for transferring a part of the context data of the task to the second memory when the task is switched, and using the register before switching; Transfer means for saving the contents of the set to the first memory during execution of the new task.

According to a second aspect of the present invention, in the first aspect, the transfer means starts operation in response to a start request from a CPU, a read means for reading data of a register set used by a task, and a register read. Writing means for writing data read by the means to the first memory; memory reading means for reading context data of a task to be executed next from the first memory; and data read by the memory reading means for next execution. Register writing means for writing to a register set used by a task; a first address register connected to the sequencer for specifying an address to be accessed by the memory writing means or the memory reading means; and a first address register connected to the sequencer, Address of memory 2 A second address register for a constant,
A register set number specification unit connected to the sequencer and specifying a register set used by the task.

According to a third aspect of the present invention, in the second aspect, the transfer means includes a current task number register for specifying a number of a task currently being executed, and a next task number register for specifying a number of a task to be executed next. Transferring the contents of the current task number register to the previous task number register based on the state of the sequencer and a previous task number register that specifies the number of the previously executed task; Task number control means for transferring the current task number to the current task number register.

According to a fourth aspect of the present invention, in the first aspect, the transfer means is connected to the register set and the first memory, and is connected to the second memory via a data bus. Has a bus.

According to a fifth aspect of the present invention, in the first aspect, the transfer means has a pre-assigned specific address of the second memory for storing a part of the context.

According to a sixth aspect of the present invention, in the first aspect, the transfer means has a stack area allocated to the second memory for storing a part of a context.

According to a seventh aspect of the present invention, in the sixth aspect, the register set has a stack pointer for holding an address different from the last position of the stack after storing the context in the stack area of the second memory.

An eighth aspect of the present invention is a microcomputer which executes a plurality of tasks while sequentially switching the tasks,
At least two or more register sets, one of which is used for executing a task, a first memory for holding context data of a task which is not being executed, and a second memory which is used for data processing by the CPU. A memory, register switching means for switching a register set when context data of a task to be executed next is returned from the first memory and the second memory to the register set, and the register set and the first memory A part of context data of a task is transferred to the second memory when a task is switched, and the contents of a register set used before the task is switched during execution of a new task. Transfer means for saving to the first memory, micro-control means for processing instructions, and the microphone A CPU for outputting a control signal output from the control means and an internal bus; a register reading means inside the CPU for reading the register set to the internal bus by the microcontroller; a control signal for the CPU and the internal bus; Connected to the CPU and provided with the same register set as the CPU;
And an extension designating means for notifying that it is connected to U and stopping the operation of the reading means.

According to a ninth aspect of the present invention, there is provided the method of
U comprises a data path section for processing data and a control section for controlling the data path, and the control section is arranged in a direction perpendicular to the data processing flow of the data path section, and is input to the data path section and the extension section. A data path control signal for controlling the data path, and a data processing flow of the data path section, which is arranged in the horizontal direction and is output from the control section, and then controls the expansion section to be input to the expansion section. It has an extension control signal.

According to a tenth aspect of the present invention, there is provided a microcomputer which executes a plurality of tasks while sequentially switching the tasks, and has an n-bit first flag indicating whether activation of the n tasks is permitted or prohibited.

According to an eleventh aspect of the present invention, in the tenth aspect, an m-bit indicating a task number to be executed next, and a power of 2 for exponentiating m is equal to or less than the value of the first flag. And a task permission flag control unit that sets a corresponding bit of the first flag by setting a desired task number in the second flag.

[0027]

FIG. 1 is a block diagram showing a main configuration of a microcomputer according to an embodiment of the present invention. The microcomputer of the embodiment includes a register file 1, a CPU 2, a context saving memory 3, a memory 4, and a transfer unit 5.

Register file 1 contains register set A
(GRA) and register set B (GAB).
The register sets A and B are alternately switched every time the task is switched, and one of them is always used for the CPU 2 to execute the task.

The CPU 2 executes a plurality of tasks while switching them. The tasks executed by the CPU 2 are switched in ascending or descending order of task numbers based on the task permission flag of the transfer unit 5 every time an event instructing task switching occurs. The task switching event is, for example,
Examples include a periodic timer interrupt, a serial transfer interrupt, and a task switching instruction.

The context save memory 3 is a memory for saving information on tasks that are not being executed by the CPU 2. The task information is a context including contents of a register set, contents of a processor status word (PSW), contents of a program counter (PC), and the like.

The memory 4 stores data processed by the CPU 2 in executing the task. Each time a task switching event occurs, the transfer unit 5 returns the context of the task to be executed next by the CPU 2 from the context save memory 3 to a register set that is not in use, and switches the register set. CP using switched register set
While U2 is executing the next task, the contents of the register set being used before switching are saved in the context saving memory 3.

FIG. 2 is a block diagram showing a more detailed configuration including the internal bus of the transfer unit of the microcomputer shown in FIG. The transfer unit 5 includes a transfer control unit 51, an ABUS
501, BBUS502, CBUS503, ARAMB
US504 and DRAMBUS505.

The transfer control unit 51 controls each bus of the transfer unit 5, a memory connected to each bus, a register file, and the like. The transfer control unit 51 stores the address when the CPU accesses the context save memory 3 in the ARAMBUS50.
Input from 4. Further, a specific address at the time of context saving is output to the ABUS 501.

FIG. 3 is a block diagram showing a more detailed configuration of the microcomputer shown in FIG.

As shown in the figure, the microcomputer includes a register set A101 and a register set B10.
2, incrementer 201, instruction address buffer 20
2. Prefetch counter 203, instruction fetch buffer 204, processor status word 205, instruction buffer 206, instruction register 207, status register 208, PLA 209, microinstruction register 21
0, ALU 211, ALU output buffer 212, operand address buffer 213, store buffer 214,
Load buffer 215, bus controller 216, timing generator 217, ROM 401, RAM 402, transfer controller 51, task timer 52, bus switch 53, RAM
Address generation unit 54, sequencer 55, task permission flag 56, next task number register 57, context save memory address register 58, ABUS 501, BBU
S502, CBUS503, ARAMBUS504, D
RAMBUS505, AROMBUS506, DROM
BUS507 and COREBUS508.

Register set 101 and register set 1
02 has the same register configuration, and each has an 8-bit data register (D0, D1, D2, D3) and 1
A 6-bit width address register (A0, A1);
It has a bit-width stack pointer (SP) and a selector for selecting and outputting these data. A circuit including an incrementer 201, an instruction address buffer 202, a prefetch counter 203, and an instruction fetch buffer 204 is an instruction prefetch preparation unit that sequentially prefetches instructions from the ROM 401.

The processor status word 205 is A
The operation flag of the LU 211 and the interrupt status of the CPU 2 are stored.

The instruction buffer 206 is an instruction queue for holding a plurality of instructions prefetched by the instruction prefetch preparation unit.

The circuit including the instruction register 207, the status register 208, the PLA 209, and the micro instruction register 210 is an instruction control unit that decodes an instruction supplied from the instruction buffer 206 and controls execution. When an event for instructing task switching occurs, the instruction control unit performs control to save and restore a part of the context of the task and control to notify the transfer control unit 51 of the start of transfer. In the present embodiment, the event is an interruption by the task timer 52. Further, the instruction control unit includes:
It controls input / output of data of US501 and BBUS502.

ALU 211, ALU output buffer 21
2. The circuit including the operand address buffer 213, the store buffer 214, and the load buffer 215 is an instruction execution unit that executes an instruction under the control of the instruction control unit.

The ROM 401 and the RAM 402 correspond to the memory 4 shown in FIG. 1, and have a plurality of task programs, a stack area, and a task start address saving area. The program of each task is stored in the ROM 401, and a stack area and a task start address saving area are provided in the RAM 402.

The CPU internal bus is ABUS501, BBU
S502, CBUS503, CPU
External memory bus is ARAMBUS504, DRAM
BUS505, AROMBUS506, DROMBUS
507 and COREBUS508.

The ABUS 501 and the BBUS 502 mainly transmit data to be accessed for the register file 1.

The CBUS 503 mainly transmits data to be accessed to the context save memory 3.

ARAMBUS504 and DRAMBUS5
Reference numeral 05 mainly transmits an address and data for accessing the RAM 402, and AROMBUS 506 and DROMBUS 507 each transmit an address and data for mainly accessing the ROM 401.

The core bus 508 mainly transmits addresses and data for accessing registers and the like included in the peripheral functions of the microcomputer.

The task timer 52 is a timer for measuring the time of the task being executed by the CPU. The timer is set at the start of the task execution, and the value of the timer is decremented at regular time intervals. When the content of the task timer reaches zero, the CP
A task switching event interrupt is generated for U2. The value set in the task timer is set in the context save memory in advance. When the task is switched, the content of the task timer is always zero, so that the content is not saved in the context save memory.

The bus switch 53 includes a DRAM BUS 50
5 is a buffer for transferring data between the CBUS 503 and the CBUS 503.

The RAM address generation unit 54 generates an address of the RAM 402 for storing a part of the context in which the CPU saves and returns when the task is switched.

The sequencer 55 outputs a signal for controlling the CBUS 503 and updating the registers in the transfer control unit in response to a start request from the CPU, and saves and restores the task context.

The task permission flag 56 is composed of the same number of bits as the number of tasks executed by the CPU, and specifies whether the execution of the task corresponding to each bit is permitted or prohibited.

The next task number register 57 stores the number of the next task to be switched and executed when a task switching event occurs. The content of the register is based on the content of the task permission flag 56 by the sequencer. Can be determined.

The task permission register 56 and the next task number register 57 are also connected to the COREBUS 508, and the contents can be read or written by executing a program of the CPU.

The context save memory address register 58 stores an address for accessing the context save memory 3 and is referred to when the sequencer 55 accesses the context save memory.

FIG. 4 is a block diagram showing a more detailed configuration of the transfer controller 51 of the microcomputer of FIG. 2 and a more detailed data configuration of the context save memory 3. In the figure, the task permission flag control section 59 decodes the task number stored in the next task number register 57 and sets the bit corresponding to the task number of the task permission flag 56 to 1. When the task permission flag is changed by an instruction, the task permission flag
The data of REBUS 508 is set in the task permission flag 56.

The current task number register 60 stores the number of the task currently being executed by the CPU. The previous task number register 61 stores the number of the task that was being executed before the CPU switched to the task that is currently being executed.

The task number control section 62 receives the contents of the task permission flag 56, the contents of the current task number register 60, and the register rewrite signal output by the sequencer 55, and receives the next task number register 57, the current task number register 60,
The contents of the previous task number register 61 are updated.
The timing of the rewrite signal output by the sequencer 55 is indicated by an arrow in FIG. FIG. 11 shows the contents of the task number control unit updating the next task number register.

According to FIG. 9, it is state 0 of the sequencer 55 that the previous task number register 61 is rewritten, as indicated by the arrow, and the next task number register 57 and the current task number register 60 are rewritten. Is state 9 of the sequencer 55.

The register set A use flag 63 indicates that the CP
U is a flag for specifying a register set to be used for task execution. When the register set A use flag is 1, the register set A is used, and when it is 0, the register B is used.

The memory control unit 64 controls reading and writing of the context saving memory 3 and reading and writing of the register file 1. The memory control unit 64 includes a context save memory write control unit 6 that controls writing of data to the context save memory 3.
5 and a context saving memory read control unit 6 for controlling reading of data from the context saving memory 3
6, a register write control unit 67 that controls writing of data to the register file, and a register read control unit 68 that controls reading of data from the register file.

The context saving memory 3 shown in FIG.
The figure shows a configuration for handling up to four tasks, and has a capacity of 64 bytes. The 64 bytes are divided into four, and the stack pointer (SP) and the data registers (D0, D1, D2, D
3), address registers (A0, A1), processor status word (PSW), task timer (TT),
Save the operand address buffer (OAB). 1
In a 6-bit register, the lower 8 bits are saved in the lower address. In this embodiment, each of the divided areas has a 2-byte spare save area.

FIG. 5 is a flowchart of a process at the time of task switching. In the figure, “CPU, transfer unit”,
The “transfer unit” indicates a flow in which the CPU 2 and the transfer unit 5 perform processing synchronously and in parallel at the time of task switching, and a flow in which the transfer unit 5 performs processing alone.

The flowchart in FIG. 11 shows a flow in which a task switching request is generated while the CPU 2 is executing the task 1 using the register set A, and the task 2 is switched to the task 2. When a task switching request is generated, the CPU 2 temporarily stops the task being executed, and shifts to a task switching process. In the task switching, the CPU 2 is processed by the PLA 209 in the same manner as the interrupt processing, and the transfer unit 5 is processed by the sequencer 55.

FIGS. 6, 7, and 8 are timing charts of the task switching process. In the figure, timings (T2, T1), IAB202, PFC203,
IR207, MIR210, ABUS501, BBUS
502, CBUS503, ALU211 and ALB21
2, OAB213, STB214, LDB215, AR
The contents of AMBUS 504 and DRAMBUS 505 are shown for each cycle. In the figure, the right direction is the time axis.

Further, the shading of ABUS, BBUS and CBUS indicates that the transfer is controlled by the transfer unit 5.

FIG. 9 is a diagram showing the operation of each unit by the sequencer 55 of the transfer unit 5. For each state and timing of the sequencer 55, the address (address), data (data), and transfer direction of the context save memory 3 are shown. (R / W), bus (ABUS, BBUS, CBU)
S), task number registers (PRVTSK, CRNTT)
SK, NEXTTSK), and the state of the register file A use flag (GRARUN) are shown in FIG.

W in the transfer direction indicates writing to the context saving memory, and R indicates reading from the context saving memory.

In the figure, parentheses in the bus column indicate that the content output to another bus is being transferred. “Old” indicates the context of the task that was being executed when the task switching request occurred, and “ned”
"w" indicates the context of the task newly switched by the task switching request. "Crnttsk", "nextsk", "prvt" in the column of "address"
sk ”is the current task number register CRNTTS.
K60, a value obtained by multiplying the contents of the next task number register NEXTTSK57 and the previous task number register PRVTSK61 by 16, for example, “crnttsk +
“12” indicates that the value “28” obtained by adding 12 to the value obtained by multiplying the content “1” of CRNTTSK by 16 is used as the address of the context save memory.

The states and timings shown in FIG.
6A to FIG. 6C. Therefore, for example, the state 0 in FIG. 7 corresponds to the cycle 0 in FIG. 6A, and the timing T2 and the timing T1 correspond to T0 in FIG.
2 corresponds to state 1 of T1, and state 1 of T1.

FIG. 10 is a diagram showing a configuration of a specific area of the RAM 402 for saving the program counter of each task. In this embodiment, an area for saving the contents of the program counters of the four tasks is provided in a specific area of 8 bytes from address 0 to address 7.

Hereinafter, the task switching process will be described in detail according to states with reference to FIGS. 5, 6, 7, 8 and 9.

<State 0> The CPU 2 determines the contents of the OAB 213 at the time of the task switching request at timings T2 and T2.
1 outputs to each BBUS.

Since the content of the current task number register is 1, the transfer section 5 outputs the lower 8 bits of the PC save address 2 to the ABUS at timing T2 and the upper 8 bits to the ABUS at timing T1. C
The PU transfers the contents of the OAB output to the BBUS to the CBUS, and writes the contents to the addresses 28 and 29 of the context save memory (step 51). Also, the contents of CRNTTSK are transferred to PRVTSK.

The save address output to ABUS is C
The PU transfers the data to the ALB 212 through the ALU.

<State 1> The CPU transfers the save address stored in the ALB to the IAB 202, and
Output to ARAMBUS through ROMBUS. Also, the contents of the PFC 203 are output to the ABUS and the constant "1" is output to the BBUS, and the return address (program counter value) of the task 1 being executed is calculated by the ALU. The lower 8 bits of the calculation result are transferred to STB 214 and output to DRAMBUS at timing T2. The upper 8 bits of the calculation result are stored in ALB. Therefore,
The CPU returns to address 2 of the RAM 402 and writes the lower 8 bits of the address (step 52).

The transfer section does nothing in state 1. The calculation of the return address is controlled by the prefetch amount of the instruction buffer 206 at the time of calculation, but a detailed description is omitted because it is not related to the present invention.

<State 2> The CPU increments the content of IAB used in cycle 1 by +1 by the incrementer 201.
Then, while outputting to ARAMBUS through AROMBUS, the upper 8 bits of the return address of task 1 calculated in cycle 1 are output to DRAMBUS,
The data is written to address 3 of step 2 (step 52). Also, the contents of the PSW of task 1 are output to ABUS.

The transfer unit transfers the contents of the PSW output to the ABUS at the timing T2 to the CBUS, and writes the contents into the address 26 of the context save memory (step 53).
At timing T1, address 32 of the context save memory is read. The register set accessed by the transfer unit uses a register set indicated by a value obtained by inverting the content of the register set A use flag. Therefore, in the example of FIG. 7, the transfer unit accesses the register set B between the state 2 and the state 8 and accesses the register set A between the state 9 and the state 14.

<State 3> The CPU returns to the RAM 40 in which the return address of the task 2 output to the ABUS is saved.
2 is stored in the ALB through the ALU.

Based on the content “2” of the next task number register, the transfer unit sets the lower 8 bits of the address 4 of the RAM 402 in which the return address of the task 2 is saved to the timing T2 and the upper 8 bits to the timing T1. At the timing T1 of the previous cycle, and outputs the SPL of the task 2 read at the timing T1 of the previous cycle.
2 to output to CBUS. At the timing T2, the address 33 of the context save memory is read, and is output to the CBUS at the timing T1. S output to CBUS
The contents of PL and the contents of SPH are transferred to BBUS,
It is stored in SPL and SPH of register set B (step 54).

<State 4> The CPU transfers the address stored in the ALB to the IAB,
The data is output to ARAMBUS through the US, and the lower 8 bits of the return address of task 2 are read from address 4 of RAM 402 and stored in LDB.

At the timing T1 of the previous cycle, the transfer unit reads D0 read from the address 34 of the context save memory.
Is output to the CBUS and stored in D0 of the register set B through the BBUS, and at the timing T1
Read the contents of D1 at address 35 of the context save memory, output it to CBUS, and store it in D1 of register set B through BBUS (step 54).

<State 5> The CPU outputs the contents of the LDB to the ABUS, stores it in the ALB through the ALU, and outputs an address obtained by incrementing the contents of the IAB of the previous cycle by an incrementer to the ARAMBUS.
The upper 8 bits of the return address of task 2 are read from address 5 of M401 and stored in LDB (step 55).

The transfer unit reads the contents of D2 and D3 from the context save memory in the same manner as in the state 4, and stores them in D2 and D3 of the register set B (step 54).

<State 6> The CPU stores the contents of the lower 8 bits of the return address of task 2 stored in the ALB in IAB.
And the contents of the LDB as AB
Output to US and output to ABUS again through ALU. The CPU stores the upper 8 bits of the return address of task 2 output to the ABUS to the ALB through the ALU.

The transfer unit reads the contents of the lower 8 bits and the contents of the upper 8 bits of A0 from the context save memory as in state 4,
0L and A0H are stored (step 54).

<State 7> The CPU sets the contents of the upper 8 bits of the return address of task 2 stored in the ALB to IAB.
The contents of IAB are output to AROMBUS, an instruction is fetched from the return address of task 2 and stored in IFB (step 55).

The transfer unit reads the contents of the lower 8 bits and the contents of the upper 8 bits of A1 from the context save memory in the same manner as in state 4,
1L and A1H respectively.

<State 8> The CPU transfers the contents of the PSW of task 2 output to BBUS to the ABU through the ALU.
S, and store it in the PSW 205 (step 5).
6). The instruction fetched in the previous cycle is transferred to the instruction buffer 206, and the return address of the task 2 is set to +
Instructions are fetched continuously from the set address and stored in the IFB.

The transfer unit outputs the contents of the PSW of the task 2 read from the address 42 of the context save memory at the timing T1 of the previous cycle to the CBUS at the timing T2 and transfers it to the BBUS. The timing T
The contents of the address 43 read in step 2 are stored in the task timer 52 which determines the execution time of the task (step 57).

<State 9> The CPU stores the instruction of task 2 in the IR 207 and starts decoding the instruction.
ALU contents of OAB of task 2 output to BBUS
Is stored in the ALB (step 58).

The transfer section outputs the contents of the OABL of the task 2 read from the address 44 of the context save memory at the timing T1 of the previous cycle to the CBUS at the timing T2 and transfers it to the BBUS. Further, the content of the address 45 read at the timing T2 is output to the CBUS and transferred to the BBUS at the timing T1. Further, the contents of the next task number register NEXTTSK are transferred to the current task number register CRNTTSK, and NEXTT
Update the contents of SK.

The transfer unit further sets the register set A use flag 63 to “0”, and sets the register set used by the CPU for executing the task thereafter to the B side (step 5).
9).

<State 10> The CPU stores the content stored in the ALB in the OAB of the task 2, and executes the instruction of the task 2 independently of the transfer unit (step 61). Therefore, after the state 11, the operation of only the transfer unit will be described.

The transfer unit reads SPL and SPH, which are the contexts of task 1 at the time of the task switching request, from register set A, outputs them to CBUS, and stores them in addresses 16 and 17 of the context save memory (step 62). .

<State 11> The transfer unit performs state 10
Similarly to the above, D0 and D1, which are the contexts of task 1 at the time of the task switching request, are read from register set A, output to CBUS, and stored in addresses 18 and 19 of the context save memory (step 62).

<State 12> The transfer unit performs state 10
Similarly to the above, D2 and D3, which are contexts of task 1 when a task switching request occurs, are read from register set A, output to CBUS, and stored in addresses 20 and 21 of the context save memory (step 62).

<State 13> The transfer unit performs state 10
Similarly to the above, A0L and A0H, which are the contexts of task 1 when a task switching request occurs, are read from register set A, output to CBUS, and stored in addresses 22 and 23 of the context save memory (step 6).
2).

<State 14> The transfer unit performs state 10
Similarly to the above, A1L and A1H, which are the contexts of task 1 when a task switching request occurs, are read from register set A, output to CBUS, and stored in addresses 24 and 25 of the context save memory (step 6).
2).

FIG. 11 is a diagram showing an operation for the task number control unit 62 to determine the value of the next task number register NEXTTSK.

The value of the next task number register is determined by the contents of the task enable flag TSKEN56 and the current task number register C.
It is determined according to the contents of RNTTSK60. The LSB side of the task permission flag corresponds to the task with the lower number, and in this embodiment, the LSB side of the task permission flag has a higher priority. Therefore, when a plurality of bits of the task permission flag are set, the task with the lower number is executed first. For example, TSKEN = '001
1 'indicates that task 0 and task 1 are permitted. If the current task number is "0", the next task number is "1", and the current task numbers are "1", "2", and "3". Then, the next task number becomes “0”. In this example, since the bits 2 and 3 of TSKEN are “0”, the task 2
And that the permission flag of task 3 has been cleared by execution of an instruction or the like.

The same applies to other combination states, and a detailed description will be omitted. In the description of the above embodiment, the number of tasks is four, but the number is not limited to four.
Also, the address of the task save area in the context save memory or RAM is not limited.

In the above embodiment, only the program counter of the task context is saved in the RAM, but PSW and the like other than the program counter may be saved in the RAM.

In the above embodiment, the save area in the RAM is a specific address. However, the context may be saved in the stack area indicated by the SP of the task being executed. In this case, the value of the SP to be saved may be the value at the time when the execution of the task is stopped.

FIG. 12 is a diagram for explaining the connection between the transfer unit and the CPU according to the second embodiment of the present invention.

In the figure, a microcomputer core 1 is a CPU 2
The CPU 2 includes a microcontroller 21, a core register read control unit 22, and a buffer 23. The extension unit 4 includes a transfer unit 5 and two register sets GRA6 and GRB7. The transfer unit 5 includes an extension designation unit 51, an extension register read control unit 52, a buffer 53, and a buffer 54. The microcomputer core 1 and the extension unit 4 are ABUS and BBUS
Are connected by two internal buses. The microcomputer core 1 can execute an instruction even when the extension unit 4 is not connected. In the following, the extension unit 4
The operation when is connected will be described.

When the extension designating section 51 notifies the CPU 2 that the extension section 4 is connected to the microcomputer core 1, the core register read control section 22 receives the instruction from the microcontroller 21 to read the register set. ,
The buffer 23 is not operated, and nothing is read to ABUS and BBUS. On the other hand, the instruction to read the register set from the microcontroller is also issued to the extension register read controller 52. The operation of the transfer unit 5 included in the extension unit 4 is the same as that of the first embodiment of the present invention having two register sets, and thus the details are omitted.

FIG. 13 shows the second embodiment of the present invention shown in FIG.
FIG. 6 is a diagram for explaining a circuit arrangement in the example of FIG.

The microcomputer core 1 is composed of a data path section composed of a repetition of a circuit per bit and a control section composed of an irregular circuit. The data path section is controlled by a data path control signal output from the control section. Is done. When the direction of the flow of data processed in the data path unit is the X axis,
The data path control signal is in the Y-axis direction. By arranging the control section, the data path section, and the extension section in the Y-axis direction in order, and extending the data path control signal in the Y-axis direction by penetrating the data path section, the same data path control signal is transmitted to the data path section. Connect to extension.

The extension control signal for controlling the extension is output from the control unit in the X-axis direction, and then connected to the extension without passing through the data path.

Although not shown in FIG. 13, ABUS and BBUS extend from the data path section in the Y-axis direction and are connected to the extension section.

ABUS and BBUS may be once extended in the X-axis direction, like the extension control signal, and then connected to the extension.

[0113]

As described above, according to the first aspect of the present invention, there is an advantage that the context saving processing and the execution of the task after switching can be performed in parallel. In particular, in a microcomputer for embedded use, task switching can be performed at high speed even if there is a restriction on the hardware scale, so that real-time control is possible.

According to the invention of claim 2, in addition to the effect of claim 1, there is an effect that the context saving processing can be realized at high speed.

According to the third aspect of the invention, in addition to the effects of the first or second aspect, after a task switching request is generated, the next task to be executed can be determined. This makes it possible to flexibly cope with an application in which the order of task processing is controlled by a real-time OS or the like.

According to the fourth aspect of the present invention, in addition to the effect of the first aspect, there is an effect that the time of the parallel processing of the context saving processing and the execution of the task after switching is shortened.
As a result, the task waiting time in the case where the context save memory is accessed by the instruction during the parallel processing can be reduced.

According to the invention of claim 5, in addition to the effect of claim 1, there is an effect that the address calculation time of the memory for saving the context is shortened.

According to the invention of claim 6, in addition to the effect of claim 1, there is an effect that the time for the context saving processing is shortened.

According to the invention of claim 7, in addition to the effect of claim 6, there is an effect that the amount of context saving processing is reduced.

According to the invention of claim 8, there is an effect that the function of task switching can be easily added to the CPU and the function can be extended.

According to the ninth aspect of the present invention, in addition to the effects of the eighth aspect, the circuit arrangement can be made compact, and the chip area can be reduced.

According to the tenth aspect, there is an effect that the order of task switching can be flexibly changed by a program.

According to the eleventh aspect of the present invention, in addition to the effect of the tenth aspect, there is an effect that activation of an arbitrary task can be flexibly designated by a program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main schematic configuration of a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a transfer unit 5 in the embodiment.

FIG. 3 is a block diagram showing a more detailed configuration of the microcomputer in the embodiment.

FIG. 4 is a block diagram showing a more detailed configuration of a transfer control unit 51 and a more detailed data configuration of a context saving memory 3 in the embodiment.

FIG. 5 is a diagram illustrating processing C at the time of task switching in the embodiment.
Flowchart showing operations of PU 2 and transfer unit 5

FIG. 6 is a diagram illustrating processing C at the time of task switching in the embodiment.
Timing chart showing operation of PU 2 and transfer unit 5

FIG. 7 is a diagram illustrating processing C at the time of task switching in the embodiment.
Timing chart showing operation of PU 2 and transfer unit 5

FIG. 8 is a diagram illustrating processing C at the time of task switching in the embodiment.
Timing chart showing operation of PU 2 and transfer unit 5

FIG. 9 is a diagram showing an operation of each unit by a sequencer 55 of the transfer unit 5 in the embodiment.

FIG. 10 is a diagram showing a configuration of a specific area of a RAM 402 for saving a program counter of each task in the embodiment.

FIG. 11 shows a task number control unit 62 according to the embodiment.
The figure which showed the operation | movement for determining the value of the next task number register NEXTTSK.

FIG. 12 illustrates a connection between a transfer unit and a CPU of a microcomputer according to a second embodiment of the present invention.

FIG. 13 is a view for explaining a circuit arrangement in the embodiment.

FIG. 14 is an explanatory diagram of a microcomputer having a multitask processing function in the first related art.

FIG. 15 is an explanatory diagram of a microcomputer having a multitask processing function in the second related art.

[Explanation of symbols]

 1 register file 2 CPU 3 context save memory 4 memory 5 transfer unit 51 transfer control unit 52 task timer 53 bus switch 54 RAM address generation unit 55 sequencer 56 task enable flag 57 next task number register 58 context save memory address register 59 task enable flag Control unit 60 Current task number register 61 Previous task number register 62 Task number control unit 63 Register set A use flag 64 Memory control unit 65 Context save memory write control unit 66 Context save memory read control unit 67 Register write control unit 68 Register read control Department

Claims (11)

[Claims] 1. A microcomputer for executing a plurality of tasks while sequentially switching the tasks, wherein at least two or more register sets having the same register configuration, one of which is used for executing a task, and a context of a task not being executed. A first memory for holding data, a second memory used by the CPU for data processing, and a point in time when context data of a task to be executed next is returned from the first memory and the second memory to a register set Register switching means for switching the register set; the register set, the first memory, and the second
And transfers a part of the context data of the task to the second memory when the task is switched,
Transfer means for saving the contents of a register set used before switching to the first memory during execution of a new task. 2. The transfer means includes: a sequencer for starting operation in response to a start request from a CPU; reading means for reading data of a register set used by a task; Writing means for writing to the memory of the following; memory reading means for reading context data of a task to be executed next from the first memory; Writing means; a first address register connected to the sequencer for specifying an address to be accessed by the memory writing means or the memory reading means; and a first address register connected to the sequencer for specifying an address of the second memory. 2 address registers , Which is connected to the sequencer, the microcomputer according to claim 1, characterized in that it comprises a register set number designating means for designating the task register set in use. 3. The transfer means includes: a current task number register for specifying a number of a task currently being executed; a next task number register for specifying a number of a task to be executed next; and a number of a previously executed task. A task number for transferring the contents of the current task number register to the previous task number register and transferring the contents of the next task number register to the current task number register based on the state of the sequencer. 3. The microcomputer according to claim 2, further comprising control means. 4. The transfer means is connected to the register set and the first memory,
And an internal bus connected to the second memory via a data bus, wherein a CPU concurrently processes reading of a register set and writing to the first memory while the CPU is using the second memory. The microcomputer according to claim 1, wherein: 5. The microcomputer according to claim 1, wherein said transfer means stores a part of the context at a pre-assigned specific address of said second memory. 6. The microcomputer according to claim 1, wherein said transfer means stores a part of the context in a stack area allocated to said second memory. 7. The register set includes a stack pointer indicating a last position of a stack used by a CPU. The stack pointer stores a context in a stack area of the second memory, 7. The microcomputer according to claim 6, wherein different microcomputers hold different addresses. 8. A microcomputer for executing a plurality of tasks while sequentially switching the tasks, wherein at least two or more register sets having the same register configuration, one of which is used for execution of a task, and a context of a task not being executed. A first memory for holding data, a second memory used by the CPU for data processing, and a point in time when context data of a task to be executed next is returned from the first memory and the second memory to a register set Register switching means for switching the register set; the register set, the first memory, and the second
And transfers a part of the context data of the task to the second memory when the task is switched,
Transfer means for saving the contents of a register set used before being switched to the first memory during execution of a new task; microcontroller processing instructions; control signals output by the microcontroller; A CPU for outputting an internal bus; a register reading means inside the CPU for reading a register set to the internal bus by the microcontroller; a CPU connected to a control signal of the CPU and an internal bus;
A microcomputer comprising: extension means having the same register set as a PU; and extension designation means for notifying that the extension means is connected to the CPU and stopping the operation of the reading means. . 9. The CPU comprises a data path unit for processing data and a control unit for controlling the data path, wherein the control unit controls a data path control signal for controlling the data path and the extension unit. An extension unit control signal is output, and the data path control signal is arranged in a direction perpendicular to the data processing flow of the data path unit and input to the data path unit and the extension unit. 9. The microcomputer according to claim 8, wherein the microcomputer is arranged in a horizontal direction with the flow of data processing, outputted from the control unit, and then inputted to the extension unit. 10. A microcomputer for executing a plurality of tasks while sequentially switching the tasks, comprising: an n-bit first flag indicating whether activation of the n tasks is permitted or prohibited; A microcomputer that sequentially executes only the tasks for which task numbers are permitted in ascending or descending order of task numbers. 11. m indicating a task number to be executed next
A second flag, which is a bit and a power of 2 that is a power of m is equal to or less than a value of the first flag; and setting a desired task number to the second flag, 2. A task permission flag control means for setting a corresponding bit of a flag of 1 to directly start a desired task.
0. The microcomputer according to 0.