JPH02214938A - Data processor - Google Patents

Abstract

PURPOSE:To effectively use a stack area by comparing the value of a stack pointer with that of a limit pointer to detect the overflow of the stack area and changing the control procedures set for storage of a state. CONSTITUTION:The overflow of a stack area is detected by a comparator 30 when the coincidence is obtained between the value of a stack pointer 23 which points the place of the latest information written into a stack area set to a register file 6 and the value of a limit pointer 24 which points the limit address of the stack area. A microaddress controller 43 of a control part 4 selects the head address of a series of microinstruction systems set to save the information on the stack area into an external memory in the prescribed timing and gives the head address to a microaddress decoder 41. Thus the switch control is given to the control procedure set for storage of a state based on the detection of the overflow of the stack area. As a result, the stack area is effectively used up to its overflow state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stack area overflow detection technique and a technique for effectively utilizing the stack area. It relates to techniques that are effective when applied to microprocessors.

[Prior art]

When an operating program is branched due to the occurrence of an interrupt or exception handling in a data processing device such as a microprocessor, the various information that was used in the previous data processing must be made available again after the state is restored. must be saved in a predetermined stack area. Saving and restoring such information is performed by executing subroutine call instructions, return instructions, etc., but if there is a lot of information to save or branches in the operating program occur frequently, such instructions A non-negligible amount of time is spent on the execution. Therefore, a technology has been proposed that allocates a stack area in the built-in memory to shorten the memory access time required to save and restore information, thereby speeding up processing.For example, this technology is published by ASCII Co., Ltd. Monthly “ASCII” 19
It is described on pages 167 to 169 of the September 1988 issue.

By the way, since the storage capacity of the stack area allocated to the internal memory is limited, if necessary information cannot be saved to an unused area of the stack area, the nature of the stack area is changed to a first-in, last-out format. First, it is necessary to first save the information saved in the built-in stack area to an external memory or other memory area to create a free area in the built-in stack area. To do this, it is necessary to manage the storage capacity of the unused area in the stack area, that is, the remaining stack length. Conventionally, this management has been done by fixing the available stack length for each subroutine, and then adjusting the remaining stack length to the number of nested subroutines, that is, the remaining stack length. This has been done by determining the number of calls, or by comparing and determining the remaining stack length and the required stack length through software each time a subroutine call occurs.

[Problem to be solved by the invention]

However, with the method of managing the remaining stack length by the number of nested subroutines, the fixed and allocated stack length for each subroutine is not necessarily utilized to the maximum every time, and the built-in stack area cannot be used effectively. . Further, restrictions such as a fixed stack length available for one subroutine may complicate processing by the compiler.

Furthermore, the method of comparing and determining the remaining stack length and the necessary stack length in advance by software places a burden on the software, and the comparison and determination step takes time to execute a branch instruction such as a subroutine call instruction.

An object of the present invention is to provide a data processing device that can effectively utilize stack areas. Still another object of the present invention is to provide a data processing device that can reduce the time spent managing stack areas and further the time required for state saving processing.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the values of the stack pointer indicating the stackable address in the stack area allocated to the storage means and the limit pointer indicating the limit of the stack area are compared, and the value is determined based on the detection of a match. The data processing device is configured to detect an overflow of a stack area included in the storage means, and to enable the sequence control means to change the control procedure for saving the state based on the overflow detection.

Further, the data processing device is configured so that the control procedure for saving the state can be changed by the sequence control means based on the carry signal output from the arithmetic unit that updates the value of the stack pointer. You can also do it.

In each of the above data processing devices, the sequence control means is configured to save information previously saved in the stack area to the outside to form a free area in the stack area based on overflow detection or carry output. It can be configured to branch into control procedures.

When each of the above data processing devices is formed on one semiconductor chip, the storage means used as the stack area is built into the semiconductor chip, so the stack area can be accessed at high speed for saving and restoring the state. Furthermore, in order to speed up the process of changing the control procedure for saving the state, it is desirable to directly give an instruction to change the control procedure to the microaddress controller to branch the microflow.

[For production]

According to the above-mentioned means, the overflow signal of the stack area and the carry signal of the arithmetic unit for instructing to change the control procedure of the state saving process are not significant when the stack area of the storage means is completely or almost completely utilized. This enables effective use of the stack area. When using the carry signal of the arithmetic unit here, it is desirable to set the stack area so that the address pointed to by the stack pointer when the carry signal is determined to be significant matches the limit address of the stack area.

On the other hand, when a limit pointer is used, the limit of the stack area can be freely set on the storage means according to the information setting for the limit pointer.

Stack area overflow detection and arithmetic unit carry signal generation to instruct changes to the control procedure of state saving processing are performed by hardware according to the stack pointer contents update, thereby improving stack area management and instruction branch processing. This reduces the burden on the software and eliminates the need for specific software processing steps, thereby reducing the time spent managing the stack area and further reducing the time required to save the state. be.

〔Example〕

FIG. 4 shows a block diagram of a coprocessor that is an embodiment of the present invention. This coprocessor 1 is positioned as one peripheral circuit to supplement the arithmetic processing capacity of the main processor (not shown), although it is not particularly limited. ) and execute it. In this coprocessor 1, an internal bus 3 having a bus interface 2 is coupled with an instruction control section 4 that generates various control signals according to a microprogram, and an execution section 5, although this is not particularly limited. It is formed by combining two register files 6.7 with large storage capacity. Although not particularly limited, such coprocessor 1 is a RISC (Reduced Instruction Set Computer) machine, has simplified instructions, has a small instruction set, and uses the built-in register file mentioned above for arithmetic processing. 6.7 is used to speed up processing.

FIG. 1 shows the main parts of the coprocessor 1 in detail in a block diagram.

Although not particularly limited, the data processed inside this coprocessor 1 consists of 40 bits, and the lower 32
The bits are an information field containing data or an address, and the upper eight bits are a tag field indicating the attributes of the information field.

Although not particularly limited, the internal bus 3 has a 40-bit bus so that one instruction can be executed in one machine cycle by exchanging source operands and the operation results of the previous instruction in parallel or continuously. It is mainly composed of a first bus 3A, a second bus 3B, and a third bus 3C. The interface of each of the internal buses 3A to 3C with the outside is a data input register 11 coupled to an external data bus 10.
and a data output register 12 and a logical address register 14 coupled to an external address bus 13.

The register file 6 is a 256-word register RFo-R with 40 bits per word, although it is not particularly limited.
The first bus 3A, the second bus 3B, and the third bus are configured by F2S5 and are individually coupled through three ports.
Data is exchanged with bus 3C. 256 registers RFD-RF2. included in register file 6.
．． is the 8 output from the register file selector 20.
One of them is selected by a selection signal output by the address decoder 21 decoding bit address information. This register file 6 is used as a temporary storage area for source operands and operation results, and is also used as a stack area 5TACK for saving the state when branching the internal operation control procedure.

Stack area 5TAC set in register file 6
Stack pointer 2 indicating the location of the latest information written to the stack top of KH, that is, stack area 5TACKE
3 is included in a pointer register group 25 that includes pointer registers of multiple words. Furthermore, this pointer register group 25 includes a limit pointer 26 that points to the limit address of the stack area 5TACKE set in the register file 6. Other pointer registers included in the pointer register group 25 are used when accessing registers other than the stack area 5TACKE in the register file 6.

A predetermined one of the pointer registers included in the pointer register group 25 is selected according to the microprogram of the instruction control unit 4, and input/output of address information between the internal buses 3A, 3B, and 3G, and from the local address bus 26 is performed. Address information is input to the adder 27, or address information is output to the adder 27.

The adder 27 is a dedicated adder for accessing the register file 6, and is a parameter PR generated according to the microprogram of the instruction control unit 4 based on the value of the pointer register selected from the pointer register group 25.
The address information obtained by adding MT can be supplied to the register file selector 20, the pointer register group 25, and even the logical address register 14. Here, 8-bit address information for selecting one of the 256 registers RF and -RF2.5 of 40 bits per word, that is, the 8-bit address selected and output by the register file selector 20. Although the information is not particularly limited, it is assumed to be 8 bits from the least significant bit of the 40 bits of information provided from the adder 27. In this case, the parameter PRMT given to the adder 27 is "±1" taking into account both increment and decrement.

The value of the stack pointer 23 above and the limit pointer 24
The comparator 30 determines whether or not the values match, and the comparison result COMP is constantly provided to the instruction control unit 4, although this is not particularly limited. For example, as conceptually shown in FIG. 2, when the upper register RFi of the register file 6 is set as the stack limit register, the address of the register RFi is set in the limit pointer 24. Stack area 5T included in register file 6
ACKE inputs and outputs information to be saved in a first-in, last-out format using a push or pop operation. When saving the state necessary for a subroutine call instruction or branching of a microprogram, the adder 27 adds the parameter PRMT (+1) to the value of the stack pointer 23, and according to the address information incremented by the addition, a predetermined register in the stack area 5TACK is stored. data is written to. By repeating this push operation according to the amount of information to be saved, the necessary state preservation is completed. At this time, the address information incremented by the adder 27 is sequentially returned to the stack pointer 23. When the value of the stack pointer 23 matches the value of the limit pointer 24 during a push operation on the stack area 5TACKE, the stack area 5TACKE enters an overflow state in which it is impossible to save a new state, and this state is changed to an instruction by the comparison result COMP of the comparator 30. Notify the control unit 4. When returning to the state, data is read from a predetermined register in the stack area 5TACK according to the address pointed to by the stack pointer 23, and the parameter PRMT is set to the value pointed to by the stack pointer 23 at that time.
The value of the stack pointer 23 is decremented by adding (-1).

The internal buses 3A, 3B, and 3C are connected to an arithmetic and logic unit 31 for data calculations and logical address calculations and a barrel shifter (not shown), and the results of the arithmetic and logic unit 31 are transferred to the internal bus via an accumulator 32. 3A,
It is possible to output to 3B and 3C. Although not shown in FIG. 1, the register file 7 side is also provided with a pointer register group, an adder, a register aisle selector, and an address decoder.

The instruction control unit 4 includes, although not particularly limited to, a micro ROM (read memory) as a micro control memory for controlling the internal parts according to commands output by a main processor (not shown).
only memory) has 40.

The micro ROM 40 contains a micro program consisting of a series of various micro instructions necessary for controlling the operation of the coprocessor 1, and is accessed by the output of the micro address decoder 41. This micro address decoder 41
receives the address information output by the micro address controller 43 based on a command issued by the main processor (not shown) fetched into the command register 42, and decodes this to create a series of micro controllers for executing the command. The first microinstruction in the instruction sequence is read. Although the second and subsequent microinstructions in a series of microinstructions corresponding to a command are not particularly limited, information in the next address field of the microinstruction read immediately before is supplied to the microaddress controller 43. be instructed.

Further, the address of the first microinstruction of the microprogram to be selected when branching the microflow is inputted to the microaddress controller 43 from a control address register group 44 of multiple words. The address information supplied from the control address register group 44 is selected based on various status flags, the comparison result GOMP of the comparator 30, and the like. Note that this selection timing is after the execution of the currently executing microinstruction sequence is completed.

Microinstructions sequentially read from the microROM 40 in accordance with address information selectively output from the microaddress controller 43 to the microaddress decoder 41 are supplied to the microinstruction decoder 46 via the microinstruction latch 45. By interpreting the microinstruction by the microinstruction decoder 46,
Various control signals for the execution unit 5 are generated.

The micro ROM 40 has a stack area of 5TACK.
When E overflows, a series of exception-handling microinstructions is created to save the information previously saved in the stack area to the outside and create a free area in the stack area 5TACKH on the register file 6. Possess. The start address of the microphone command series is set in a predetermined register included in the control address register group 44.

During the execution stage of a branch instruction such as a subroutine call instruction, when necessary information is saved in the stack area 5TACKE, the values of the stack pointer 23 and limit pointer 24 match and the stack area 5TACKH is saved.
When an overflow is detected by the comparator 30, the microaddress controller 43, which receives the comparison result COMP, determines at a predetermined timing the starting address of a series of microinstructions for saving the information in the stack area 5TACKE to the external memory. It is selected and applied to the microaddress decoder 41.

The branch timing of this microflow is the timing before the start of the next bushing operation following the bushing operation when the stack area 5TACKE overflows. When the microflow is branched in this way, for example, the operation of performing a pop operation on the stack area 5TACKE and writing the read information using a push operation is sequentially repeated, as well as sequentially writing the information that should be saved to the external memory. Only a pop operation is performed on the information frame of
An empty area is created. Once the free area is created, the last microinstruction of the microprogram specifies the return address of the microflow, although this is not particularly limited, and the state continues to be saved in the stack area 5TACKE.

In the above explanation, the overflowed stack area 5TAC
A branch instruction to a series of exception handling microinstructions for creating a free area in the KE is given based on the comparison result GOMP of the comparator 30. For example, as shown in FIG. It can also be instructed by the carry signal CAR of the device 27. In this case, the stack area STA that can be set in the register file 6,
The size of CK is limited by the configuration of adder 27. That is,
The stack area 5TAC is configured to match the address pointed to by the stack pointer 23 with the limit address of the stack area 5TACKE when the carry signal CAR is significant.
It is necessary to set KE.

According to the above embodiment, the following effects can be obtained.

(1) Compare the values of the stack pointer 23 and the limit pointer 24, and detect an overflow of the stack area 5TACKE included in the register file 6 based on the comparison result COMP, which detects a match between the two, and then performs this overflow detection. The control procedure for saving the state is switched based on the stack area 5TACKE.
can be used effectively up to the overflow state.

(2) By being able to effectively use the stack area 5TACKE up to the overflow state, it is possible to minimize the number of times the information previously stacked in the stack area 5TACKE is transferred to external memory to create a free space in the stack area 5TACKE. This can reduce the total operating time for state saving processing over the entire system operation.

(3) Overflow detection of the stack area 5TACK is performed by the comparator 30 hardware-wise or automatically according to the increment/decrement of the stack pointer 23.
In addition to reducing the burden on the software for E management and state saving processing, there is no need for specific software processing steps, thereby reducing the time spent managing the stack area and further reducing the time required for individual state saving processing. be able to.

(4) Since the coprocessor 1 is formed on one semiconductor chip and uses the register file 6 built into this semiconductor chip as the stack area 5TACKE, it is possible to access the stack area 5TACKE at high speed for saving and restoring the state. Yes, but additional stack area 5TAC
The state saving process can be controlled when the stack area 5TACKE overflows by directly giving the micro address controller 43 an instruction to change the control procedure for saving the state due to the overflow of the KE and branching the microflow. It is possible to speed up the process of changing the procedure, and further speed up the state saving process.

(5) By using the limit pointer 24, the limit of the stack area 5TACKE can be freely set on the register file 6 according to the information setting for the limit pointer 24.

(6) Even if the carry signal CAR output from the adder 27 is used and the control procedure for saving the state is changed via the microaddress controller 43 based on the carry signal CAR, the above (1) to (5) ) It is possible to obtain the same effect as described in .

However, in this case, it is necessary to set the stack area so that the address pointed to by the stack pointer 23 when the carry signal CAR is significant matches the limit address of the stack area 5TACKE, and the register file The stack area 5TACKE that can be set to 6 is limited by the hardware of the adder 27.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, a case was explained in which an instruction to change the control procedure of state saving processing is given directly to the microaddress controller, but the present invention is not limited to this, and if an interrupt controller is built in, the register file The overflow detection signal may be given to the controller as an interrupt signal. Further, in the above embodiment, the branch destination address itself is held in the control address register, but it is also possible to generate the branch destination address through arithmetic processing).

Further, the register file can be dedicated as a stack area, and the stack area is not limited to the register file structure, but may be a storage means with a structure accessed by a memory access instruction. Address calculation when accessing a register file may be performed by decrementing in response to a push operation and incrementing in response to a pop operation, contrary to the above embodiment. In this case, the limit address of the stack area is on the lower address side of the register file relative to the value of the stack pointer.

Furthermore, when using the carry signal of an adder to detect an overflow in the stack area, the settable stack area is limited to the hardware of the adder, so when using a part of the register file 6 as the stack area 5TACKE, When the stack limit is not set to the highest register of the register file 6 as in the above embodiment, another adder that increments/decrements the value of the stack pointer in parallel with the adder 27 is used to prevent overflow of the stack area. may be detected.

At this time, the operation result of the dedicated adder does not need to be returned to the stack pointer.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, a case was explained in which an instruction to change the control procedure of state saving processing is given directly to the microaddress controller, but the present invention is not limited to this, and if an interrupt controller is built in, the register file The overflow detection signal may be given to the controller as an interrupt signal. Further, in the above embodiment, the branch destination address itself is held in the control address register, but the branch destination address may be generated through arithmetic processing.

Further, the register file can be dedicated as a stack area, and the stack area is not limited to the register file structure, but may be a storage means with a structure accessed by a memory access instruction. Address calculation when accessing a register file may be performed by decrementing in response to a push operation and incrementing in response to a pop operation, contrary to the above embodiment. In this case, the limit address of the stack area is on the lower address side of the register file relative to the value of the stack pointer.

In addition, when using the carry signal of the adder to detect overflow of the stack area, a part of the register file 6 is used as the stack area 5TACK'E because the stack area that can be set is limited to the hardware of the adder. In this case, when the stack limit is not set to the highest register of the register file 6 as in the above embodiment,
An overflow of the stack area may be detected using another adder that increments/decrements the value of the stack pointer in parallel with the adder 27.

At this time, the operation result of the dedicated adder does not need to be returned to the stack pointer.

Although the invention made by the present inventor is applied to coprocessors, which is the background field of application, the present invention is not limited thereto, and can be applied to other microprocessors, microcomputers, and intelligent Needless to say, the present invention can be widely applied to other standardized peripheral controllers, and is not limited to RISC machines, but can also be applied to Cl5C (complex instruction set computer) machines. The present invention can be applied to at least those that require state preservation during data processing operations.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, it compares the values of the stack pointer and limit pointer, detects an overflow of the stack area based on whether they match based on the comparison result, and switches control procedures for saving the state after detecting this overflow. This has the effect that the stack area can be used effectively up to an overflow state.

In addition, by using the carry signal output from the arithmetic unit that updates the value of the stack pointer and making it possible to change the control procedure for saving the state based on this, the stack area can be used up to the overflow state as described above. The effect is that it can be used for

By being able to effectively utilize the stack area up to an overflow state, the number of times information previously stacked in the stack area is transferred to the outside to create free space in the stack area can be minimized in terms of system operation. This has the effect that the total operating time for state saving processing can be shortened in the entire system operation.

Stack area overflow detection is performed using a comparison method that compares the value of the stack pointer and the value of the limit pointer,
This is done either hardware-wise or automatically using arithmetic means that updates the value of the stack pointer, which reduces the burden on software for stack area management and state saving processing, and eliminates the need for specific software processing steps. This has the effect of reducing the time spent managing the stack area and further reducing the time required for individual state saving processing.

When the data processing device is formed on one semiconductor chip, the storage means used as the stack area is built into the semiconductor chip, so the stack area can be accessed at high speed for saving and restoring the state. Change the control procedure for state saving processing when the stack area overflows by giving processing instructions directly to the microaddress controller and branching the microflow. This has the effect of speeding up the processing.

By detecting overflow of the stack area using the limit pointer, it becomes possible to freely set the limit of the stack area on the storage means according to the information setting for the limit pointer.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the main parts of a coprocessor according to an embodiment of the present invention, and Fig. 2 is a conceptual configuration for detecting stack area overflow by comparing the values of the limit pointer and the stack pointer. 3 is a block diagram conceptually showing a configuration for detecting overflow in the stack area using a carry signal output from the adder value of the stack pointer, and FIG. 4 is a block diagram showing the entire coprocessor. FIG. 2 is a block diagram schematically showing the FIG. 1...Coprocessor, 4...Instruction control unit, 5...
Execution unit, 6.7...Register file, RFo-RF
, 5...Register, 5TACKE...Stack area, 23...Stack pointer, 24...Limit pointer, 25...Pointer register group, 27...Adder, 30...Comparator, GOMP... ·Comparison result,
40... Micro ROM, 43... Micro address controller, 44... Control address register group, CAR... Carry signal.

Claims (1)

[Scope of Claims] 1. A data processing device that uses part or all of a storage means used for executing instructions as a stack area for saving a state, wherein a stackable memory in the stack area of the storage means is provided. A stack pointer for indicating an address, a limit pointer for indicating the limit of the stack area, the value of the stack pointer and the value of the limit pointer are compared, and the stack included in the storage means is stored based on the detection of a match. A data processing device comprising a detection means for detecting an overflow of an area, and a sequence control means capable of changing a control procedure for state preservation based on the overflow detected by the detection means. 2. The sequence control means is formed in one semiconductor chip, and the sequence control means saves the information previously saved in the stack area to the outside based on the overflow detection by the detection means, and stores the information in the stack area on the built-in storage means. 2. The data processing apparatus according to claim 1, wherein the operation control procedure branches into a control procedure for forming a free area in the data processing apparatus. 3. The data according to claim 2, wherein the sequence control means includes a microcontrol memory storing a microprogram, and a microaddress controller that branches the microprogram for state preservation based on overflow detection by the detection means. Processing equipment. 4. A data processing device that uses part or all of the storage means used for executing instructions as a stack area for state storage, and indicates a stackable address in the stack area included in the storage means. A data processing device comprising: a stack pointer for a stack pointer; an arithmetic unit that updates the value of the stack pointer; and a sequence control means that can change a control procedure for state preservation based on a carry signal output from the arithmetic unit.