CA1155231A - Pipelined digital processor arranged for conditional operation - Google Patents

Abstract

BO?DIE-2 PIPELINED DIGITAL PROCESSOR ARRANGED FOR
CONDITIONAL OPERATION

Abstract of the Disclosure A digital processor arranged for pipelined operation includes a common data and control bus and a source of instructions and data words. An arithmetic section processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination receives the resultant data word from the arithmetic section.
Control circuits (IR-C) decode a single conditional instruction for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2). The control circuits further decoding another instruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle (i.e., i+3). A comparison circuit compares conditions existing in the digital processor during the first subsequent processor cycle with the specific condition information included in the conditional instruction and logic circuitry selectively disables control of at least one section of the digital processor during the second subsequent processor cycle.

Description

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5~,3 PIPELINED 3IGITAL PROCESSOR ARRANGED E'0R
COMDITIONAL OPERATION

Background of the Invention The invention relates to a pipelined digital processor which is described more particularly as a processor arranged for conditional operations.
Stored program control digital computers typically include a memory, input-output circuitry, a controller and an arithmetic section. The memory provides a source for a computer program and data to be operated on by the arithmetic section. rhe arithmetic section includes circuits which provide means for manipulating data in a predetermined manner. The controller provides control signals for regulating timing and transfers of data to be operated upon. The input-output circuitry provides means for transferring information between the computer and external devices. Some operations of the computer may be conditioned upon flags, status, or conditions, indicating a result of prior operations or other events.
~o increase computational speed, some digital computers are arranged for pipelined operation. In a pipelined operation the arithmetic unit, or section, includes a collection of specialized circuits capable of working simultaneously but altogether forminy a general purpose organization. These specialized circuits operate independently, each performing a specific task in a general purpose procedure. The pipelined operation divides a process into several subprocesses which are executed by the individual specialized circui~s. Successive ones of the subprocesses are carried out in an overlapped mode analogous to an industrial assembly line. New operands are applied at the input to the arithmetic section during each cycle. Different subsections of the arithmetic section perform their tasks in sequential order during subsequent cycles. A resultant is produced during each cycle. Each 1.~, J

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~ 31 specialized circuit performs its own task at the cyclic rate.
Control of a pipelined computer, or processor, presents particularly perplexing problems when operations are to be executed conditionally because instructions become stacked up in the pipeline during steady-state operation.
Heretofore a pipelined digital processor has been designed to transfer data words and instructions from memory to the arithmetic section and a control section in respective pipelined streams. These streams of data words and instruction words fill pipelines of circuits within the processor. As long as the processor operates normallyr the pipelines of information are processed step by step through sections of the processor in a cyclical operation.
A problem arises, however, when an operation must be executed conditionally. Typically this operation is realized by a conditional transer that causes execu-tion of one of two alternative sequences of one or more instructions. Since one of these sequences of instructions is in the processor pipeline when the condition is tested, it may be necessary to abort execution of that sequence and start to fill the pipellne for execution o~ the alternative se~uence. Processing time is lost whenever this alternate sequence is invoked.
Summary of the Invention This problem is solved in an exemplary pipelined digital processor arranged for conditional operation~ rrhe processor includes a source of instructions and data words.
An arithmetic section processes one data word with another data word through selected processing subsections performing operations according to an expression, thereby producing a resultant data word. A destination receives the resultant data word from the arithmetic section.
Control circuits decode a single conditional instruction word for controlling performance of a specific condition test during a ~irst subsequent processor cycle. The ~5~3 control circuits further decoding another inskruction word during the first subsequent processor cycle for controlling all processing sections operations during a second subsequent processor cycle. The specific condi~ion test is performed by a ci~cuit which compares conditions existing in the digital processor during the first subsequent processor cycle with information included in the conditional instruction for selectively disabling control of at least one section of the processor during the second subsequent processor cycle.
In accordance with one aspect of the invention there is provided a pipelined digital processor having a source providing a stream of instruction words for controlling routine processing operations and providing a stream of data words; an arithmetic section for processing one data word with another data word through selected processing subsections performing operations represented by an expression, thereby producing a resultant data word; a destination section for receiving the resultant data word from the arithmetic section; the pipelined digital processor being characterized by control means (IR-C) for decoding a single conditional instruction word for controlling per-Eormance of a speciic condition test during a first subsequent processor cycle (i.e., i~2?; the control means further oc decoding another instruction word during the eirst subsequent processor cycle Eor controlling some processing section operations during a second subsequent processor cycle (i.e., i~3); and means responsive to a comparison between the conditions existing in the digital processor during the first subsequent processor cycle and the specific condition information included in the conditional instruction for selectively disabling control of at least a part of a section of the digital processor during the second subsequent processor cycle.

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~5~3 - 3a -In accordance with another aspect of the invention there is provided a pipelined digital processor in accordance wi~h claim 1 wherein the pipelined digital processor is further characterized by the single conditional instruction being a conditional arithmetic section execute instruction, and the responsive means enabling control of the arithmetic section during the second subsequent processor cycle if the condition is true and disabling control of the arithmetic section during the second subsequent processor if the condition is false.
Brief Description of the Drawings A better understanding of the invention will be reached by reading the subsequent detaiIed description with reference to the drawing wherein FIGS. 1 and 2 when positioned as shown in FIG. 3 which appears with FIG. 1, form a block diagram of a pipelined digital sign~al processor;
FIG. 4 is a timing diagram;
FIGS. 5 and~6, when positioned as shown in FIG.
7, which appears with FIG. 5, form a processor function chart; and FIG. 8 is a processor function chart for a condi~ional opera~ion.
Detailed Description Referring now to FIGS. 1 and 2, there is shown the overall architecture of a pipelined digital signal processor.
A read only memory 100 stores instructions and , ~ fixed data words. Instructions are transferred from the read only memory by way of~a common data and control bus L01 to instruction registers IR-C, IR-L,M,N; and IR-S,T,131, 133 and 134 respectively. Parts of instructions are dis-tributed to the instruction registers. Fixed data words, or coefficient ~words, are transferred from the read only memory by way of the common data and control bus 101 to a coefficient register 102. The register 102 is labelled REG
X because the coefficients are identified .
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hereinafter by the symbol x.
A random access memory 105 stores variable data words which may be stored therein either from an external source or from the output of the arithmetic section of this processor. The variable data words are transferred from the random access memory by way of the common data and control bus 101 to a variable data register 106. The register 106 is labelled ~EG Y because variable data words are identified hereinafter by the symbol _. By choice of the user, the random access memory may store coefficients used in place of fixed data words as well as the variable data words.
Registers 102 and 106, respectively, store a sequential stream of coefficient words and variable data words which are operands applied as inputs to an arithmetic section 110. These sequences of operands are processed in a pipeline fashion through a multiplier subsection 112, an accumulator subsection 115 and a rounding and overflow circuit subsection 116. A rounded output word is produced in a register 118 that is labelled REG W because rounded output words are identified by the symbol w hereinafter.
A select output circuit 120 is included within the arithmetic section for choosing as an output word from the arithmetic section to the data bus 101 either the ~5 variable data word y stored in register 106 or the rounded output word w stored in register 11~. The rounded output word w is a resultant of some process performed by the arithmetic section. The chosen output word can be trans-ferred from either the register 106 or the register 118 by way o~ the common data and control bus 101 to a writeable destination, such as in the random access memory 105.
As previously mentioned, instructions for the digital signal processor are stored in read only memory 1~0. During each processor cycle, shown in FIG~ 4, a single instruction automatically is read out o~ read only memory from a location having an address produced by an ~ ~,, ., , . ~ ~

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address arithmetic unit, or section, 124. 1'he address from a program counter register PC in the address arithmetic section is applied by way of an address bus 128 to the address circuitry of the read only memory. Read only memory responds during each processor cycle by sending the single instruction thus fetched by way of the common data and control bus to the various control field, or instruction, registers IR-C, IR-L,M,N, and IR-S,~
associated with different sections of the processor.
Each instruction, or opcode, used in the digital signal processor includes a plurality of control fields, or control messages, each of which is given a designation such as 1, m, n, s and t to be used hereinafter. The control field register IR-L,M,N associated with ari~hmetic section 110 receives some of the fields, such as instruction fields 1, m and n, respectively associated with control of multiplying, accumulating and rounding operations. The control field register IR-S,T, associated with the address arithmetic section 124, receives instruction fields s and t which relate to control of address register modification for controlling the fetching of operands x and y and the storing of the output word chosen by the selector circuit 120.
The address arithmetic section 124 incllldes two sets of registers 141 and 142, an address bus latch 145, an adder 147 and an adder latch 150 interconnected by some busses.
One set of registers 141, including registers RX, RY, RD, and PC, i5 arranged to store memory addressesO An address stored in register RX can be used for accessing a coefficient word stored in a location in either random access memory or read only memory. An address stored in register RY can be used only for accessing a variable data word stored in a location in random access memory. An address stored in the register RD can be used for writing a resultant data word into a destination, such as a location in random access memory. An address stored in the program `:
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counter register PC is used for accessing the next instruction or ~ixed data word from the read only memory.
The second set of registers 1~2 is arranged to store variable increment values to be used for incrementing automatically addresses stGred in registers RX, RY and RD.
Alternatively, the stored addresses ~ay be incremented by one of a set of fixed value increments.
Operations of the digital signal processor are controlled by t~o types of instructions. Normal instructions are used most of the time. They control the performance of arithmetic operations during signal processing. Another type of instruction, used occasionally, is called an auxiliary instruction. One specific auxiliary instruction controls the loading of an address register or an address increment register in the address arithmetic section.
It is assumed that a start up sequence of instructions is stored in the read only memory starting at an initial address and that a reset circuit sets the program counter register PC to the initial address.
Following the reset operation, typically there is a sequence of instructions for storing additional addresses in the address registers RX, RY and RD and increment values in increment registers ~ J and RK. These registers are set by auxiliary instructions. Ordinarily the values stored in the reyisters RI, RJ and RK are retained therein throughout a program while the values in the registers RX, RY and RD are modified from time to time during the execution of a sequence of normal instructions.
After the processor is reset and the address and increment values stored, the processor can run a valid program for processing digital signals. Most of the instructions used for processing signals are normal arithmetic instructions.
Information in each of the registers RX, RY, RD, PCr RI, RJ and RK can be set to any specific value by an auxiliary lnstruction. For example, a ~irst instruction to :

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load address register RY specifies that some processor register is to be loaded or set.
In this first instruction, a control field c contains the required information. This control field c is stored in an instruction register IR-C during the instruction fetch cycle.
A fixed data word, associated with the first instruction and loaded into the address arithmetic section 124 during the processor cycle in which that instruction is decoded, provides information identifying which address register is to be loaded and fixing the increment value to be loaded~ The control field and value field are transferred from memory by way of the common data and control bus 101 to the control field register XSR 185 and the value field register XSL 1~6.
While the first instruction is being executed, the control field in the register XSR is decoded in a decoder 157 to select the proper address re~ister. From register ~SL the value to be loaded into the address register RY is applied to the registers 141 and 142 through a selector circuit 158 and a bus 160 in the execution cycle of the first instruction.
A second instruction to load increment register RI specifies that a processor register is to be loaded or set. As in the just described example of setting the address register RY, a fixed data word similarly associated with the second instruction provides a control field to identify the register to be set and a value field to establish the value to be loaded. The fields of the fixed data word are applied from the register XSR through the decoder 157 and the bus 137 to determine the increment register selected in the set of registers 142 and from the register XSL through selector 15~ and bus 160 to establish the value to be loaded in the selected increment register during the execution cycle of the second instruction.
During the processing of both normal and auxiliary instructions, control fields s and t from the .. ,.,~ .

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instruction are stored in the instruction register ~R-S,T
when that instruction is fetched. These fields are decoded in a decoder 152 during the next processor cycle with the decoded information being latched in an AAU control circuit 154. This decoded information is applied over a bus 135 to the sets of registers 141 and 142 during the instruction execute cycle, or second processor cycle, after the fetch. Both an address register and an increment register or a fixed increment are selected by the in~ormation on bus 135. The address is applied to ~he address bus latch 145 and to the input of an adder 147.
l'he increment value simultaneously is applied to the other input of the adder 1~7, which increments the address and stores it for one machine state in an adder latch 150.
During the following machine state, the incremented address is applied by way of a bus 136 to the set of address registers 141.
Simultaneously during the processing of a normal instruction, part of the information in the fields s and t is applied through a single machine state delay in a delay circuit 155. This delayed information provides selection information for determining which of the address registers 141 is to be written after the just described addressing operation. In the following machine state, the delayed information is decoded in a decoder 157 and applied over a bus 137 to the add~ess registers 141. ~t this time, the incremented address stored in the adder latch 150 is written into the selected address register thus modifying the address after the addressing operation.
During the processing of an auxiliary register set instruction, the above described operation for writing a post modified address back into an address register may be preempted by the register set operation~ Preempting is accomplished by the decoder 157 in response to information applied thereto from logic circuit 122 by ~ay of a path 138, AAU control circuit 154 and delay circuit 155.

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When the register set instruction preempts the writing of an address register, the information for selecting the address register is applied from register XSR
through the decoder 157 and bus 137 to the address register set 141. Simultaneously from the register XSR, information is applied through decoder 157 and bus 137 for selecting in~ormation on bus 160 in lieu of information on bus 137.
The address arithmetic section 124 transmits addresses by way oE the address bus latch 145 for accessing locations in memories 100 and 105, generates new addresses in the adder 147 and sets the address registers RX, RY, RD
and PC.
Referring now to FIG. 4, the diagram shows that addresses are transmitted to memory as a series of four addresses being transmitted during each processor cycle.
One of the addresses is transmitted during each of four machine states during each processor cycle. The first address transmitted during the first machine state is the address stored in the program counter register PC~ As indicated in FIG. 4, this address is transmitted automatically during the ~irst machine state of each processor cycle. The second address transmitted during the second machine state is the address stored in register RD
or in register RX. The third address transmitted during the third machine state is the address stored in register RX or in the program counter register PC. The fourth address transmitted during the fourth machine state is the address stored in register RY.
Each address transmitted by the address arithmetic section is latched in the address bus latch 145 during the mentioned machine states of the processor cycle.
Also during those machine states, the addresses are incremented in the address arithmetic unit adder 147 by an increment value that is read out of one of the increment registers RI, RJ and RK or in the case of the address from register PC, the address is incremented hy +1. These incrementing operations are accomplished during the same . .

machine state that the address is latched.
Identification of the selected address and increment registers is accomplished by appl~ing the appropriate control fields to the instruction register IR-~,1' prior -to the addressing operation so that the appropriate coding is applied to access circuitry for both the address and the increment registers during the machine state that the address is to be transmitted. soth the address and the value of the increment are read out and are summed by the adder 147. The resulting incremented address is stored in the adder latch 150 while the address is being transmitted from the address bus latch 1~5.
Coding for identifying whichever address register was selected is transferred through the delay circuit 155 to the decode register circuit 157. Delay and decoding are designed so that the incremented address stored in the adder latch 150 can be written into the address re~ister from which the transmitted address was fetched. Thus the transmitted address is post-modified or post--incremented during the processor cycle when it is transmitted to the memories 101 and 105.
Turniny now to FIG. 2, the arithmetic section 110 is organized for pipelined operations. Coefficients words x and variable data words ~ are operands received from the memories by way of the common data and control bus 101 into coefficient word register 102 and the variable data word register 106. The rounded output words w also are operands for some operations and are stored in the regis-ter 11~
new operand is received into each of those registers during every processor cycle of a normal instruction.
The arithmetic section 110 includes three subsections which are independently controllable in response to different control fields 1, m and n. During the fetch cycle of an instruction, the fields 1, m and n are stored in an instruction register IR-L,~,N. In the next processor cycle, those fields are decoded in a decoder circuit 113 and the result stored in register REG F 1~8.
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~55~:Z3:1 During the ~ollowing processor cycle, this information is transferred to an AU control circuit 11~ for supplying control signals to various subsections o~ the arithmetic section. This latter processor cycle is the execution cycle of the instruction. The control signals provide information relating to which choices are to be made from processing options available in each of the suhsections.
The multiplier subsection 112 typically generates a product of two operands during each processor cycle. In a typical multiplication, one operand is the coefficient word x and the second operand is either the variable data word _ or the rounded output word _.
Coefficient word x is a 16-bit word. These sixteen bits are taken into the register 102 from the most significant bit lines of the common data and control bus.
A selection circuit 162 scans the sixteen bits of the coefficient wordj from the least significant bit to the most significant bit, four bits at a time during each of the four machine states in every processor cycle. Another selection circuit 163 concurrently selects either a 20-bit variabIe data word y or a 20-bit rounded output word _~
Multiplication based on Booth's algorithm well known in the art is performed. I'hus a Booth loyic circuit 165 responds to the successive ~-bit nibbles to produce control signals for the generation of partial products.
The output from the Booth logic circuit 165 during every machine state is latched into a register 166.
This output is applied to a circuit 168 which produces the partial products by data selection.
These partial products are accumulated by adding ~o prior sums and carries. An adder 170 sums the partial products with the prior sum and carry information storing a resulting 36-bit intermediate operand, or product word p, in a product register P 191. Associated registers S 190 and C 189 respectively store the surn and carry information produced during each processor cycle~
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,. , Because the arithmetic section is arranged for pipelined operation, the product register P 191 receives a new intermediate operand, or product word, p during every processor cycle of normal instructions. This product word p is applied by way of a bus 172 as an intermediate operand to the input of the accumulatox subsection 115.
In the accurnulator subsection r the product word p is added with a 40-bit resultant output word a t~at may be shifted by a circuit 174 prior to application as an input to an adder circuit 17~. 'l'he adder circuit 175 produces sum and carry information which is stored in register 177.
The sum and carry information is stored in register 177 during every processor cycle. Carries are resolved by carry-look-ahead logic in adder 178 Output from adder 178 15 is applied to an input of a logic circuit 18~ together with the resultant output word a to generate the next subsequent value of the 4~-bit resuItant output word a to be stored in register A. Such a resultant output word is produced and stored in register A 192 during each processor cycle of a 20 normal instruction.
A portion o~ the resultant output word a is applied as an input to the rounding and overflow circuit subsection 116 in 10-bit slices. ~rhese slices are clocked through a roun~ing circuit 1~ and an overflow logic circuit 184 to the 20-bit rounded output register W in three consecutive machine states of each processor cycle In the fourth machine state~ ~he value in the register W
may be corrected for overflow if the value in the ?
register A is too large to be represented in the 2~-bit 30 register W 118. Then the rounded output word can be transferred through the common data and control bus 101 to a destination, such as a location in the random access memory 105 where it is stored.
l~he three subsections (multiplier~ accumulator 35 and rounding) of the arithmetic section acco~nplish their basic operations in one processor cycle each. Outputs of the subsections are stored in registers every processor ;

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~,3 cycle so that the next subsection in line has a stable input to commence the next subsequent processor cycle.
Control of the arithmetic section 110 and of the address arithmetic section 124 is accomplish~d by a pipelined stream of instructions applied from the memory 100 through the common data and control bus 101. As previously stated with respect to FIG. 4, a single instruction is read out of memory during each processor cycle of operation. Such an instruction includes several instruction fields, or control messages, 1, m, n, s and t.
Fields _, m and n are transferred through the common_ bus ~01 to the register IR-L,M,N for controlling the subsections of the arithmetic section 110. Flelds s and t are transferred through the common bus 101 to the register I~-S,T for controlling selection and incrementation of addresses stored in the registers RX~ RY, RD and PC.
A fuller appreciation of the arrangement for and operation by pipelined control of processing may be achieved by the followiny discussion of a specific example of operation.
Normal Opera-tion A complete normal assembly language instruction includes all o~ the information required to perform a desired arithmetic operation. Assembly language instructions for the digital signal processor are designed to represent the control for access to the memory and the contro- for operation of the arithmetic subsection and of the address arithmetic subsection. The arithmetic subsection continuously performs multiplication and addition operations. The normal arithmetic section operations are characterized by the following general expressions:
x-f(y) ~ fa(a) --> a{ --> w}
x.f(w) ~ fa(a) --> a{ --> w~, where '' ,. :

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x is a 16-bit wide coefficient word usually fetched from read only memory. The coefficient word x also could be fetched from random access memory or from an input/output circuit 200 and ordinarily has a value for all arithmetic operations.
y is a 20-bit wide data word normally fetched from random access memory~ Such a data word also could be fetched from the input/output circuit 200.
a represents the 40-bit wide contents of an accumulator register A 192. In the accumulator register A 192, the least significant thirty-six bits are used to accumulate the product of a 16-bit by 20-bit multiplication. The four most significant bits provide overflow protection for the accumulation operation.
w is a 20-bit wide rounded or truncated output of the accumulator. The least significant bit of the rounded output w corresponds with the bit that is fourteenth from the least significant bit of the contents a of the accumulator. This correspondence of bits is consistent with an assumption that the data word _ and the rouncled output w are integers and that the coefficient word x usually is restricted within the bounds -2 < x < 2.
f describes a function of either -the data word ~ or the rounded output w. Such function can be the actual value, the sign, or the absolute value of either one of the variables y or w.
fa generally describes a function of the contents a of the accumulator, such as a/ -a, 0, 2a, etc.
The variables x, y, w and p are contained in arithmetic section registers X 102, Y 106, W 118 and P 191, respectively.
The aforementioned general expressions imply that three operations are to be performed by the processor.

(1) One of the products p = x~f(y) or p = x~f(w) is formec3 and is stored in the product register P located ,:

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at the output of a multiplier.

(2) An accumulation o~ a resultant word a = p ~ fa(a) is accomplished in the accumulator.

(3) Then if required the result~nt word a of the S accumulator is rounded and the rounded output word w is written into the rounded output register W.

Each of these three operations is completed during one processor cycle of the digital signal processor. Typically during the operations, the coefficient word x has a value and a multiplication forms the product p. Also typically during each cycle~ all three types of operations are performed concurrently by different subsections of the arithmetic section. ~`or some instructions one or more of the three operations may not occur. 'l'he operation performed by one subsection during one processor cycle is a partial evaluation of a different general expression than the expressions concurrently being evaluated in the other subsections~
~ssembly language instructions are converted to machine language instructions which are stored in the memory for actually controlling the digital signal ~rocessor. Because the operations are dependent upon one another and because all of the operations occur concurrently within the processor, it is important to know at all times what is stored in various reyisters and what operation is to be performed thereupon.
To avoid confusion regarding which values of the product word p and which values of the contents a of the accumulator are involved in any processor operation the following order of operations is recolnrnended when writing assembly language expressions representing ~hem.
p <-- x-f(y) {w <-- a} a <~~ P ~~ fa(a) or ~ <-- x-f~w) ... .

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~ 16 --hen as the reader proceeds froi,l left to right, the proper values o~ the product word p and of t~e contents a of the accumulator are more apparent. The proper values are the results of the last preceding oyeration which determined those values. Thus the value of the contents a of the accumulator to be rounded into the rounded output w or to be used in any function fa(a), is the contel-ts a of the accumulator at the end of the last previous accumulation~
Similarly the value of a product word _ to be used in a l~ current accumulation has a value determined in the last previous multiplication operation.
Because of the reasons given in the foregoing discussion of the order of processor operations it is important that the information contained in the assembly language instruction be presented to the processor in proper order. Information presented in the following order is acceptable to the processor.
(1) A choice of destination is made. The word to be written to the destination is chosen from either the rounded output word w or khe data word ~. The chosen word can be written into the random access memory or into the input/out~ut circuit. The speciEic de~tination of the selected word is given~
(2) As required by the instruction there is a choice o~ whether or not to move the resultant word a into the rounded output w.
(3) One accumulation operation is selected from a group of operations having a general expression a = P + fa(a)-

(4) Specify a multiplication operation producing the product p = x-E(y) by indicatiny the source XSRC of the coefficient word x the nature of the function f, and the selection of the data word ~r together with the source YSRC of the data word y. Alternatively specify a multiplication operation producing the ~ .

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, ' ' " . . - ' ' ~ ' 1 3 ~, product p = x f(w) by indicatin~ the source XSRC of the coefficient word x, the nature of the function f, and the selection of the rounded output w rather than the data word y.
The following exceptions apply to the above-mentioned left-to-right rule~ When the rounded output w is selected for the multiplication, the value of the rounded output is the value determined by the last rounding of the resultant word a as performed in a preceding instructiont If data word _ is to be written and a source for data word ~ specified, the first step in execution of the instruction moves the data from the specified source into the data register Y. Thereafter any writing of this new value for data word y can occur.
The following Table I summarizes the normal assembly language instructions that a programmer would use for preparing an assembly language program. The syntax of a language called C is used as the assembly language which is described in a text entitled, The C ~ Language by B. W. Kernighan et al, Prentice-Hall, Inc., 1978. Each complete instruction is formed by choosing four statements, one statement Prom each column oP Table I starting with the lefthand column and working toward the right. In the two leftmost columns, the word NOTHING is listed as a valid choice. When the word NOTHING is selected as a part of a complete instruction, the corresponding space in the instruction is left blank. Every complete assembly lanugage instruction is terminated by a semicolon.

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TABLE I ~ NORMAL ASSEMBLY LANGUAGE INSTRUCTIONS

NOTHING NOTHING a=p p=XS~C*YSRC
DEST=y w=a a-p~a p=XSRC*w DEST=YSRC a=p-a p=XSRC~c DEST=w a=p~2*a p=XSRC*abs(YSRC) a=p+8*a p=XSRC*abs(w) a=p*a/2 p=XSRC~c*sgn(YSRC) a=p~a/8 p=XSRC*c*sgn(w) a=p&a In Table I the symbol DEST means a destination statement and is to be replaced in the assembly language instruction by one of the following statements.

DEST

*rd+~i *rd~j *rd+~k obuf where e.g., *rd+~i means that rd, which is the address of khe location in random access memory pointed to by the contents o~ register RD, is post incremented by the contents i of register RI. Interpretations of different ones of the foregoing destination statements are explained in more detail subsequently.
Also in Table I 7 the symbol XSRC means a statement for the source of data word x, and the symbol YS~C means a statement for the source of the data word y. Each of those two symbols in Table I is to be replaced, in any assembly language instruction, by one of the sta~ements in the following two columns:
XSRC YSRC
x(old x) *ry~i ., .~., :: ~ : ,- , ~ . , -VALUE (immediate x) *ry~+j *rx++i *ry++k *rx~+j ibufy *rx++k *rx *rx--ibufx ~(rom+rx~+i) *(rom+rx++j) ~(rom+rx~+k) &LABEL

In the foregoing columns headed XSRC, the symbol VALUE represents a number that appears as an argument (mathematical) of an instruction, i.e., the 16-bit word immediately following the opcode in the read only memory.
Such argument is addressed by the address stored in the program counter register PC. In other fetches from memory, the coefficient word x is addressed by the contents rx of the re~ister RX. The notation ~(rom~rx...) is used to indicate that the contents rx of the register RX poiot to read only memory rather than the random access memory. The symbol &LABEL represents that the value read from memory source x is an address associated with a label in the program. Other expressions presented in the foregoing two columns for the sources of the coefficient word x and the data word y are presented in more detail subsequently.
~ ith respect to forming complete assembly language instructions from the information presented in Table I, some caution is suggested. If the expression 30 DEST = YSRC is desired in an instruction including the expression YSRC from the rightmost column, then the expression DEST = y must be used in place of the expression DESI = YSRC. If the rounded ou~put w is to be used in the rightmost column, the expression D~5T = YSRC cannot be 35 selected from the leftmost column. Additionally, NOTHING
should be selected from the leftmost column when the ' assembly language instruction is a normal instruction in which the source of the coefficient word x is located in random access memory.
In the preparation of a program, a programmer will first write out a series of general mathematical expressions or operations desired to be performed. q~hese may take, for éxample, the form x-f(w) + fa(a) --> a{ --> w}
Such a general mathematical expression is translated by the programmer into an assembly language statement which takes the following form: `

s n m l,t *rd++~=w w=a a=p+a p=~rx~+i**ry~+k;
where 1 means an instruction field for controlling the formation of a product~

~. .. ..

m means the instruction field for performing an accumulation.
_ means an instruction field for controlling a transfer operation from register A to register W with the required rounding.
s represents an instruction field identifying a write destination. In this example the destination is a memory location specified by the address stored in register RD. That address is post-incremented and the result stored in the register RD.
t means an instruction field to fetch information from an address stored in an address arithmetic unit register, post-increment that address and store it back into that same register.
The next step performed by the programmer is to skew (spread or distribute) in time the assembly language statement as follows:
Time s n _ l~t i ~ _ p-*rx-~i*~ry~k.
20 i~2 ~ w-a a=p~a . _ ____ __ _ .__ _ __ _____ i1-3 ~
_ . . . .. ~_ The resulting skewed assembly languaye statement, which appears diagonally on the time line of the leftmost ~;
column, is stated together with skewed assembly language statements representing other general mathematical operations. When these skewed assembly language statements are stated together, the resulting pieces of different statements which appear in the same row, or during the same interval such as interval i, form an assembly language instruction. In the assembly language instruction, the different pieces of information in the same interval are separate fields of that assembly language instruction.

, Each of these fields controls a separate subsection of the processor for performing a step in the process of evaluation, as described by a portion of one of the general mathematical expressions.
An assembler program, which runs on a general purpose computer, operates on each assembly language instruction by moving the source fields two processor cycles earlier in the program than the rest of the fields in that same assembly language instruction. This moving o~
the source fields is done to every assembly language instruction in the program. The resulting time line for the foregoing assembler statement, as skewed by the programmer and the assembler will appear as follows:

Tlme s t n m I

15 i-2 x=*rx++i Y=*rY~k i-l - == =xl~
_ P Yl , i~l _ _ _ _ a=~+a i+2 _ _ _ w=a _ _ 20 i-~3 *rd~j~w _ _ _ _ __ .

Referrinq now to FIGS~ 5 and 6, there is shown a time line diagram indicating how data is processed in the digital signal processor. In general, the diagram presents the flow of data through various subsections o~ the processor during the evaluation of one general mathematical expression together with parts of other mathematical expressions.
Before attempting to describe the operations represented we will first define symbols used throughout the time line diagram of FIGS. 5 and 6.

Ii is a machine language instruction fetched from read only memory during a processor cycle~ or interval, i and decoded within the processor durinq a ... . . .

processor cycle, or interval, i+l. In general the instruction Ii a~fects operation of sections of the processor during a processor cycle~ or interval, i~2. As previously mentioned each instruction contains the fields, or con~rol messages, 1, m, n, ..
s and t.
(t) represents the field t in the machine language instruction Ii for co~trolling the fetching of operands xi+3 and Yi+3- These fetches take place during the interval i~3.
Ii(l) represents the field 1 in the machine language instruction Ii for controlling the computation of a product, or intermediate operand, Pi~2 during the interval i+2. The product Pi+2 is a function of the operands xi~l and Yi~l-(m) represents the field m in the machine language instruction Ii for controlling the accumulation of output from, or desired resultant word, ai~2 during the interval i+2. The resultant word ai+2 is a function of the last prior resultant word ai~l and a product Pi+l previously computed.
(n) is a field n ln the machine language instruct.ion for controlling the transfer of a roundecl OlltpUt word wi~2 during interval i-~2~ Rounded output wi~2 is a function of the last prior rounded output wi+
and the resultant word ai~1 of the accumulator.
(s) is a field in the machine language instruction for controlling the storing of the rounded output word wi+l and the modification of register s-tored : 30 addresses ui+2 during the interval i+2. The modified addresses are a function of the prior address ui+l and field Ii(s). The updated memory state Mi+2 is a function of the field Ii(s), the : prior memory state Mi+l, register stored addresses ui~l and the rounded output word wi+l.
Ii(s,t) is a combination of fields s and t within the machine language instruction. The Eields control , . , .
. : , - ~ , .

the ~odification of register stored ad~resses ui+2 during the interval i+2. The modified addresses ui+2 are also a function of the address u Xi and

5 Yi are operands fetched from memory during the interval i, under control of the field t of the instruction Ii 3 fetched from memory during the interval i-3. Instruction Ii 3 is decocled during interval i-2 and controls processing during interval i-l wherein the addresses for operands xi and Yi are produced. As previously mentioned these operands are accessed from memory during interval i. They are processed through the multiplier during the interval i-~l under control of the field 1 of the instruction Ii 1~ which is fetched during the interval ii_l. This produces the intermediate operand or product Pi+l-Pi+l represents the product formed by the multiplier during the interval i~l. This product is an intermediate operand which is used as an input to the accumulator for its operation occurrin~ during the interval i+2. Product Pi~l is formed in re~ister P under control of the field Ii_l(l). I'he rnultiplier and multiplicand are the operands xi and Yi-ai~2 represents the contents of the accumulator during the interval i+2. This is the desired resultant word ai+2 for the expression being evaluated. The word ai+2 is an input for the rounding and output !.
circuit subsection for the interval i~3. The rounding operation occurs under the control of the field Ii+l(n).
Wi~3 represents rounded output word w which is available in the register W and which can be stored into writeable memory during the interval i~4 under the control of the field Ii+2(s).

,.

.. . . . .
- , . ' :. ' ~

. . .

In the diagram of EIGS. 5 and 6, there is shown all of the processing activities of various processor subsections of the digital signal processor together with time in processor cycle~s. Each column in the chart represents a different processor cycle, or time interval, of the processor. Information in each column is closely related to some machine language instruction~ Each row represents activities of a different processor subsection performing its assigned functions during operation of the digital signal processor.
Since each row of the chart represents a different activity, we shall define those activities. The first row below the processor cycle headings indicates storage activities, i.e., memory fetches and stores. The second row presents the times at which instructions are decoded within the digital signal processor. The third row shows the computing of the product p by the multiplier subsection of the processor. The fourth row presents the accumulating of the resultant word a by the accumulator subsection of the processor. Row five presents ac-~ivities of the roundiny and overflow subsection of the processor, which produces the rounded output word w. The sixth row discloses activities associated with modifying addresses used for fetching data for the arithmetic processes.
The processing of the a~orementioned general arithmetic expression can be traced through -the various sections and subsections of the digital signal processor by re~erence to FIGS. 5 and 6.
A first step in the processing of a general arithmetic expression is the fetching of operands for a multiplication. As previously mentioned, information relating to this fetch operation is placed by the assembler program into an interval earlier than the information associated with control o~ the multiplication operation. -As a result of this assembler program function~ every machine languaye instruction includes a control field for a fetch operation that fetches information from memory for , .
: ,. :~ - .

processing to be controlled by a subsequent machine langua~e instruction.
As an example of processing an instruction~
consider processing a general expression having information relating to fetch operations for its operands included within an instruction fetched during the interval i-3 oE
FIG. 5. This instruction Ii 3 is shown in an emphasized box and is labelled with a subscript identifying the instruction as the instruction fetched during interval i-3.
Each instruction shown in the processor function chart is similarly designated in accordance with the interval during which the instruc~ion is fetched from memory. Also each instruction, shown in FIGS. 5 and 6 includes several fields of control information. Each of those fields 1, m, n, s and t are shown in parentheses associated with the instructions in the first row representing the fetching and storing operations. A separate field or separate fields of an instruction are shown in other rows of the chartr e.g., Ii~l) in the row for computing products and Ii(s,t) in the row for modifying addresses.
- During the interval i-2, the just fetched instruction Ii_3 is decoded by the processor, ~s shown in the emphasiæed box in the second row representing the decoding oE instructions.
A fetch operation for the operands x and y, identified by the instruction Ii_3, begins during the interval i-l. The fetch operation begins using an address specified in the instruction field Ii 3(t). When that address is used, it is modified and stored back in the address arithmetic section as a function of the instruction field Ii_3(s,t) and the prior state ui_2 of the registers in the address arithmetic section. This modification of addresses is shown in the emphasized box under the interval i-l. Fetch of those operands x and y is concluded during interval i when the specific operands xi and Yi, identified by the instruction Ii_3, are read out of memory and are transferred by way of the common data and control bus .

.

' ., BO~IE-2 respectively to registers REG X 102 and REG ~ 106. These fetch operations are shown in the emphasized box under the lnterval i. The operand xi typically is read out of read only memory, and operand Yi typically is read out of random S access memory.
The address pointers, or the addresses stored in registers RX and RY, which were updated in the prior interval i-1 are used for accessing the operands from memory during the interval i.
~rhe first arithmetic operation to be performed on the operands xi and Yi occurs during interval i+l. At this time the multiplier subsection responds to the instruction field Ii 1(l) for computing an intermediate operand, or product, Pi+l, as shown in the emphasized box under interval i+1. Such product Pi+l is shown as a function of the operands xi and Yi and of the instruction field _l (1) .
Instruction Ii_l, which includes -the field Ii_l(l), is fetched from memory during the interval i-l, is decoded during interval i and controls sections of the processor during interval i+l.
The next step in evaluating the general expression is processed in the accumulator during interval i+2. This is shown in F~G. 6 in the fourth row 2S representiny the accumulation of the resultant word a in an ernphasized box under the column designated interval i+2. A
resultant word ai+2 is shown to be a function of the prior resultant word ai+l stored in the accumulator, the just described intermediate operand, or product, Pi.~l, and of the instruction field Ii(m).
If specified by the programmer and after the result is accumulated during interval i+2, that result is rounded and is stored in the rounded output register W.
This rounding operation is shown under the interval i~3 in an emphasized hox in the fifth row representing rounding of the output. The specific rounding operation occurs during interval i+3 where the rounded output wi~3 is shown as a ,, , , function of the last prior rounded output wi+2 of -the rounded output register W 118, the just descrihed resultant word ai+2 of the accumulator, and of the instr~c-tion field Ii+l~n).
A final step in processing the general expression is a writing of the rounded output wi~3 into memory during interval i+4. This is shown in the emphasized box in the first row of the chart under the interval i+4. Writing a new memory state Mi+4 is a function of the memory state Mi+3 for interval i+3 of the last prior address register state ui+3, of the last rounded output wi~3 just described, and of the instruction field Ii+2(s) which was fetched during interval i+2 and decoded during interval i+3.
Rounded output wi+3 contained in the rounded output register at the end of interval i+3 is transferred by way of the common data and control bus either to the random access memory or to a buffer in the input/output circuitry during interval i+4.
At the same time that the memory write operation occurs during interval i-~4, the address arithmetic section registers are updated based on informa-tion in the instruction fetched during interval i~2. I'he information used is included in the fields Ii~2(s,t) of the instruction ~i+2 that is fetched during interval i+2 and is decoded during interval 1~3.
During the interval i-~2, it is noted that the instruction Ii which was fetched during interval i controls the multiplier subsection, the accumulator subsection and the rounding and overflow subsection of the arithmetic section. This results from the instruction Ii being fetched in interval i, decoded in interval i-~l and used for control during interval i~2. No parts remain for controlling subsections of the arithmetic section during subse~uent intervals, as in prior pipelined control arrangements. ~ost of the column representing interval i+~
is emphasized with heav~ lines so that the reader readily can find several fields of the instruction Ii for controlling subsections of the arithme-tic section during interval i+2.
Operands for the multiplier operation were fetched during the interval i+l which follows interval i.
The resulting product Pi+2 is formed during the next interval i~2.
A resultant word ai+2 which is formed during that same interval i+2 is a function of an earlier resultant word ai+1 and an earlier product Pi+l. This resultant word ai+2 is a resultant word evaluated for a different general expression than the general expression being evaluated by forming the product Pi+2. This concept can perhaps be better understood by the realization that the emphasized boxes forming a diagonal from the top of the column designated processor cycle i down to the fifth row in the column designated processor cycle i+3 relate to the evaluation of one general expression. ~ similar diagonal, shifted one interval to the right in each column, relates to the evaluation of another different general expression.
Typically in a signal processinq pro~ram, instructions are executed, in sequence, up to a point where the program counter PC, is set to the address value in the program store which is the location of the instruction of the ~eyinning of the sequence. 'rhus the progr~m will operate contlnuously in a loop executin~ the same sequence of instructions repeatedly. Furthermore, fixed data words will be stored at memory locations where addresses are interleaved with location of instructions in the program sequence. In this way, as shown in FIG. 4, the address in the program counter register PC is used to address a fixed data word during state 2 of processor cycle i+l. The program counter then is incremented by the fixed increment +1 or is used to address an instruction, Ii~2, in state O
of processor cycle i+2. ~gain the program counter is incremented ~y the fixed increment, +1, and used to address the next fixed data word in state 2 of processor cycle i+2~
Continuing, the program counter is incremented by -~1 and is , ~, , , . . I

used to address instruction, Ii+3, in state O of the processor cycle i+3 and so on until the end of the instruction sequence. At that time the program counter is set, by an auxiliary register set instruction, to the address of the first instruction in the sequence.
I'o this point in the description, only routine normal operations of the digital signal processor have been mentioned. Other operations, such as conditional operations, can be performed by the pipelined digital signal processor.
Conditional Operation In many cases, the algorithm, realized by the condition test and execution of alternative operations that are dependent upon the outcome of the test may be realized lS as well by a se~uence of one or more instructions that either is executed or is not executed. If this sequence is short, the overall savings in processing time may be large when compared with using the conditional program transfer technique o~ the prior art Eor achieving the same result.
We have discovered that conditional operations occurrin~ ln digital si~nal processin~ frequently can be realized with the use of a ~equence oE one or more instructions that either is executed or not. Therefore the digital signal processor has been designed to process efficiently conditional operations in this manner. The concept used, however, has wider applicability to digital processors yenerally.
For example consider the problem of finding the maximum value of a sequence of samples stored in memory.
The value of each sample in the sequence can be compared with the value of a word in another location by using the conventional conditional transfer approach requiriny alternative sequential processing paths.

...

, : ~

if (x > Xmax) Xmax x;
else /*do nothing*/

such that the statment xmax = x; i5 bypassed or branched around by conditional change of the program counter contents. In our digital signal processor, the instruction xmax = x is processed (i.e., fetched and decoded) in sequence independent of the test with the actual transfer of data to xmax being inhibited if the test fails.
A conditional instruction causes the processor to perform a condition test operation which is a non-arithmetic auxiliary operation. As in normal arithmetic operations described previouslyl there is a proper order for writing an assembly lanyuage instruction for conditional operations. llhe following is presented in the proper order.

(1) A choice of destination is made. The word to be written to the destination is chosen from either the rounded output word w or the data word y. The chosen word can be written into the random access memory or into'the input/output circuit. The specific destination of the selected word is given.

(2) Specify the condition to be ~ested and the processor operation to be performed if the test is successful.

.

The following table summarizes the conditional instructions which are formed by choosing one statement from each of two columns.

TABLE II - CONDITIONAL INSTRUCI'IONS
NOTHING if (COUDITIO~) doset( ) DEST = YSRC if (CONDITION) doau( ) DEST = w if (CONDITION) dowt( ) Meanings for DEST and YSRC are the same as those applicable in TABLE I. The term CONDITION should be replaced by one of the following:

CONDITION Description a==0 Accumulator contents a equals zero.
a > 0 Accumulator contents a is greater than zero.
a < 0 Accumulator contents a is less than zero.

Each conditional instruction is assembled as a 16-bit opcode word followed by a 16-bit argument. 1'he format for a conditional instruction is c I 's _~

~ where c, s and t are control fields, as in the normal _ _ arithmetic instructions. Fields s and t have the same meaning. Control field c provides control information for the conditional opera-tion. That information includes what operation is to be performed to~ether with the condition to be tested.
There are three choices of operations provided.
A processor address or increment register is set if the specified condition is true. The next arithmetic section operation is performed if the condition is true. The next write operation is performed if ~he condition is true. For every conditional instruction, the mentioned operations do . ., B O~D D I E - 2 not occur if the condition is false.
operations which are sub~ec-t to the condition test are the operations specified in the instruction next following the conditional instruction in the pipeline.
Each conditional instruction processed by the digital signal processor is fetched from the read only memory 100 and is transferred over the data bus to the instruction registers. The control fields s and t are stored in the instruction register IR-S,ll as previously described. Control field c is stored in instruction register IR-C.
By reference to FIG. 8, the operation of the arrangement of FIGS. 1 and 2 will be described performing a conditional operation. Most of the conditional operation occurs much like a routine normal operation. ~rherefore emphasis will be placed upon those portions of the operation which differ from a routine normal operation.
The reader is refer~ed back to the preceding descrip-tive material for completeness.
In FIG. 8, there is shown a conditional instruction Ii(c,s,t) that is Eetched during processor cycle i and is decoded in processor cycle i+1. In this ?
exarnple the conditiorlal instruction Ii~c,s,t) ls positioned in the pipeline to affect a normal arithmetic instruction Ii+l~l,m,n,s,t) which is fetched cluring processor cycle i~l, decoded during processor cycle i+2 and is conditionally executed during processor cycle i+3.
Fields s and t of instruction Ii(c,s,t) control i data fetches and a write operation during the interval i+2.
The state ui+2 of the registers in the address arithmetic section is updated during interval i+2 as a function of the control fields Ii(s,t) and of the prior state ui+l of those registers. A write memory operation Mi+2 that occurs during cycle i+2 is similar to the operation previously described with respect to the normal arithmetic instruction. Because the conditional instruction is an auxiliary instruction, the arithmetic section 110 is idled ., ~ :
. ~ ~., , ' :

- 3~ -during interval i+2 which is the usual execution cycle for this instruction. Therefore multiplier register P, accumulator register A and rounded output register ~J`1 retain their respective data from the last prior cycle.
5 Intermediate operand Pi+2 equals Pi+l, resultant ai+2 equals ai+l and the rounded output word wi~2 equals w Control field Ii(c) which is stored in the instruction register IR-C during interval i includes one part identifying what condition is to be tested and a 10 second part identifying what operation is to be controlled in dependence upon the test outcome of the condition.
During interval i+l, the two parts of the control field Ii(c) are decoded in circuits 211 and 212 and are stored in registers 213 and 214.
During interval i~2, the first decoded part of control field Ii(c) that is stored in register 213 is applied to a comparator 215 establishing what condition is being tested. Simultaneously, the status of conditions, or flags,Vi+2 from the arithmetic section control 114 are 20 applied by way of a path 225 to the comparator 215~ Thus the status of the conditions of the arithmetic section are tested. Comparator 215 produces a condition true or a condition false siynal on lead 221 through which the resulting signal is applied as a conditional conkrol on 25 logic circuit 122.
Also during interval i+2, the logic circuit 122 operating under control of the conditional signal on lead 221 produces further control signals ~hat are i dispersed to the circuit DECODE F 113, the address 30 arithmetic section control 154, the random access memory 105 and the input/output circuit 20û. The result of the conditional operation is held at the output oi the logic circuit 122 for controlling the various sections of the processor durîng interval i+3.
Normal arithmetic instruction Ii+l(l,m,n,s,t), which is to be affected by the conditional instruction Ii(crs,t), is fetched during interval i+l and is decoded .

.

during the cycle i+2. Without the preceding conditional instruction this instruction would control the processor during interval i+30 Data fetches for interval i+3 occur as usual.
Thereafter during interval i+3, operations executed depend upon the usual operands together with the state of the control lines from the logic circ~it 122, which are conditioned upon the outcome of the comparison made during interval i+2.
When the conditional instruction Ii(c,s,t) is a conditional arithmetic section execute, only arithmetic unit operations are conditionally executed during the interval i~3. Writing memory is not inhibited at this time. If the condition is true for the conditional arithmetic section execute instruction, a new product pi+3r resultant word ai+3 and rounded output word wi+3 are produced. If the condition is false, control of the arithmetic section is disabled and no new product, resultant word or rounded output word is formed. The registers P, A and W retain values from the last prior interval. All other normal processor operations occur during interval i~3.
If the conditional instruction Ii(c,s,t) is a conditional write instruction, only the memory write and output write operations are affected during interval i+3.
Operations of the arithmetic section are not inhibited. If the condition is true for the conditional write instruction, the me~ory write operation Mi~3 or output write operation occurs. If the condition is false, control o~ the write operation is disabled and the memory retains its state ~i+2 from the prior interval. Writing to memory or output is controlled by control field Ii, as discussed previously for normal instructions. Whether the condition is true or false, all other processor operations occur normally during interval i+3. If the conditional instruction Ii(c,s,t) is a conditiona~ register set instruction, only a register set operation is affected , `` ~ , "

S~

during interval i~3. Note that in this case, since the register set instruction is an auxiliary instruction, there will be no activity in the arithmetic section. Memory or output write may proceed without interference as specified by control field Ii(s). If the condition is true, the register designated by the register select field cf the fixed data word, associated with the register set instruction, is loaded with the value in the value field of that data word, as explained previously. If the condition is false, control of the register set operation is disabled and the register contents are not changed by the register set instruction.
The foregoing is a description of the arrangement and operation of an embodiment of the invention. The scope of the invention is considered to include that embodiment together with others obvious to those skilled in the art.

.
.
: . :

Claims (7)

Claims

1. A pipelined digital processor having a source providing a stream of instruction words for controlling routine processing operations and providing a stream of data words; an arithmetic section for processing one data word with another data word through selected processing subsections performing operations represented by an expression, thereby producing a resultant data word; a destination section for receiving the resultant data word from the arithmetic section; the pipelined digital processor BEING CHARACTERIZED BY
control means (IR-C) for decoding a single conditional instruction word for controlling performance of a specific condition test during a first subsequent processor cycle (i.e., i+2);
the control means further for decoding another instruction word during the first subsequent processor cycle for controlling some processing section operations during a second subsequent processor cycle (i.e., i+3); and means responsive to a comparison between the conditions existing in the digital processor during the first subsequent processor cycle and the specific condition information included in the conditional instruction for selectively disabling control of at least a part of a section of the digital processor during the second subsequent processor cycle.

2. A pipelined digital processor in accordance with claim 1 wherein the pipelined digital processor is FURTHER CHARACTERIZED BY
the single conditional instruction being a conditional arithmetic section execute instruction, and the responsive means enabling control of the arithmetic section during the second subsequent processor cycle if the condition is true and disabling control of the arithmetic section during the second subsequent processor if the condition is false.

3. A pipelined digital processor in accordance with claim 1 wherein the pipelined digital processor is FURTHER CHARACTERIZED BY
the single conditional instruction being a conditional write instruction, and the responsive means enabling control of writing the destination section during the second subsequent processor cycle if the condition is true and disabling control of writing the destination section during the second subsequent processor cycle if the condition is false.

4. A pipelined digital processor in accordance with claim 1, wherein the pipelined digital processor is FURTHER CHARACTERIZED BY
the single conditional instruction being a conditional register set instruction, and the responsive means enabling control of setting a register section during the second subsequent processor cycle if the condition is true and disabling control of setting the register section during the second subsequent processor cycle if the condition is false.

5. A pipelined digital processor operating in response to a plurality of control fields in each opcode word of a sequence of opcode words, each conditional opcode word being designated Ii(c,s,t) and each unconditional opcode word being designated Ii+l(l,m,..s,t) where i = 0,1,2..., Ii(c) is a conditional control field, Ii(s,t) are control fields, Ii+l(l) is a first normal control field and Ii+l(m) is a second normal control field, each normal control field including information for determining a step in processing a selected expression of an operand yi+2;
means for decoding a conditional opcode word Il(c,s,t) during a first interval (i.e., i+l=2) and a normal opcode word I2(l,m,..s, t) during a second interval (i.e., i+2=3);
means for fetching and storing an operand y3 during the second interval, the pipelined digital processor BEING
CHARACTERIZED BY
at least one processor section responsive to some of the decoded fields I2(l,m,..s,t) during a third interval for processing the operand y3 during the third interval if the condition is met and for omitting processing the operand y3 during the third interval if the condition is not met.

6. A pipelined digital processor operating in response to a plurality of control fields in each opcode word of a sequence of opcode words, each conditional opcode word being designated Ii(c,s,t) and each auxiliary opcode word being designated Ii+l(c,s,t) where i = 0,1,2..., Ii(c) is a conditional control field, Ii(s,t) are control fields Ii+l(c) is an auxiliary control field including information for setting a processor register; means for decoding a conditional opcode word Il(c,s,t) during a first interval (i.e., i+l=2) and an auxiliary opcode word I2(c,s,t) during a second interval (i.e., i+2=3); means for fetching and storing a register control field (XSR, XSL) during the second interval, the pipelined digital processor BEING
CHARACTERIZED BY
at least one processor section responsive to some of the decoded fields I2(c,s,t) during a third interval for setting the register during the third interval if the condition is met and for disabling control of setting the register during the third interval if the condition is not met.

7. A pipelined digital processor operating in response to a plurality of control fields in each opcode word of a sequence of opcode words, each conditional opcode word being designated Ii(c,s,t) and each normal opcode word being designated Ii+l(l,m,..s,t) where i = 0,1,2..., Ii(c) is a conditional control field, Ii(s,t) are control fields, Ii+l (s) is a normal control field including information for identifying a destination for the processing result W3;
means for decoding a conditional opcode word Il(c,s,t) during a first interval(i.e., i+l=2) and a normal opcode word I2(l,m,..s,t) during a second interval (i.e., i+2=3);
means for transferring and writing a result w3 during a third interval, the pipelined digital processor BEING
CHARACTERIZED BY
at least one processor section responsive to the decoded normal control field I2 during the third interval for writing the result w3 during the third interval if the condition is met and for disabling the control of the writing of the result w3 during the third interval if the condition is not met.