JPS5999552A - Microcomputer - Google Patents

Abstract

PURPOSE:To perform fast instruction execution without requiring fetch of any instruction by providing a storage device which is stored successively with instructions stored in an instruction register. CONSTITUTION:The storage device 6 which is stored with execution instruction from an instruction queue register 1 is provided. A negative-directional relative jump instruction is stored in the instruction register 4. A code signal 30 indicating this relative jump instruction is applied to a PLA8 and a load signal is sent out of the PL8 to an address counter 7. At this time, the sum of the address of the storage device 6 stored with the current relative jump instruction and the discounted value of the relative value field of the instruction register 4 is applied to another input terminal of the address counter 7. Therefore, when the load signal 22 is applied to the address counter 7, instructions stored in the storage device 6 are read out successively and executed to perform high speed operation without requiring fetch of any instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcomputer that enables high-speed processing by reducing the average instruction execution time.

Conventional configurations and their problems In recent years, microcomputers have been widely used in various industrial fields, but as the fields of application have expanded, the demand for faster microcomputers has become stronger.

As a method to increase the instruction execution speed of a computer, the instruction prefetch method is widely used as a very effective method that parallelizes the instruction fetch operation and the instruction interpretation/execution operation, effectively reducing the instruction fetch time to zero and increasing the speed. has been done.

In FIG. 1, 1 is an instruction queue register, 2 is a prefetch counter, 3 is a prefetch control circuit, 4 is an instruction register, and 5 is a programmable logic array (hereinafter referred to as P
(written as LA).

The instruction queue register 1 has a first-in, first-out (hereinafter referred to as FIFO) structure, and instructions read from the storage location of the main memory indicated by the briefetch counter 2 are sequentially stored. On the other hand, an instruction is interpreted and executed by taking out one instruction from the instruction queue register 1, storing it in the instruction register 4, and interpreting it in the PLA 5.

Since the reading of instructions from main memory and the interpretation and execution of instructions are carried out simultaneously, as long as there are instructions in instruction queue register 1, instructions are executed continuously, and the instruction reading time becomes essentially zero. High-speed operation can be achieved.

However, since instructions are read out to the instruction queue register 1 by the briffetch counter 2 which counts up by 1, the effect described above is achieved sequentially in the order in which the instructions are stored in the main memory. limited to cases. In other words, if there is a jump instruction among the instructions and the instruction execution order changes, the instructions that have been read and stored in instruction queue register 1 up to that point will become useless, and the previously stored instructions will become useless. , the previously stored instruction queue must be canceled and a new instruction must be read. As a result, execution of the next instruction after the jump instruction is delayed until the instruction is read from main memory.

Specifically, when we investigated the frequency of instructions appearing in various programs, we found that jump instructions were the second most common instruction after load instructions, so the conventional temporary storage of programs using instruction queue register 1 was inefficient. . Especially the second
There are many cases where several instructions as shown in the figure are grouped together and executed repeatedly. In conventional devices, the execution speed decreases due to the fact that the fetch time is included in the instruction execution time, and the instruction execution speed decreases due to bus congestion caused by repeating useless instruction fetches many times. This also increased the efficiency of program execution.

OBJECTS OF THE INVENTION An object of the present invention is to provide a microcomputer that does not require repeated prefetching of the same instruction block for a loop operation in which several instructions are repeatedly executed as a unit. .

Structure of the Invention In order to achieve the above object, the present invention sequentially stores instructions stored in an instruction register in a newly provided storage device, and executes a jump instruction, especially a relative jump instruction in the negative direction. By configuring the system to sequentially read and execute the corresponding instructions from the storage device when executing the instruction, it is possible to eliminate the need to prefetch new instructions and enable high-speed instruction execution.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of essential parts of a microcomputer in an embodiment of the present invention.

In FIG. 3, 1 is an instruction queue register, 4 is an instruction register that temporarily stores execution instructions, 6 is a storage device, 7 is an address counter that instructs the storage device 6 to write and read instructions, and 8 is an instruction register. PLA decodes the instructions stored in register 4; 9 is an adder circuit; 10 is a gate circuit that supplies instructions from storage device 6 to instruction register 4; 11 is a gate circuit that supplies instructions from instruction queue register 1 to instruction register 4; It is.

The operation of the above configuration will be described in detail below. The operation of reading and storing instructions from the main memory into the instruction queue register 1 is exactly the same as in the conventional example.

First, an instruction to be executed is stored in the instruction register from the instruction queue register 1 through the gate 11, and is also stored in the storage device 6 at the same time. The storage operation in the storage device 6 is performed by PLA.
This is done by the write signal 21 (WRT) output from s, and at the same time the contents of the address counter 7 are also changed (+1).
and prepare for the next loading. Thereafter, each time an instruction is sequentially read out from the instruction queue register 1, the storage device 6
The data is written to the location where the address is incremented by (+1) by the address counter 7.

Here, a relative jump instruction in the negative direction is stored in instruction register 4,
That is, assume that an instruction to jump to an instruction n instructions earlier than the current instruction position is stored.

A code signal 30 from the instruction register 4 indicating that it is a relative jump instruction is applied to the PLAs, and an o-code signal 22 is applied to the PLAs.
(LOAD) is output from the PLAs and sent to the address counter 7. At this time, the input terminal of the address counter 7 contains the address of the storage device 6 storing the current relative jump instruction and the value 3 of the relative value field of the instruction register 4.
Since the value added with 1 is applied, when the load signal 22 is input, the address counter 7 is set to the added value. The relationship between the address counter 7 and the contents of the storage device 6 at this time will be explained using FIG. 4. FIG. 4(a) shows the state immediately before the load signal 22 is applied to the address counter terminal, and FIG. 4(b) shows the state after the load signal 22 is applied.

Until the jump instruction is executed, the instructions are stored sequentially as shown in FIG. 4(a), and the value of the address counter 7 at that time is pJ. At this time, when an instruction called "JMP-3" that causes a relative jump by 3 in the negative direction is executed, the next instruction to be executed becomes instruction A.

However, in the conventional case, instruction A, instruction B, instruction C2,
...and I had to fetch the instruction.

In this embodiment, instead of performing a brief fetch, the storage device 6
As shown in FIG.
By setting N-3 from N-3, the command is extracted. Generally, the relative jump value of a negative direction relative jump instruction is given in complement representation, so the addition circuit 9 can be used to calculate the new value of the address counter 7, and there are no numerical limitations.

Then, the execution instruction after executing the negative direction jump instruction is not supplied from the instruction queue register 1, but is supplied from the storage device 6 via the gate 10 via the signal line 23, and is sent to the address counter 7 by the read signal (RD double signal 20). (
+1) Sequentially reads instructions into the instruction register 4 and executes them.

In FIG. 4, the relative jump value is -3 and 7, but this may generally be -n and the value of the address counter 7 at that time will be N-n.

According to this embodiment, as described in "2" below, the instruction queue register 1
A storage device 6 is provided to sequentially store instructions for reading instructions from the instruction register 4, and after executing a negative direction pair jump instruction, the instructions are sequentially read from the storage device 6 and executed. It is possible to process instructions at high speed without performing unnecessary brief fetches for loop processing.

In this embodiment, the instructions are read from the instruction queue register, but the operation is exactly the same as in this embodiment even when the queue depth of the instruction key, -(/ register is zero, that is, there is no instruction queue register. It is clear that the same effect can be obtained by doing this.

Effects of the Invention As described below, the present invention sequentially stores and stores instructions stored in an instruction register in a storage device.

When an instruction, especially a relative jump instruction to the negative opposite direction, is executed, the instructions are sequentially read from the storage device and executed, thereby eliminating the need to repeatedly prefetch the same instruction block. It can execute commands at high speed, and its effects are comparable to those of a dog.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of a conventional microcomputer, Fig. 2 is a diagram showing an example of a program, Fig. 3 is a block diagram of main parts of a microcomputer according to an embodiment of the present invention, and Fig. 4 is the same. FIG. 3 is a diagram showing the operation of a microcomputer. 4...Instruction register, 6...Storage device,
7...Address counter, 8...P'L
A, 9...Addition circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Scope of Claims] A storage device that sequentially stores instructions executed by a computer, an address counter that indicates write and read positions in the storage device, an instruction register that temporarily stores instructions that the computer executes, and the instruction register. a programmable logic array for decoding the instructions stored in the memory device; an adder circuit for adding the relative jump code of the relative jump instruction stored in the instruction register and the value stored in the address counter; means for supplying an instruction to the instruction register, and when the programmable logic array decodes a relative jump instruction in a negative direction, the output of the adder circuit is stored in the address color, and from then on the A microcomputer characterized in that instructions are supplied from a storage device to the instruction register.