JPS5852265B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, and more particularly to a data processing device suitable for processing vector instructions that use array vectors of data as operands.

In order to process the above-mentioned vector instructions in a general-purpose data processing device, it is not possible to sufficiently meet the demand for high-speed calculation.

Conventionally, the processing of such vector instructions has been met by using a processing device dedicated to vector instruction processing.

However, today, there is a long-awaited demand for a data processing apparatus that can process vector instructions at a speed that satisfies demands even in data processing apparatuses oriented for general purposes.

However, a second object of the present invention is to provide a data processing device that enables high-speed processing of vector instructions even in a general-purpose data processing device.

Another object of the present invention is to provide a device for detecting whether or not an operand is a vector that is used continuously based on an address increment value, in order to process vector instructions at high speed. The object of the present invention is to speed up access to the operands of vector instructions by loading the operands into a vector buffer, and reading the operands from the buffer memory when the operands are used intermittently.

To this end, the main feature of the present invention is that, in addition to the memory means, instruction control means, and arithmetic means included in a general-purpose data processing device, the present invention includes vector instruction control means for decoding vector instructions and controlling the number of vector operations.

The memory means in the present invention stores instruction words and operands, and the instruction control means reads out the instruction words from the memory means and decodes them.

The instruction control means further causes the arithmetic means to perform an operation according to the decoded instruction when the instruction is other than a vector instruction.

However, if the decoded instruction is a vector instruction, subsequent control is deferred to the vector instruction control means.

The vector instruction control means decodes vector instructions and controls the number of vector operations under control from the instruction control means, and causes the operation means to perform vector operations accordingly.

Therefore, although the means controlled by the arithmetic means differs depending on whether the instruction is a vector instruction or not, the arithmetic means is shared by all instructions.

Another feature of the present invention is that the invention has a register that stores an address of a vector operand given by a vector instruction and an increment value of the operand address;
It is possible to process vector instruction operations at high speed by detecting whether or not the operands are consecutive based on the increment value, and if they are consecutive, controlling the operands in advance using a chapter vector buffer. I have to.

The present invention will be explained in detail below using one example.

FIG. 1 shows an example of a processing apparatus according to the present invention.

1 is an instruction control unit, 2 is an arithmetic unit, 3 is a storage control unit, 4 is a main memory 5 is a vector instruction control unit, and 6 is a maintenance control unit.

We will now briefly describe the processing flow for ordinary commands other than vector commands.

The command word is stored in the main memory 4, and is taken into the command control unit 1 via the storage control unit 3.

Thereafter, the instruction control unit 1 decodes the instruction and calculates the operand address, and the arithmetic unit 2 reads the operand and executes the operation of the instruction.

Reading of the operands takes place via the storage control unit 3.

The present invention is effective for processing vector instructions that use a large area in the main memory 4 as an operand.

Vector instruction word processing is the same as normal instruction word processing.
The command control unit 1 takes in command words and decodes the commands.

When the instruction is recognized as a vector instruction by decoding, subsequent instruction control is performed by the vector instruction control unit 5, which is the core of the present invention.

FIG. 2 shows the format of the vector instruction 101 in this embodiment.

The instruction code 102 is given a certain instruction code (F34 in this embodiment) in the case of a vector instruction as well, as in the case of a normal instruction word.

Count specified general register register number R1 is general register GR
The contents of the general-purpose register indicated by R1 represent the initial count of 107 for the vector,
The content of the general-purpose register indicated by R1+l represents the operation length 108 of the G1 vector.

The vector command designation general-purpose register number B2 also indicates the number of the general-purpose register, and the vector command part 110 of the contents of this general-purpose register and the vector command data part indicated by D2 are added in an addition operation 112 to become a vector command code 111. Become.

This vector command code 111 indicates the type of vector operation code (addition operation, multiplication, division, inner product operation, etc.).

The address vector command general register number R3 indicates a general register number, and the address of the address vector 114 is specified by the address 109 of the address vector in the contents of this general register.

In this embodiment, the address vector 114 is composed of three operand vector table addresses.

The three are the first operand vector table address 11.
5, second obland vector table address 116,
A third operand vector table address 117 is shown.

These indicate the address of the vector table for each operand.

In the example of FIG. 2, the second operand is illustrated, but the same applies to the case of the first operand and the third operand.

The address indicated in second operand vector table address 116 points to second operand vector table 118 .

The second operand vector table 118 is composed of the second operand start vector address 119c [2 operand address increment value 120].

The second operand start vector address 119 indicates the start address of the second operand vector 121.

Also, the second operand address increment value is 120
indicates the pitch used for the vector of the second operand.

For example, in this embodiment, if l words - 4 bytes and the address indicates a byte address, if the value of the second operand address increment value 120 is 4, the second operand vector is used with l word pitch, and 8
Then the second operand vector is used with a two-word pitch.

The second operand vector of this vector instruction is not necessarily used from the beginning, and each vector is not necessarily used consecutively.

The vector element address first used in the second operand vector of a vector instruction is the vector initial count 107 multiplied by the second operand address increment value 120 by the multiplication operation 113, plus the second
This is the result of adding the operand head vector address 119 in operation 122.

In the example of FIG. 2, the elements of the second operand vector 121 are shown from 1 to n, but the arrow indicates that the first vector element used is 5.

FIG. 3 shows how a vector instruction is decoded by the instruction control unit 1 in this embodiment.

When the instruction word is entered in the instruction register 201 and the instruction is decoded, and the decoder 202 decodes it as a vector instruction, first, the general-purpose register number indicated by B2 passes through the multiplexer 203 and is stored in the general-purpose register 204. The vector command part which is the contents of is read out and stored in the register 20.
Set to 6.

Also, 1) the value indicated by 2 is set as is in the register 205, added to the contents of the register 206 in the adder 207, set in the register 208 as a vector command code, and sent to the vector command control unit 5 via L4. .

Next, the general-purpose register number indicated by R3 is passed through the multiplexer 203, the contents of the general-purpose register 204 are read out, set in the register 206 as the address of the address vector, and then set in the register 208, and L1
4 to the vector command control unit 5.

Finally, the contents of general-purpose registers indicated by R1 and R1+1 are set in register 206 as vector initial count and vector operation length, respectively, and register 206 is set as vector initial count and vector operation length.
08. It is sent to the vector command control unit 5 via L4.

One of the central elements of the present invention is the vector instruction control unit 5, and FIG. 4 shows a more detailed block diagram showing one embodiment of the present invention.

The decoding information of the vector instruction decoded by the instruction control unit 1 is sent via L4 to the vector instruction control unit 5 for further detailed decoding.

First, among the information sent from the instruction control unit 1, a vector command code is sent to the decoder 402 through the input register 401.

The vector initial count is set from the human power register 401 to the vector power want register 404.

The vector operation length is also set from the input register 401 to the vector operation length register 405.

These are used to count the number of vector operations and control termination.

The address of the address vector is once set from the manual register 401 to the vector address register 408, passes through the address adder 410, passes through the storage control unit interface controller 412, and issues a memory request to the storage control unit 3 via L6. It will be done.

This read data is an address vector as understood from FIG. 2, and is set in the register 415 by the storage control unit 3 via L13.

This data is the first. Second. It is set in each of the vector address registers 408 as the third operand vector table address.

These values are again sent to address adder 401, storage control interface controller 412 . A memory request is issued to the storage control unit 3 via L6.

This read data is an operand vector table, and is sent from the storage control unit 3 to the register 4 via L13.
Set to 15.

The operand vector table is composed of an operand start vector address and an operand address increment value.

Among these, the operand address increment value is sent from the register 415 to the arithmetic unit increment face controller 403, is also transferred to the register 401, and is set in the vector address increment register 409.

The operand start vector address is sent to the arithmetic unit interface controller 403 together with the vector initial count in the vector count register 404, and from there these three data are sent to the arithmetic unit 2 via L5.

The details of the calculation unit 2 will be omitted, but like the calculation unit of a well-known general-purpose large digital computer, it includes an adder,
It consists of shifters, multipliers, byte arithmetic units, work registers, etc.

Here, the data sent from the vector instruction control unit 5 is multiplied and added, and the results are sent to the vector instruction control unit 5 via L14.

Data enters the manual register 401 and is then set into the vector address register 408.

There are three operand pect tables, 11th, 2nd, and 3rd, and the above operation is repeated for each.

The address increment register 409 stores increment values of the operand vector address for the first, second, and third operands.

When these values are set in the register, the address continuity detector 411 determines that if the increment value is 4 in single precision (l word) operation, it is considered as continuous address, and if the increment value is 8 in double precision (2 word) operation, it is considered as continuous address. latches 416, 417, and 418 are set for the first, second, and third operands, respectively.

i1% The second and third operand addresses are stored in the vector address register 408, and the sum of these and the contents of the vector address increment register 409 is passed through the memory control unit ink face controller 412 and sent to the operand via L6. It is sent to the storage control unit 3 as a request.

Although the details of the storage control unit 3 will be omitted, it is composed of an address translation mechanism, a high-speed small capacity memory (buffer memory), etc., similar to the storage control unit of a general-purpose large digital computer.

An important point of the present invention is that when issuing an operand request from the vector instruction control unit 5 to the storage control unit 3, if the addresses are consecutive, latches 416 to 418
is set, the vector buffer 413,4
14, and if the addresses are non-contiguous, a buffer memory is used.

For example, taking the second operand as an example, whether or not the addresses are consecutive is reflected in the latch 417.

Using this, when addresses are continuous, the data in the main memory 4 is put into the first vector buffer 413 via the storage control unit 3, and requests are continued until the first vector buffer 413 is full.

When the arithmetic unit 2 requires an operand, the latches 416 to 418 are tested within the arithmetic unit 2, and if continuity is indicated, a read request is issued from the arithmetic unit 2 to the first vector buffer 413 to read the first vector. The contents of buffer 413 are read and sent to computing unit 2 via L5 through computing unit interface controller 403.

In FIG. 4, there are a first vector buffer 413 and a second vector buffer 414.

This is because the vector instruction in this embodiment has a three-operand format, two operands are used for fetching, and one operand is used for storing, and two of these operands exist as vector buffers for fetching.

These vector buffers are used for prefetching operand data, are read out when necessary for an operation, and are
5 to the arithmetic unit.

If the addresses are non-consecutive, the arithmetic unit 2 issues a request to the storage control unit interface controller 412 to send the operand address to the storage control unit 3,
If the operand is in the buffer memory, the operand is sent from the buffer memory to the arithmetic unit 2.

If the operand is not in the buffer memory, it is transferred from the main memory 4 to the buffer memory, and from there the operand is sent to the arithmetic unit 2.

Note that the main memory and buffer memory can be regarded as substantially one memory means.

The vector count register 404 is set with the vector initial count 107 shown in FIG. 2, and the vector operation number register 405 is set with the vector operation number 108 shown in FIG.

Each time one operation is completed, the contents of the vector count register 404 are incremented by 1 by a counter 406, and compared with the contents of the vector operation number register 405 by a comparator 407.

The comparator 407 compares them, and if the contents match, a signal is sent to the arithmetic unit via the arithmetic unit interface controller 403 and L5 to control the end of the arithmetic operation.

The counter 406 output is the vector count register 404
is set to update the contents of the register 404.

As described above, according to the present invention, by adding a decoder for decoding a code for commanding vector instruction operations and a device for controlling the number of vector operations to a data processing device that processes general-purpose instruction words, data array vectors can be processed. It becomes possible to process vector instructions that use .

Also, if the operands to be used are consecutive, a dedicated vector buffer is used to perform the pre-fetch, and if they are not consecutive, access to the operands can be made faster by using buffer memory (or main memory). It becomes possible.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of a data processing device showing one embodiment of the present invention, and FIG. 2 is a schematic diagram showing the relationship between the vector instruction format, various registers, and operands in this embodiment.
FIG. 3 is a block diagram showing one embodiment of the main device of the present invention, and FIG. 4 is a more detailed block diagram showing one embodiment of the most main device of the invention. Figure 1: 1... command control unit, 2...
... Arithmetic unit, 3... Memory control unit,
4...Main memory, 5...Vector instruction h control unit. Fig. 4; 402... decoder, 404...
...Vector count register, 405...Vector operation number register, 406...Counter,
407...Comparator, 408...Vector address register, 409...Vector address increment register, 410...Address adder, 411...・Address continuity detector,
413 and 414...Vector buffer.

Claims (1)

[Scope of Claims] 1. A memory means storing instruction words and operands, an arithmetic means, connected to the memory means and the arithmetic means, and decoding the instruction word read from the memory means, and decoding the instruction word as a vector instruction. If the instruction is other than the instruction, the instruction control means is connected to the instruction control means and the operation means for controlling the operation means, and the instruction control means is connected to the instruction control means and the operation means in order to cause the operation means to perform the operation according to the instruction. Since the instruction decoded by the control means is a vector instruction, the above-mentioned vector instruction control means controls the arithmetic means in order to cause the arithmetic means to perform a vector operation according to the vector instruction; The vector instruction control means includes means for instructing the arithmetic means to perform a vector operation in accordance with the vector instruction from the instruction control means, and means for instructing the arithmetic means to perform the vector operation based on the vector instruction from the instruction control means. 1. A data processing device comprising: vector operation number control means for controlling readout of operands for processing and controlling the number of vector operations. 2. Consisting of a memory means storing instruction words and operands, an instruction control means, a vector instruction control means, and an arithmetic means, the instruction control means reads out an instruction word from the memory means and decodes it, and the instruction word is When a vector instruction is specified, subsequent control is passed to the vector instruction control means, and when a vector instruction is specified, the calculation means is made to perform an operation according to the instruction, and the vector instruction is executed. The control means takes over the above control from the instruction control means and decodes the vector instruction and controls the number of vector operations, and also detects whether or not the operands are continuous based on the instructions given from the vector instruction, and determines whether the operands are continuous. In this case, the operand is loaded in advance from the memory means into a dedicated vector buffer, and the operation means reads the operand from the vector buffer and performs vector operation under the control of the vector instruction control means. A data processing device characterized in that it reads operands from the memory means and performs vector operations.