JPS58169247A - High-speed instruction reading system - Google Patents

Abstract

PURPOSE:To speed up jump processing without any contention of a data bus, by reading a jump instruction out of a program storing means on the basis of a jump destination address outputted from a jump-destination address holding means by a switching means when a jump condition is satisfied. CONSTITUTION:An instruction address selector IAS is connected to an instruction memory IM. This selector IAS selects an address for reading the memory IM from an instruction counter register ICR, instruction address register IAR, or initial setting address register IR and the output of the memory IM is set in an instruction register IR. This set instruction is decoded by a decoder DEC and when it is a jump instruction, the jump-destination address is stored in the register IAR without being outputted to the data bus DBUS. Thus, jump processing is speeded up without any contention of the data bus.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a high-speed instruction reading method for a sequential processing microprocessor, and in particular, to a high-speed instruction reading method for a jump instruction when reading an instruction from a memory in which the instruction is stored. This invention relates to a high-speed instruction reading method for a sequential processing type microprocessor.

■ Prior Art and Problems For example, as shown in Figure 1, a microprocessor has an instruction memory IM in which instructions are stored, and an instruction memory IM in which instructions output from the instruction memory IM are set. - A register ta and an instruction run counter register IOA are provided in which an address for reading data from the instruction memory IM is set. The address set in the instruction counter register IOR by the incrementer INO is successively incremented by 1, and the instructions are successively read from the instruction memory IM. This instruction is set in the instruction register IR via the data bus DBUS, and this instruction is sent to the decoder D.
I? According to the result, data etc. are read out from a memory (RAM, not shown) to registers R1, 4, . . . and arithmetic processing is performed by an arithmetic unit ALU.

Note that the address for accessing the memory (RAM), etc. is created by this command processing and is sent out via the address bus input BU8 after being set in the register B1 group.

In this way, a high-speed microphone processor that independently controls the instrafsilon memory IM in which instructions are stored and the external or internally built-in memory (RAM) that can be written to and read from data etc. has the following features. A problem exists.

That is, when executing a jump such as a branch instruction (JUMP) in an instruction in the instruction memory IM,
Since the jump address (branch destination address) in this instruction is stored in the intraframe counter register OR via the data bus DBUS, the data bus DBUS is dedicated during that time, so the arithmetic unit ALU is There is a problem that processing such as calculation cannot be executed using .

For example, the following program ? R0 Chidori-R.

When executing the program JUMP XXXX, registers R2 and R
An instruction to add the contents of 1 and set it in register R,
Since both JUMP instructions must use the data bus DBUS, two or more steps are required.

G) Purpose of the Invention The purpose of the present invention is to solve these problems by setting the jump instruction to the address of the instruction memory without using the data bus, thereby avoiding contention on the data bus. An object of the present invention is to provide a high-speed instruction reading method for a sequential processing type microphone processor, which enables high-speed processing.

(4) Structure of the Invention In order to achieve this object, the high-speed instruction reading method of the present invention includes a microprogram storage means for storing microprograms arranged in processing order, and a register for indicating the execution address of the mosquito microprogram. In a microprocessor equipped with a micro sequencer section,
A jump destination address holding means for setting a jump destination address, an address holding means for setting a read address that is not a jump destination address, and a switching means are provided, and a jump condition is decoded using an instruction advance read method, and at the same time the jump destination address is set to the jump destination address. The jump instruction is efficiently executed by loading the jump instruction into the destination address holding means and reading the jump instruction from the microprogram storage means using the jump destination address output from the jump destination address holding means by the switching means when the jump condition is satisfied. Features.

■ Invention 051! Example An embodiment of the present invention will be described based on diagram R2.

In the figure, the same reference numerals as in other figures indicate the same parts, and IA8 is an instruction address selector that selects the address for reading one instruction from the memory IM.Instruction counter register l0R1 Initial setting address register 0ONIT, Instructions
This is to select which of the address hot dis- tae^B will appear first. Further, Gl-Gl is a gate.

Here, the initial setting address register 0ONT is used to store the first instruction necessary for data processing in the infrasilon memory I.
This is a register in which an initial setting address for reading from M is set, and the instruction address register IAR is a register in which a jump destination address is set.

Now, in FIG. 2, - Usually, the address set in the initial setting address register 0ONT by an appropriate means is first set in the instruction address selector IA.
8 selectively outputs the instruction, thereby reading the instruction from the instruction memory IM, setting the read instruction in the instruction register IR, decoding it in the decoder DEC, and performing the operation in the same manner as in the case of FIG. Processing is performed.

The initial setting address selected and output from the instruction address selector IAS is incremented by 1 by the incrementer INO and set in the instruction counter register IOR. The instrafsilon address selector IAS then outputs the address set in the instrafsilon counter register IOR, thereby instructing the instrafsilon memory 1. Instructions are sequentially read from M, and data processing is performed sequentially.

However, as a result of decoder DEO decoding the instruction set in instruction register IR...1,
If this is related to a JUMP instruction, this jump destination address is stored in the infrastructural address register AR without outputting it to the data bus DBU8. In the next step, the instruction address selector Ijl outputs the jump destination address held in the instruction address register AR, and the instruction address IM is thereby read out. In this way, the instruction is immediately read from the jump destination address and executed.

This jump destination address is incremented by 1 by the incrementer INO and set in the instruction counter register OR, and then the instruction counter register OR is sequentially incremented by 1 again and the address set is used to set the instruction counter register OR. Mesori IM
Instructions are read from the , and arithmetic processing is executed based on these instructions.

Therefore, as mentioned above, R, + Melon - R1 J Color xXX What is the 5 program? Since it is possible to store the amplifier addresses at the same time, this can be done in l steps.

(0) Effects of the Invention According to the present invention, there is no need to use a data bus when transferring a jump instruction.Therefore, there is no need to transfer calculation data when transferring a jump instruction.
As a result, data processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 shows a conventional instruction reading system, and FIG. 2 shows a configuration of an embodiment of the present invention. In the figure, IM is in-strafsilon memory, IR is in-stock scene register, IOR is in-stock scene counter register, DEO is decoder, and INO is in-stock scene counter register.
is an incrementer, ALLJ is an arithmetic unit, IAR is an instrafsilon address register, OON'l is an initial setting address register, I^8 is an instrafsilon address selector, G3. ABO3 is an address bus, and DBU8 is a data bus. Patent Applicant Fujitsu Limited Representative Patent Attorney Ha Employed by Song

Claims (1)

[Claims] α) A microprocessor comprising a microprogram storage means for storing microprograms arranged in processing order and a microsequence unit having a register for indicating an execution address of the microprogram,
The jump destination address holding means sets the jump destination address, and the address holding hand R sets the read address at the jump destination address.A switching means is provided, and an instruction advance reading method is used to decode the jump condition and jump at the same time. The jump command is executed by loading the destination address into the jump destination address holding means and reading out the jump instruction from the microprogram storage means using the jump destination address output from the jump destination address holding means by the switching means when the jump condition is satisfied. A high-speed instruction reading method characterized by efficient execution.