JPS5998253A - Microprogram controller - Google Patents

Abstract

PURPOSE:To perform simultaneously the control and branching of a micro instruction, which is held in a control storage register, by providing a small- capacity address control storage device where a branch destination address is held and controlling this device. CONSTITUTION:In the initial stage of instruction execution, an address control counter 14 is set up in accordance with contents of a control storage register 11. According as the micro instruction is executed, contents of an address control storage 16 are selected through a selector circuit 17 when a branch address is required, and a control storage device 10 is accessed on a basis of contents of the device 16. When the device 10 is accessed, contents of a counter 14 are updated by one by an incrementer 15 to prepare for the read of a branch address to be used next from the control storage 16. Thus, since the branch address is not included in the micro instruction read out from the control storage device 10, the branching and the execution of the instruction are performed simultaneously without increasing the number of bits per one word of the control storage 10.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a microprogram controller.

[Technical background of the invention and its problems]

Control methods using microprograms are often used because of the miniaturization of devices and ease of design. A microprogram is usually stored in a read-only memory called a control memory, and is controlled by reading and executing predetermined contents from the control memory to realize a specified functional operation. In order to execute multiple microprograms in a predetermined order, a hardware configuration similar to that shown in FIG. 1 has conventionally been used.

That is, the microprogram stored in control memory C8I is read out according to the address indicated by address #8, and its contents are held in control memory register RC8R2. The contents of control storage register 2 are stored in decoder circuit DE
C3 and is also supplied to the selector circuit 4 as a branch address for the branch of the microinstruction. The decoder circuit 3 outputs a predetermined control signal based on the contents of the control register 2. The output of the selector circuit 4 is supplied to the control storage device 1 to read out the content to be executed next. The output of the selector circuit 4 is also supplied to a +1 adder (hereinafter simply referred to as adder 5) for incrementing by '1''. The output of adder 5 is held in microinstruction counter MIC6.

A stack register 5TK7 is provided for subroutine call control of the microprogram, and the contents of the microinstruction counter 6 are held in the stack register 7 every time a microinstruction of a subroutine call is executed. Normally, a stack of stacks can hold about 4 levels of addresses. The selector circuit 4 is used to control the address that accesses the control memory 1. Here, either the contents of the control memory register 2, the contents of the stack register 2, or the contents of the microinstruction counter 6 are selected and set as the access address. used as.

The format of a microinstruction (read out to the RC8R2) read and executed in such a hardware configuration is normally as shown in FIG. 2, FIG. 3, or FIG. 4.

In particular, in order to branch a microinstruction, the address field is necessary, and when the TYPE field is set to a certain value as shown in Figure 3, it is necessary to select the branch condition to select and the branch address (BRADH). , a microinstruction is assigned, or a dedicated field for branch address (C0NT
R0L) was used.

However, when the above conventional method is used, there are the following drawbacks. Using microinstructions in the format shown in Figure 4,
There is an advantage in terms of performance because execution and branching according to the microinstruction can be performed at the same time, but the word length of the microinstruction word is long.
The cost will be high. When microinstructions are stored in the format shown in Figures 2 and 3, the word length of the microinstructions is short.
It is advantageous in terms of cost because it is compact, but it is disadvantageous in terms of performance because branching and other processing cannot be done together.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and a small amount of address control device that holds the history V and branch destination addresses is added to the peripheral circuit of the control memory, and this is controlled. To provide a microblock control device which is disadvantageous in terms of cost and performance by simultaneously controlling and branching microinstructions held in a ntlJml8 self-memory register. With the goal.

[Delusion of invention]

In the conventional system, if a micro-branch and a micro-instruction are to be executed simultaneously, the micro-instruction format shown in FIG. 4 must be used, but the bit length of one word becomes long, resulting in high cost.

The present invention provides a small-capacity address control storage device that stores the branch destination' address, since the Sudeten to which a branch is executed in a micro-processor is from lWIJ to F of all steps. By controlling the
It is possible to control and branch microinstructions held in a control storage register at the same time.

This makes it possible to provide a high-speed and efficient microprogram control device.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using FIG. 5. FIG. 5 is a block diagram showing an embodiment of the present invention. In the figure, 10 is a control storage device that stores a microprogram, 1 is a register (control storage register) that holds microinstructions obtained from the control storage device #10, and 12 is a decoder, which is the control storage register 11. The output can be decoded and used as control signals to control various parts of the system. 13 is set by a selector circuit (SEL). The selector circuit 13 inputs an input to an address control storage counter AC8CT 14, which will be described later, to an incrementer 1.
It is provided to select whether to take the output from the control storage register 11 or the output from the control storage register 11. 14 is an address control storage counter (AC8CT), which holds an address for accessing an address control storage device 16, which will be described later. 15 is the address control storage counter 1
This is a circuit (+], ) for incrementing the address control memory counter 14 by '°1'.The address control memory device AC316 holds branch address information and outputs a value obtained by adding '°1' to the contents of the address control memory counter 14. This is read-only memory.

17 is a selector circuit. The selector circuit 17 is connected to the output of the address control storage device 16 and the stack register 2.
0 and the output of the microinstruction counter 19, respectively, and are provided so that any one of these can be selected and switched. 18 is an incrementer (ADD
), the address for accessing the control memory 1 is added by 1" and supplied to the microinstruction counter 19 or stack register 20. 19 is a microinstruction counter (MIC). 20 is a stack register ( S
It is called LIFO (Li5t In-Fi) and holds the return address from the micro subroutine.
Writing/reading is performed in the format rst Out ). In the embodiment of the present invention, up to four levels are provided.

The operation of the present invention will be explained below. Since the number of steps in which branches (including conditional branches) are normally performed by microinstructions is less than 10% of all steps, the present invention provides an address control storage device 16 with a walking capacity that holds branch destination addresses.
As mentioned above, by controlling this, the control and branch indicated in the control storage register 1 can be performed at the same time. That is, assuming that the capacity of the control memory is 8, it is sufficient for the address control memory 16 that holds branch addresses to have a capacity of 800 to IK words, which can cover the drawbacks of the conventional system.

Address control counter 14 is set up according to the contents of control storage register 11 at the initial stage of instruction execution. Following the execution of a microinstruction, when a branch condition is satisfied in a microbranch or a conditional branch, that is, when a branch address is required, the address control storage counter 14
Since the contents of the address control memory 16 have been read from the address indicated by , the contents of the address control memory 16 are selected via the selector circuit 17, and the control memory 10 is accessed based on the contents. When the control memory device 10 is accessed according to the contents of the address control memory 16, the incrementer 15 updates the address control memory counter 14 by °'1'' to prepare for reading a branch address to be used from the address control memory 16. Ru.

By doing this, the branch address is not included in the microinstruction read from the control memory unit 110 and executed, so the microbranch and its instruction can be executed simultaneously without increasing the number of bits per 1001 words of the control memory. Go,
Therefore, a high-speed microprogram control device can be realized.

〔Effect of the invention〕

As described above, according to the present invention, branch addressing and execution can be performed simultaneously without increasing the length of 9 bits per word of the control storage device, and an efficient microprogram control device can therefore be provided. This is also based on experimental data showing that the total number of branches in microprograms up to now is less than 10% of the total steps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional microprogram control device, FIGS. 2 to 4 are diagrams showing the format of a microinstruction word, and FIG. 5 is a block diagram showing an embodiment of the present invention. . 10... Control storage device (CCS), 11... Control storage register (RC8R), 13, 17... Selector circuit (SEL), 14... Address control storage counter (AC8CT), 16... Address Control Storage (Acs). Applicant's representative Patent attorney Takehiko Suzue Figure 2 TPY C0NTR0BITS Figure 3 TPY RCOND BRADDR Figure 4

Claims (1)

[Claims] a first control storage device in which a plurality of microinstructions constituting a microprogram are stored; a control storage register that holds the microinstructions obtained from the first control storage device and whose contents are executed; A second control memory device in which a branch destination address is stored; and an address to access the second control memory device only when a branch address is required according to the contents held in the control memory register. an address control memory counter to be set;
and a dart circuit that accesses the first control storage device based on contents obtained from the second control storage device when a microinstruction branch is performed.