JPS5920047A - Microprogram control system - Google Patents

Abstract

PURPOSE:To control a microprogram in an excellent way, by providing the 1st and the 2nd control memories, the 1st and the 2nd address switching sections, an adder and a control section and the like, and constituting the system so that the start address of the 2nd control memory is used selectively. CONSTITUTION:Control memories 2, 11, address switching sections 13, 15, control memory address register 4, adder 5 and a control section 14 and the like are provided. A memory 11 is provided with the 1st and the 2nd specific field. The 1st specific field stores a required processing routine, the 2nd specific field discriminates the content of the 1st specific field so as to use selectively the start address of the memory 11. Then, the microprogram control is attained without increasing the capacity in the direction of bit of the memory 11 and without increasing the capacity of the microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a microprogram control method used to access control memory in a microprogram for controlling a data processing device.

(Description of Prior Art) Regarding address control methods for control memory in microprogram control, conventional methods include methods for accessing control memory by decoding the operation code of the instruction register, and methods for accessing the control memory by decoding the operation code of the instruction register, and methods for controlling the address of the control memory in microprogram control. There is a method in which a second control memory is provided, and the first address of the side memory is assigned to the second control memory for each macro instruction word, and the second control memory is accessed depending on the operation code of the instruction word. He had been hired. In the latter case, when the second control memory is accessed, the start address of the corresponding instruction word in the control memory is read from the corresponding address.

The data processing device is controlled by accessing the control memory using this start address and executing microinstructions read from the control memory. However, these methods have the disadvantage that a very large capacity control memory is required because the start address is different for each macro instruction.

As a method to eliminate such drawbacks, the control memory is divided into data preparation routines and execution routines, so that macro instructions can commonly use each routine in the first control memory, and each routine is stored in the second control memory. There is a method of storing the start address of the routine for each macro instruction.

However, this method has the disadvantage that multiple addresses stored in the second control memory are included in each word provided for each macro instruction, and the capacity increases in the direction of the pits of the control memory. .

As explained above, the conventional methods have the disadvantage that the amount of hardware increases in any case.

(Detailed Description of the Invention) An object of the present invention is to provide control necessary for accessing the second control memory by the operation code of the instruction word, and further accessing a specific area of the second control memory in detail. When a macro instruction is executed,
bits of the second control memory by first reading the contents of the second control memory and then reading the necessary contents from the second control memory again according to the control of a specific field included in the read contents. To provide a data processing device configured such that the directional capacity can be reduced, and a microprogram can be stored and effectively utilized without increasing the capacity of a first control memory. be.

(Description of structure and operation of the invention) A data processing device for realizing the microprogram control method according to the present invention includes an instruction register, a first control memory, a microinstruction register, a control memory address register, and a second control memory. It includes a control memory, a read register, a first address switching section, a second address switching section, an adder, and a control section.

The instruction register is a register for holding instruction words. The first control memory is a memory for storing microprograms.

The microinstruction register is a register for holding microinstructions read from the first control memory. The control memory address register is a register that holds the address of the next microinstruction to be executed and supplies this address to the first control memory. The second control memory includes first and second specific fields, the first specific field stores the address of a necessary processing routine, and the second specific field stores the first specific field. It is configured to hold information for identifying the contents of the address and use this information to effectively select the necessary start address. The read register is a register for holding address information successively read from the first specific field of the second control memory.

The first address switching section selects at least one of the contents of the first specific field of the second control memory and the output direction of the read register for holding the contents of the first specific field. It is used to supply necessary address information to the control memory address register.

In order to read the contents of the first specific field of the second control memory, the second address switching section reads the operation code held in the instruction register and the contents of the second specific field of the second control memory. Necessary address information is selectively supplied to the second control memory according to the conditions determined by the above.

The adder is used to increment the address information set in the control memory address register by one and perform address addition. The control section is for controlling the first and @2 address switching sections based on instructions from the first and second control memories.

(Description of Examples) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram partially showing an embodiment of a data processing device for realizing a microprogram control system according to the present invention.

In Figure 1, 1 is an instruction register, 2 is a first control memory, 3 is a microinstruction register, 4 is a control memory address register, 5 is an adder, 1 is a second control memory, 12 is a @2 A read register for holding the contents of the first specific field in the control memory, c) a first address switching unit, c) a control unit, and c) a second address switching unit. The first control memory 2 is normally used when decoding a macroinstruction executed in a data processing device and executing a microinstruction in accordance with the macroinstruction. That is, when a macro instruction is executed, the signal line 13 is connected to the control memory address register 4.
The start address is sent from the first address switching section 13 via the first address switching section 13. Therefore, control memory address register 4
Address information for incrementing the address by 1 is sent from the adder 5 to the adder 5 via signal lines 401 and 403. In adder 5, signal line 501'! The increment information is sent to the address switching section 13 of $1 via "il". Then, the address incremented by +1 is again added to the control memory address register 4 from the first address switching section 13 via the signal line 131. At this time, the first address switching unit 1
3, the address information added from the adder 5 via the signal line 501, the start address transferred via the signal line 121, or the start address transferred via the signal lines 112 and 113. Control signal line 14
Select according to the control signal on 2.

Here, if address information to be added from adder 5 is selected, this address information is sent to control memory address register 4 as explained above. As a result, signal lines 401 and 402 are connected depending on this address information.
The first control memory 2 is accessed via the signal line 201, and the microinstruction stored at the above address is read into the microinstruction register 3 via the signal line 201. Normally, microinstructions are sequentially outputted from the first control memory 2 to the microinstruction register 3 and executed in accordance with the address information obtained by the adder 5.

Generally, when a macro instruction is executed, the macro instruction is first sequentially issued from an external main memory and held in the instruction register 1. Next, the first control memory 2 is accessed by the control memory address register 4, and a microinstruction indicating the last microinstruction step of the macroinstruction being executed is written on the output signal line 202 of the first control memory 2. When the output signal is being sent out, the control unit 1
4H respond. That is, the control unit 1
4 responds, the second control memory 11 is accessed via the second address switching section 15 depending on the operation code of the instruction word held in the instruction register 1.

Next, in order to explain the address switching operation in detail, one embodiment of the circuit configuration of the second address switching section 15 is shown in FIG. In FIG. 2, the second address switching unit 15
, and second switching circuits 41 and 42. Signal lines 101, 103 and signal lines 101, 102
via the first switching circuit 41 and the second switching circuit 41, respectively.
The operation code is sent from the instruction register 1 to the switching circuit 42. Therefore, the first and second switching circuits 41
At 42, Ol and l are added to the most significant bits of the input data, respectively. From the control unit 14 to the signal line 1
When the state of the control signal sent through 41 is 0,
The first switching circuit 41 selects the input data and connects the signal line 15 to the signal line 15.
1 and accesses the second control memory 11. On the other hand, when the state of the control signal sent from the control unit 14 via the signal line 141 is 1, the second switching circuit 42 selects the input data and sends it to the signal line 151, and the second control memory 11 selects the input data and sends it to the signal line 151. access. In the second control memory 11, the first specific field contains the first control memory 2.
, and an identification bit is stored in the second specific field. The identification bit identifies whether the start address is the start address of the instruction execution preparation routine or the start address of the instruction execution routine. If the start address is the start address of the instruction execution preparation routine, the second specific field is designated with state 1, for example, and if the start address is the start address of the instruction execution routine, the second specific field is For example, state 0 is specified. Therefore, if the first specific field represents the address of an instruction execution routine, state 0 will be designated. In this case, when a macroinstruction is executed and a microinstruction instruction to end the microinstruction step of the corresponding macroinstruction is sent to the output signal line 202 of the first control memory 2, the control unit 14 is notified of this and the control The contents of the second specific field of the second control memory 11 are sent to the section 14 via the signal line 114.

FIG. 3 is a block diagram showing an example of the circuit configuration of the control section 14 in FIG. 1. In FIG. 3, the control unit 1
4 comprises first and second AND gates 52 and 53 and a flip-flop 51. The flip-flop 51 is set depending on the content of the second specific field input to the wholesaler details 14 via the signal line 114, and the content of the second specific field is stored in the flip-flop 51. This flip-flop 51 is set when the state of the signal on the signal line 114 is 1, and is reset when the state of the output signal of the second AND gate 53 is 1. The second (7) A N D gate 53 opens only when a microinstruction step end instruction microinstruction of the macroinstruction appears on the signal line 202 and the flip-flop 51 is set. The states on 531 and 141 are 1, so the flip-flop 51 is reset via the signal line 531.

When a micro-step end r instruction micro-instruction of the macro-instruction being executed arrives on the signal line 202 and the output state of the flip-flop 51 built in the control unit 14 is 0, the first address switching unit 15 2, the state of the signal sent from the control unit 14 via the signal line 141 is 0.
It is.

In this case, the operation code is selected by the first switching circuit 41, thereby accessing the second control memory 11. Here, the second specific bit read from the second control memory 11 indicates an instruction preparation routine,
The state of the signal sent onto the signal line 114 is 1. On the other hand, the contents of the first specific field of the second control memory 11 are sent to the readout register 12 via signal lines 111 and 112' and stored in the readout register 12, and are also sent via signal lines 111 and 113. It is also sent to the first address switching unit 13. Signal line 114
When the state of the above signal is 1, the first address switching section 13 uses the control signal on the signal line 142 to switch to the signal line 111.
, 113 is selected. When the selection of the start address is completed, the start address selected via the first address switching unit 13 is input to the control memory address register 4.

Following the above operation, a selection signal is sent from the control section 14 to the second address switching section 15 via the signal line 141, and the state of the signal on the signal line 141 becomes 1. In this state, the second switching circuit 42 is selected and the second control memory 11 is accessed via the signal line 151. In this case,
The start address stored in the first specific field is sent to the read register 12 via signal lines 111 and 112 and is stored in the read register 12. Therefore,
When an output is sent from the first control memory 2 to the output signal line 202 and a microinstruction for selecting the read register 12 is sent to the control section 14, the signal line 142 is sent from the control section 14.
A selection signal is sent out via. Address information sent from the successive register 12 in response to this selection signal is applied to the first address switching section 13 via the signal line 121.

Therefore, the first control memory 2 is accessed via the control memory address register 4 according to the sent address information. In this way, the input of the first address switching unit 13 is selected for the microinstruction appearing on the output signal line 202 and added to the control memory address register 4, so that each step of the macroinstruction is executed. .

(Detailed Description of the Invention) As described above, the present invention includes an instruction register, first and second control memories, first and second address switching units, a continuation register, and a control memory address register. In a data processing device configured to include an adder, a microinstruction register, and a control unit, a second control memory is provided with first and second specific fields, and the first specific field contains necessary information. A second processing routine is stored.
By adopting a microprogram control method configured to identify the contents of the first specific field and selectively use the start address of the second control memory in the specific field, The effect of being able to perform microprogram control is to increase the size of the microprogram stored in the first control memory without increasing the bitwise capacity of the second control memory. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially showing an embodiment of a data processing device for realizing a microprogram control system according to the present invention. FIG. 2 is a block diagram showing an embodiment of the configuration of the second address switching section shown in FIG. 1. FIG. 3 is a block diagram showing one embodiment of the configuration of the control section shown in FIG. 1. 1...Instruction register 2, 11...Control memory 3.
...Microinstruction register 4...Control memory address register 5...Adder 12...Read register 13,
15...Address switching unit 14...Control unit 41
, 42...Switching circuit 51...Flip-flop 52, 53...AND gates 101-103, 111-114, 121, 13
1, 1.41. 142, 151, 401-403, 201-20
4, 411. 421, 501, 511, 531...Signal line patent applicant NEC Corporation agent Patent attorney Hisashi Inoro 1st figure 2nd figure 3rd figure sj+

Claims (1)

[Claims] an instruction register for holding instruction words; a first control memory for storing a microprogram;
a microinstruction register for holding a microinstruction read from the control memory of the first control memory; and a control memory address for holding an address of a microinstruction to be executed next and supplying it to the first control memory. a second control memory comprising a register, a first and a second specific field, and a readout 7 for holding address information read from the first specific field of said second control memory;
a register and said first register of at least said second control memory;
and the output of a read register for holding the contents of the first specific field, and select one of them, and supply necessary address information to the control memory address register. and an operation code held in the instruction register and the first address switching section of the second control memory in order to read the contents of the first specific field of the second control memory. a second address switching unit for selectively supplying necessary address information to the second control memory according to a condition determined by the contents of the second specific field;
an adder for incrementing address information set in the control memory address register by 1; and controlling the first and second address switching units based on instructions from the first and second control memories. A data processing device equipped with a control unit for controlling the first
The second specific field stores the address of a necessary processing routine in a specific field, holds information for identifying the content of the first specific field in the second specific field, and
A microprogram control system, characterized in that the start address of the first specific field in the control memory of the microprogram is configured to be selectable according to the processing routine.