JPS63153637A - Data processor - Google Patents

Abstract

PURPOSE:To improve the processing speed of a macroinstruction and to drastically reduce a microinstruction step by providing an operand address calculation circuit and using one microinstruction so as to calculate the operand address and to access the operand. CONSTITUTION:The operand address of the microinstruction is calculated and the operand address is given to a processing means 1 and a main storage control means 2 by an operand address calculation circuit 4. The processing means 1 reads and decodes the macroinstruction from a main storage device 3 storing in advance a program comprising macroinstructions via the main storage controller 2. The operand address calculation circuit 4 calculates the operand address of the macroinstruction and the operand is outputted to the processing means 1 and the main storage control means 2. Thus, one microinstruction is used to calculate the operand address and to execute the access of the operand.

Description

[Detailed Description of the Invention] [Summary] The present invention calculates an operand address and accesses the main memory based on the operand address when executing a macro instruction in a data processing device using a microprogram control method. In order to improve the processing speed, it is equipped with an operand address calculation circuit that calculates the operand address with one microinstruction, outputs the operand address to the processing unit, and simultaneously writes data to the corresponding operand address in the main memory. It is designed so that it can be accessed by

[Industrial application field]

The present invention relates to a data processing device that uses a microprogram control method to improve the processing speed of operand access.

When a data processing device executes a macro instruction, it is required to emulate the macro instruction at high speed. Therefore, one means for emulating macro instructions at high speed is to calculate and access operand addresses of macro instructions at high speed.

[Conventional technology]

As a data processing device in the prior art, there is one shown in FIG.

501 is a data processing device (hereinafter referred to as rcPUJ) which is the core of the computer system, and its basic architecture is a stored program control method and a microprogram control method. 510 is a microprocessor (hereinafter referred to as rMPUJ) that controls the execution of a program composed of macro instructions, and is realized by an LSI. A control memory 520 stores a microprogram composed of microinstructions, and is realized by a memory that can be read at high speed. This control memory 52
Out of 0, 521 is a microprogram routine that calculates the operand address of a macroinstruction, and is composed of microinstructions. A main memory control circuit 530 outputs a control signal 560 necessary for accessing (reading or writing) to the main memory device 502, which will be described later, in response to a memory request signal 519 from the MPU 510. 502
is the main storage device mentioned above, which stores a program composed of macro instructions and is realized by RAM. 553 is C
This is the macro instruction that the PU 501 is currently emulating.

554 is an operand of macro instruction 553.

540 and 541 are the CPU 501 and main storage device 502, respectively.
This is a data bus and an address bus provided between the

Next, the configuration of the MPU 510 will be explained.

511 is a microprogram counter (hereinafter referred to as rMPCJ) that indicates the address of the next microinstruction to be executed.
), and the value instructed by the MPC 511 indicates the address of the control memory 520. 512 is a sequence control circuit, and the value instructed by the MPC 511 indicates the address of the control memory 520.
The microinstruction read from the address at address 0 is decoded to generate various control signals. 513 is a work register (hereinafter referred to as rWRJ), which transfers macro instructions from the main memory 502 to the data bus 540. A register 551 that stores a BXD section (described later) of a macro instruction read into the WR 513 via the main memory control circuit 530, and an MPU
510 is a register 5 in which the value of the operand address calculated by the operand address calculation routine 521 is stored.
It consists of 52 etc. 514 is a general-purpose register (hereinafter referred to as rGRJ) in which various general data are stored; 515 is a logic operation unit (hereinafter referred to as rGRJ) that performs numerical or logical operations based on the data stored in GR 514 and WR 513; rALUJ).

The format of the macro instruction is shown in FIG. 4. 300 is an operation code section (rO
301 is a pace register designation part (hereinafter referred to as "B part"), 302 is an index register designation part (hereinafter referred to as "rX part"), and 303 is a displacement (hereinafter referred to as "10 part"). 0 or more, 301, 302, and 303, which respectively indicate ), are collectively called BXn bear - ζ knee 3 ('lil + on the way to the Maro meeting.

is an extension with various specifiers that are valid for certain macro instructions.

Operation of CPU 501 in such a configuration.

In particular, the calculation of the operand address and the access to the operand address will be mainly explained. It is assumed that the macro instruction has already been stored in the instruction register (not shown) of the MPU 510 from the main memory 502 via the data bus 540 and the main memory control circuit 530.

The MPU 510 decodes the 02 part 300 of the macro instruction, and when recognizing that it is an instruction that requires access to the main memory bag gi 502, sets the MPC 511 to the value of the start address of the operand access calculation routine 521,
The operand address calculation routine 521 is executed. Then, first, the BXD part of the macro instruction is read from the storage device 502 into the register 551 of the MPU 510 via the data bus 540 and the main memory control circuit 530, and the ALU
The operand address is obtained by adding the B part, the X part, and the D part using the WR 515, and the operand address is set in the register 552 of the WR 512.

Thereafter, based on the operand address set in the register 552, processing specified by the OF section 300 of the macro instruction 553, for example, in the case of a read instruction, a series of processing of reading data stored in the operand 554 and setting it in the general-purpose register 514. are executed sequentially using multiple microinstructions. When the processing of the macro instruction is completed, the next macro instruction is read from the main memory 502 and the same operation as described above is performed.

[Problem that the invention seeks to solve]

However, in such conventional data processing devices, when a macroinstruction read from the main memory requires access to the main memory, the operand consisting of multiple microinstructions stored in the control memory is first read out from the main memory. The operand address is calculated by the address calculation routine, and then the macro instruction is executed based on the operand address and the 02 part of the macro instruction, so the execution speed of the corresponding macro instruction does not require operand access. They are slower than macro instructions, and the operand address calculation routine must be incorporated into every microprogram routine that emulates macro instructions to prevent processing speed from slowing down, resulting in an increase in the number of steps in the microprogram. There were problems.

[Means for solving problems]

The present invention has been made in view of these conventional problems, and an object of the present invention is to provide a data processing device that can improve the execution speed of macro instructions.

The means includes processing means for reading, decoding, and executing macro instructions using micro instructions from a main memory device in which a program composed of macro instructions is stored in advance, and main memory control means for accessing the main memory device. The data processing device includes an operand address calculation circuit that calculates an operand address of a macro instruction and outputs the operand address to the processing means and main memory control means.

[Effect]

The operation of the present invention will be explained based on the principle block diagram of the present invention shown in FIG.

The processing means 1 reads macro instructions from the main memory 3 in which a program composed of macro instructions is stored in advance, via the main memory control device, and decodes the macro instructions. The operand address calculation circuit 4 calculates the operand address of the macro instruction and outputs the operand address to the processing means 1 and the main memory control means 2.

Therefore, operand address calculation and operand access can be executed with one microinstruction.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 shows a configuration diagram of a data processing device in an embodiment of the present invention. 200 is a data processing device (hereinafter referred to as rcPUJ) which is the core of the computer system, and has a microprogram control system and a stored blog. The basic architecture is a RAM control method.

211 is a microprocessor (hereinafter referred to as rMPUJ) which is composed of a plurality of macro instructions and controls the execution of a program stored in advance in the main memory 231, which will be described later.
) and is composed of LSI. 201 is a microprogram counter (hereinafter referred to as rMPcJ) that stores the address of the microinstruction to be executed next, and the address indicated by this MPC 201 is the address of the microprogram in the control memory 214, which will be described later. . Reference numeral 203 is a sequence control circuit that decodes a microinstruction read from an address in a control memory 214, which will be described later, and which is instructed by the MPC 201, and outputs various control signals.

A work register (hereinafter referred to as "rWR") 202 is composed of a plurality of registers.

Reference numeral 214 denotes the aforementioned control memory which stores a microprogram composed of microinstructions, and is constituted by a high-speed read/run memory. 22'0 is a microprogram routine corresponding to a predetermined macroinstruction, and is composed of a plurality of microinstructions 221. Said MPU21
1 and the operand address calculation circuit constitute the processing means 1 described in the claims.

22. This is an operand address calculation circuit corresponding to the operand address calculation circuit 4 described in the claims.

224 is a control circuit for the operand address calculation circuit 229, which receives the decode signal 2 from the sequence control circuit 203.
When 04 is input, various control signals necessary for calculating the operand address are outputted by a predetermined timer. 213
is a register that stores the BXD part of the macro instruction.

210 is a general-purpose register (hereinafter referred to as rGRJ) in which various general data are stored.

212 is an adder, which combines the BX part of the macro instruction stored in the GR 210 and the D part stored in the register 213.
The operand address is calculated by adding the values of the parts. 222 adds the operand address to the adder 21
This is an operand address register (hereinafter referred to as rOARJ) that inputs and holds an operand address from No. 2.

230 is a main memory control circuit corresponding to the main memory control means 2 described in the claims, and when a memory request signal 215 from the control circuit 224 of the operand address calculation circuit 229 is input, it is sent to the main memory device 231, which will be described later. Control signals 26 necessary for access (reading or writing)
This is a main memory control circuit that outputs 0. 202 and 203 are a data bus and an address bus, respectively, provided between the main memory control circuit 230 of the CPU 200 and a main memory device 231, which will be described later.

A main memory 231 stores a program composed of macro instructions and various data, and is composed of a RAM. 250 is a macro instruction to be emulated. 251 is an operand of a macro instruction. The BXD part of the macro instruction 250 is transferred from the main memory M231 to the register 213 via the data bus 203 and the main memory control circuit 230.
It is now loaded into . The instruction format of the macro instruction is the same as that shown in FIG.

The operation of the data processing device 200 having such a configuration will be explained, particularly focusing on calculation of an operand address and access to the main storage device 231 based on the calculated operand address. Note that the macro instruction 250 is stored in the main memory 23.
1 to an instruction register (not shown) of the MPU 211 via the data bus 203 and the main memory control circuit 230.

The MPU 211 decodes the OF portion of the macro instruction 250 and transfers execution to the microprogram routine 220 that emulates the macro instruction 250. Macro instruction 25
If 0 is an instruction that requires operand access, the microroutine 220 stores one microinstruction 221 that calculates the operand address, and this microinstruction 221 is input from the control memory 214 to the sequence control circuit 203. . Then, the sequence control circuit 203 outputs a decode signal 204 that causes the control circuit 224 in the operand address calculation circuit 229 to calculate the operand address.

When the control circuit 224 receives the decode signal 204, it outputs various control signals to target the BXD part of the macro instruction 250 as the main culprit t! read from the device 231 to the register 213 via the data bus 203 and the main memory control circuit 230, and
Macro instruction 250(7)B stored in register 213
The X section points to the GR210.The adder 212 adds GR(8) indicated by the D section of the register 213 and the B section stored in the GR210, and GR(χ) indicated by the X section. The operand address that is 0AR2
Output to 22. In this embodiment, after setting GR(B)+D to 0AR222, the contents of OAR222 and GR(X) are added and the result is set to 0AR222 again. lastly.

The operand address, which is the content of OAR 222, is set in WR 202 specified by microinstruction 221 and output to main memory control circuit 230.

Main memory control circuit 230 outputs an operand address to main memory N231 via control signal 260 and address bus 232. When the main storage device 1231 inputs the operand address and control signal 260, the operand 251
access. The data stored in the operand 251 is stored in a temporary register (not shown) in the operand address calculation circuit 229 via the data bus 203 and the main memory control circuit 230.

Therefore, according to this embodiment, one microinstruction 22
When only 1 is input, the operand address is set in the WR 202 and the operand is accessed.

After executing the microinstruction 221, the MPU 211 stores the operand address set in the WR 202 in the GR 210 if the macroinstruction is an instruction (LEA instruction) to set the operand address in the GR 210. Also, the main memory where the macro instruction is indicated by the operand address! 123
In the case of an instruction that sets the operand in step 1 to GR210, the contents of the temporary register are stored in GR210. In this way, it is possible to read from the operand and store it in the GR 210 using the same process as reading from a register.

〔Effect of the invention〕

According to the present invention, an operand address calculation circuit is provided,
Since the operand address is calculated and the operand is accessed using one microinstruction, the processing unit can read the operand and set the operand address to a general-purpose register using the next microinstruction. It is possible to improve the instruction processing speed and significantly reduce the number of microinstruction steps.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a data processing device showing an embodiment of the present invention, Fig. 3 is a block diagram of a conventional data processing device, and Fig. 4 is a block diagram of a macro instruction. It is a form. 1...Processing means 2...Main memory control means 3...Main memory device 4...Operand address calculation circuit data processing reward 1.

Claims (1)

[Claims] Processing means (1) for reading, decoding, and executing macro instructions using micro instructions from a main memory (3) in which a program composed of macro instructions is stored in advance;
3), in a data processing device equipped with a main memory control means (2) that performs access to the main memory control means (2), calculates an operand address of a macro instruction, and transmits the operand address to the processing means (1) and the main memory control means (2). 1. A data processing device comprising an operand address calculation circuit (4) that outputs an operand address.