JPH0471219B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a computer using a microprogram control system, the validity check of an effective address is performed by hardware rather than by a microprogram, and the entry address for error processing is set as one of the microprogram entry addresses. In the above, when the validity check determines that the entry address is invalid, the microprogram entry address is corrected by -1 so that the error processing entry address can be accessed immediately. This makes it possible to simplify the microprogram and speed up instruction control.

[Industrial application field]

The present invention relates to instruction control in microprogram control type computers, and in particular, when a half-word boundary restriction is specified for the effective address, the validity of the generated effective address is checked, and an unreasonable effective address is checked. The present invention relates to an error detection processing method for performing error processing when an address is generated.

[Conventional technology]

An overview of the conventional method will be explained with reference to FIG.

FIG. 4a conceptually shows the instruction control mechanism of a conventional microprogram controlled computer.

In the figure, 41 is an instruction register that holds microinstructions.

42 is a decoder that decodes the instruction code of a macro instruction and generates an entry address (in the control memory) of a microprogram that executes the macro instruction. This decoder can be configured as a jump table, for example.

43 is a control memory CS in which microprograms corresponding to each macroinstruction are stored.

44 is a microprogram MPU.

45 is a main storage device MS in which user programs are stored.

FIG. 4b is a flowchart showing the operation of the conventional example shown in FIG. 4a. The outline will be explained according to the steps in the figure.

The macro instruction set in the instruction register 41 is decoded by a decoder 42 to generate a microprogram entry address.

The control memory CS is accessed using the microprogram entry address, and the MPU executes the microprogram.

The MPU checks the validity of the effective address generated according to the microprogram. For example, if half-word boundary restrictions are specified, odd addresses are considered illegal.

If the effective address is valid, control of the microprogram corresponding to the macro instruction is executed and the process ends normally.

If the effective address is invalid, a microprogram for error handling is executed with reference to an error handling entry address table (not shown), and the program terminates abnormally.

[Problem that the invention seeks to solve]

In conventional microprogram control computers, the validity of the effective address was checked in the microprogram, which required time to execute several steps of macro instructions and required an entry address table for error handling. Therefore, there were problems in that the instruction control time became slow and the control memory became large.

[Means for solving problems]

In order to solve the above-mentioned problems with the conventional method, the present invention separates the validity check function of the effective address from the microprogram and implements it in hardware, thereby increasing speed and providing an entry for error handling when the effective address is invalid. By using the address immediately before the microprogram entry address as the address, the error processing entry address can be calculated with a simple calculation (-1 calculation) without using the error processing entry address table, and the error processing This allows the execution of microprograms for

FIG. 1 is a basic configuration diagram for explaining the principle of the present invention. In the figure, 11 is an instruction register in which macro instructions to be executed are set. A macro instruction consists of an instruction code section and an operand section.

12 is jump table (branch destination table)
The microprogram entry address and control information corresponding to the instruction code of the macro instruction are registered.

13 is a microprogram entry address, which indicates the start address of a microprogram that performs a function corresponding to the instruction code of the macro instruction.

Reference numeral 14 denotes control information that specifies parameters necessary for executing the macro instruction, such as the fetch format of the operand, and whether or not effective address calculation is necessary.

Numeral 14a is validity designation information that serves as a standard for checking the validity of an effective address, for example, information indicating whether half-word boundary restriction is designated.

15 is an address calculation circuit, which is a register specified by the operand of the macro instruction (not shown)
Based on the value of , calculate the effective address to fetch or store the operand.

Reference numeral 16 denotes a validity check circuit, which determines the validity of the effective address based on validity designation information 14a in the control information 14. If the effective address is invalid, "1" is subtracted from the microprogram entry address 13.

Reference numeral 17 denotes a control memory, in which an error processing entry address including a jump address to an error processing microprogram is set one place before the microprogram entry address.

[Effect]

The operation based on the principle of the present invention shown in FIG.
This will be explained using the flow shown in FIG.

The operation of the present invention will be explained according to the steps in the figure.

The fetched macro instruction is set in the instruction register 11.

The macro instruction is decoded and the entry address of the jump table 12 is obtained.

The jump table 12 is accessed using the entry address, and the microprogram entry address 13 and control information 14 are read.

Based on the control information 14, it is determined whether calculation of an effective address is necessary or not.

If it is necessary to calculate an effective address, the address calculation circuit 15 calculates the effective address.

The effective address is determined by the base register value (B) + index register value (X) + displacement D.

The validity check circuit 16 checks the validity of the effective address according to the validity designation information 14a. In this example, a half-word boundary restriction is specified, that is, the effective address should be an even address, so the validity check circuit 16 determines whether the least significant bit of the effective address is "1" or "0". is checked, and if it is “1”, it is determined to be invalid.

If the least significant bit of the effective address is "0" (=even number), the microprogram starting at the microprogram entry address corresponding to the macro instruction is executed.

If the effective address is invalid (=odd number), the validity check circuit 16 subtracts "1" from the microprogram entry address to return the address to the previous address and generate an error handling entry address.

The control memory 17 is accessed using the error processing entry address, and the error processing microprogram is executed.

〔Example〕

FIG. 3 shows the hardware configuration of one embodiment of the present invention. In the figure, 20 is an instruction address register IAR.

21 is an operand address register ADR.

22 is a main storage device MS in which user programs and data are stored.

Reference numeral 23 denotes an instruction code register OPR in which an instruction code (OP code) part of a macro instruction is stored.

24 is a jump table that holds microprogram entry addresses and control information.

25 is a table output register.

26 is a validity check circuit.

27 is the operand (BXD) in the macro instruction
This is the operand register BXDR where the part is stored. The operand section consists of a base register address B, an index register address X, and a displacement D.

28 is a plurality of base registers BR.

29 is a plurality of index registers XR.

30 is the base address (B), index (X)
and displacement D to calculate an effective address.

31 is a microprogram MPU.

32 is a control memory CS. The address immediately before each microprogram entry address in the CS is an error handling entry address.

33 and 34 are internal buses.

In operation, the main memory device MS22 is accessed by the fetch address of the execution instruction (macro instruction) set in the instruction address register IAR20, and the instruction code part and operand part of the read macro instruction are transferred to the internal bus 33. The data is distributed and stored in the instruction code register OPR23 and the operand register BXDR27 via the .

The jump table 24 is accessed by the instruction code in the instruction code register 23, and the data of the corresponding table entry, that is, the microprogram entry address and control information, is read into the table output register 25.

On the other hand, one base register BR28 is selected by the base register address of the operand part data of the operand register BXDR27, and one base register BR28 is selected by the index register address.
One index register XR29 is selected.

The adder 30 adds the selected values of BR and XR,
The value of displacement D in BXDR27 is added to generate an effective address and stored in the operand address register ADR21.At the same time, the least significant bit LSB is added to the validity check circuit 26.
send to

The validity check circuit 26 checks that the validity designation information included in the control information in the table output register 25 specifies, for example, a half-word boundary restriction that prohibits half-word boundary access, and that the LSB of the effective address is On the condition that it is "1" (odd number), 1 is subtracted from the microprogram entry address in the table output register 25 to generate an error handling entry address, and the MPU 31
Transfer to. Also, the LSB of the effective address is “0”
(even number), the microprogram entry address is transferred to the MPU 31 without being modified.

The MPU 31 controls the control memory according to each address transferred from the validity check circuit 26.
The CS 32 is accessed and a macro instruction microprogram or an error processing microprogram is executed according to each address.

If the effective address is valid, access to the main memory device MS22 is executed according to the effective address of the operand address register ADR21.

〔Effect of the invention〕

According to the present invention, since the validity check of the effective address and the generation of the error processing entry address are executed by the hardware circuit, the number of microprogram steps is reduced.

Furthermore, since the error processing entry address can be determined from the microprogram entry address by a simple calculation, the speed can be increased compared to the conventional method using an error processing entry address table.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a flow diagram showing the operation of the present invention, FIG. 3 is a block diagram of one embodiment of the present invention, and FIG. 4 is an explanatory diagram of a conventional system. In Figure 1, 11: instruction register, 12: jump table, 13: microprogram entry address, 14: control information, 14a: validity designation information, 15: address calculation circuit, 16: validity check circuit, 17: control memory.

Claims (1)

[Scope of Claims] 1. Means for generating a microprogram entry address in a control memory and control information according to an instruction code of a macro instruction, and means for generating an effective address of an operand according to the control information. In a computer using a microprogram control system, the above control information is appended with validity designation information that serves as a standard for determining the validity of the effective address, and the validity of the effective address generated by the means for generating the effective address is added to the control information. The microprogram entry address in the control memory is checked based on the above validity designation information, and if it is determined to be invalid, a means is provided to change the corresponding microprogram entry address to the previous address. Immediately before the address, set an entry address for error handling when the effective address is invalid, and if the effective address is valid, give the microprogram entry address to the control memory and execute the macro instruction. An error detection processing method in instruction control characterized in that when an effective address is invalid, an error processing entry address immediately before the microprogram entry address is given to execute error processing.